JP2005251828A - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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JP2005251828A
JP2005251828A JP2004057207A JP2004057207A JP2005251828A JP 2005251828 A JP2005251828 A JP 2005251828A JP 2004057207 A JP2004057207 A JP 2004057207A JP 2004057207 A JP2004057207 A JP 2004057207A JP 2005251828 A JP2005251828 A JP 2005251828A
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insulating film
pad
copper
semiconductor device
copper pad
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Takeshi Hamaya
毅 濱谷
Masaji Funakoshi
正司 舩越
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

【課題】高速化、微細化に伴い、配線材料にCuを採用すると共に拡散工程の複雑化及び拡散工程数の増大する中で、この拡散工程数を軽減すると同時に、CuパッドとAuボールを安定に接合できる半導体装置を提供することを目的とする。
【解決手段】層間絶縁膜１、Cuパッド部３、Cuパッド上を含む半導体素子上に成膜する絶縁膜６、Cuパッド上の絶縁膜から突き出たCuビア４から構成された外部電極に、荷重と超音波振動を印加することにより、Cuビア４が折れ、Cu新生面を出す。これによってAuボール７をCuパッド部３に接合することで解決できる。
【選択図】図１

Description

本発明は、絶縁膜に覆われたCuパッドに拡散プロセス工程のCu配線またはCuビアを用いて上記絶縁膜から突き出させてCuに直接、金属細線を接合できる構造に特徴を有する半導体装置に関するものである。
半導体素子への微細化、高速化の要求に伴い、半導体素子の配線材料として0.13μmプロセス当たりからAlと比較して比較的低抵抗であり配線遅延も少なく、更に耐エレクトロマイグレーションが向上できるCuが採用されて来ている。しかしながら、Cuは容易に酸化し、非常に硬い酸化銅を生成する。その結果、ボンディング工程でCuパッドにAuボールを押し潰しても酸化銅は破壊されずCuパッドとAuボールは接合できない。
そこで従来は、拡散プロセス工程において、Cu配線形成後に絶縁膜を成膜し、その後Cuパッド部の絶縁膜を除去し且つ清浄化する。そしてその上にAuとの接合性に優れた金属膜層のアルミパッドを形成した構造によって、安定した接合を行うことができている。
また別の方法として、半導体チップの電極に金スタッドバンプを形成し、この場合基板であるが、銅電極の表面をプラズマ処理して清浄化且つ活性化し、プラズマ処理した銅電極の表面に金スタッドバンプを接合することができる。
なお、この出願の発明に関する先行技術文献情報としては、例えば特許文献１が知られている。
特開2001−60602号公報
しかしながら、従来の技術では下記のような課題がある。
Cuパッド上にアルミパッドを形成して接合する手法では、Cu配線形成後に絶縁膜を全面形成し、その後Cuパッド部の絶縁膜を除去して、アルミパッドを形成後絶縁膜を形成しなければならず、Cu配線形成後の工程数が非常に多い。近年微細化に伴い、拡散工程が複雑且つ増大している中で、拡散リードタイムが長くなり、拡散コストも増大することは、大きな課題となる。
また半導体チップの電極に金スタッドバンプを形成する手法では、プラズマ処理工程が必要であり、プラズマ装置も必要となる。この手法においても、上述同様に、組立リードタイムが長くなり、組立コストも増大する。
上記の課題を解決するため本発明は、拡散工程において、最上層から１層下層のCu配線で形成したCuパッドと、前記Cuパッド上にCuビアと最上層のCu配線を用いて、細い棒状のCuを形成し、絶縁膜から前記棒状のCuを突出させたことを特徴とする半導体装置である。
従来、最上層配線でCuパッドを形成後、絶縁膜を形成し、その後Cuパッド部の絶縁膜を除去して、アルミパッドを形成後絶縁膜を形成していたが、アルミパッドの代わりに前記Cuビアと最上層のCu配線を用いて、細い棒状のCuを形成し、このCuパッドに従来のボンディング（荷重と超音波振動）で前記細い棒状のCuを折ることにより、Cuの新生面を露出させて接合するため、従来大きかったパッド表面状態の影響が小さく、安定した接合が実現できる。
また本発明は、従来からのワイヤーボンディングで接合ができるため、装置の変更及び追加が一切不要である。
本発明の半導体装置及びその製造方法は、拡散工程における、最上層から１層下層のCu配線で形成したCuパッドと、前記Cuパッド上にCuビアと最上層のCu配線を用いて、細い棒状のCuを形成することにより、アルミパッドを形成する工程と絶縁膜を形成する工程及びそれぞれのマスクを削減することができ、コスト削減及び拡散リードタイム短縮を実現できる。また従来の接合方法である、ワイヤーボンドで接合することができるため、装置の変更や追加は一切不要であり、更には細い棒状のCuを折って新生面を露出させるため、パッド表面の影響が小さい。
以下、半導体装置及びその製造方法について図面を参照しながら説明する。
先ず半導体装置について説明する。図１は本発明の一実施形態を示しており、図１(a)はボンディング前における本発明のチップのCu電極断面図、図１(b)はボンディング後の本発明のチップのCu電極断面図を示す。１は各配線層の層間絶縁膜、２は最上層から１層下層のCu配線、３はCu配線層で形成されたパッド部、４は配線と配線を接続するCuビア、５は最上層のCu配線、６はチップを保護する絶縁膜、７は圧着させたAuボール、８はキャピラリー、９は金ワイヤーを示す。図１に示すように、本発明の実施形態は、最上層から１層下層のCu配線で形成したCuパッドの上に、Cuビアと最上層のCu配線を用いて、細い棒状のCuを形成し、パッド部分の層間絶縁膜を除去して突出させ、更に絶縁膜を形成後も細い棒状のCuを絶縁膜からも突出させる。前記棒状のCuを突出させたCuパッド上にAuボールによりワイヤーボンドされる時に、荷重と超音波振動により前記棒状の突出させたCuを折ることによって、新生面を露出させて、CuパッドとAuボールの接合が可能となる。
図２、図３に本発明における半導体装置の製造方法を示す。
図２(a)に示すとおり各配線工程が形成され、最上層から２層下層のCu配線形成後、層間絶縁膜１を化学気相堆積法（以下CVDと略す）を用いて形成する。次に図２(b)に示すとおり、層間絶縁膜１にドライエッチング、Cuめっき、化学的機械研磨（以下CMPと略す）を用いてCu膜を平坦化し、Cuビア４及び最上層から１層下層のCu配線２形成と同時にCuパッド３を形成する。次に図２(c)でCuパッド上を含む半導体素子上にCVDを用いて絶縁膜１を形成する。その後、図３(d)で、Cuビア４及び最上層配線５を図２(b)の工程と同様に形成する。次に図３(e)に示すとおり、Cuパッド３上の絶縁膜１のみドライエッチングで除去し、細い棒状のCuを形成する。次に図３(f)でCuパッド３上を含む半導体素子上にCVDを用いてチップ保護用の絶縁膜６を形成する。但し絶縁膜６を形成後も細い棒状のCu は突出させて置く。
本発明の半導体装置は、配線材料にCuを用いた半導体素子に搭載したCuパッドに安定したボンディングを行うことができることから、高速化、高機能化が現在最も求められる情報通信機器に搭載する半導体素子として有用である。
本発明の一実施形態における半導体装置を示す図 本発明の一実施形態における半導体装置の製造方法を示す断面図 本発明の一実施形態における半導体装置の製造方法を示す断面図
符号の説明
１ 層間絶縁膜
２ 最上層から１層下層のCu配線
３ パッド部
４ Cuビア
５ 最上層のCu配線
６ 絶縁膜
７ 圧着Auボール
８ キャピラリー
９ Auワイヤー

Claims (3)

  1. 平坦な銅パッドと、前記銅パッド上に形成された絶縁膜と、前記銅パッドと接続され、且つ前記銅パッド上にビア状に突出した複数の銅突起を備え、前記銅突起が前記絶縁膜中を通り抜け、前記絶縁膜より先端が突き出たことを特徴とする半導体装置。
  2. 前記銅パッド形成後に全面に絶縁膜を形成する工程と、前記銅パッド上の前記絶縁膜に前記銅パッドに達するビア状の穴を空ける工程と、前記ビア状の穴に銅を埋め込んで平坦化する工程と、前記銅パッド上のみ前記絶縁膜を除去することにより前記銅パッドと接続され、且つ前記銅パッド上にビア状に突出した複数の銅突起を形成する工程と、全面に絶縁膜を形成し、前記絶縁膜より先端が突き出たビア状に突出した複数の前記銅突起で構成されたことを特徴とした請求項１記載の半導体装置の製造方法。
  3. 前記銅パッド上に、荷重および超音波振動を印加することにより、前記銅パッド上の前記絶縁膜より先端が突き出たビア状に突出した複数の前記銅突起を折る工程と、前記銅突起を折ることにより銅の新生面が露出し接合できることを特徴とした請求項１記載の半導体装置の接合方法。
JP2004057207A 2004-03-02 2004-03-02 半導体装置およびその製造方法 Pending JP2005251828A (ja)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010103533A (ja) * 2008-10-21 2010-05-06 Taiwan Semiconductor Manufacturing Co Ltd ディッシング効果を低減する接合パッドの設計
JP2012160633A (ja) * 2011-02-02 2012-08-23 Lapis Semiconductor Co Ltd 半導体装置の配線構造及びその製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010103533A (ja) * 2008-10-21 2010-05-06 Taiwan Semiconductor Manufacturing Co Ltd ディッシング効果を低減する接合パッドの設計
KR101107806B1 (ko) 2008-10-21 2012-01-25 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 감소된 디싱 효과를 가지는 본드 패드 설계
JP2012160633A (ja) * 2011-02-02 2012-08-23 Lapis Semiconductor Co Ltd 半導体装置の配線構造及びその製造方法

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