CN101728371A - 集成电路结构 - Google Patents

集成电路结构 Download PDF

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CN101728371A
CN101728371A CN200910179462A CN200910179462A CN101728371A CN 101728371 A CN101728371 A CN 101728371A CN 200910179462 A CN200910179462 A CN 200910179462A CN 200910179462 A CN200910179462 A CN 200910179462A CN 101728371 A CN101728371 A CN 101728371A
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joint sheet
patterning
integrated circuit
silicon
circuit structure
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CN101728371B (zh
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余振华
邱文智
吴文进
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开一种集成电路结构，包括一半导体芯片，其还包括一第一表面以及一第一图案化接合垫，露出于第一表面。第一图案化接合垫包括彼此电性连接的多个部位以及位于其内的至少一开口。集成电路结构还包括一介电材料，填入开口的至少一部分。本发明提供的集成电路结构能够降低大型接合垫制作中的碟化效应，因而改善接合垫的品质。

Description

集成电路结构
技术领域
本发明涉及一种集成电路，尤其涉及一种接合垫(bond pad)的设计。
背景技术
自集成电路的发明创造以来，由于各个电子部件(即，晶体管、二极管、电阻、电容等等)的集成度(integration density)持续的改进，使半导体业持续不断的快速成长发展。主要来说，集成度的改进来自于最小特征尺寸(minimum feature size)不断缩小而容许更多的部件整合至既有的芯片面积内。
这些集成度的改进实质上是朝二维(two-dimensional，2D)方面的，因为集成部件所占的体积实际上位于半导体晶片的表面。尽管微影(lithography)技术的精进为2D集成电路制作带来相当大的助益，二维空间所能拥有的密度还是有其物理限制。这些限制其中之一在于制作这些部件所需的最小尺寸。再者，当更多的装置放入一芯片中，需具备更复杂的电路设计。
另外的一个限制因素来自于当装置的数量增加时，装置之间内连线(interconnection)的长度及数量也明显增加。
为了解决上述限制因素，已开始创作三维(3D)集成电路(three-dimensional integrated circuit，3DIC)。在典型的3DIC制造工艺中形成二个具有集成电路的晶片。接着连同装置对准而接合上述晶片。硅通孔电极(through-silicon vias，TSV)可用于两晶片上装置的内连接。
传统接合两晶片的方法包括胶合法(adhesive bonding)、直接覆铜法(direct copper bonding)及直接覆氧化物法(direct oxide bonding)。一般所使用的直接覆铜法中，每一晶片具有铜接合垫露出于晶片的表面，并通过施加高压来接合两晶片，使铜接合垫彼此接合例如，在彼此上方接合两个芯片。
由于客制化(customized)电路需求，有些需要大的接合垫。这些大的接合垫面临一些问题。图1示出经由大型接合垫进行两晶片的接合。芯片2包括大型接合垫4而芯片6包括大型接合垫8。接合垫4及8是以直接覆铜法进行接合。在接合垫4及8的制造中，通常需进行化学机械研磨(chemicalmechanical polish，CMP)。然而，由于接合垫4及8较大，接合垫4及8的各自区域属图案密集区。因此，当进行CMP制造工艺以形成接合垫4及8的期间，会发生碟化效应(dishing effect)，使接合垫4及8中心区域磨除的比边缘区域来得多。
可从图1发现到碟化效应所引发的各种问题。首先，接合可靠度受到严重的影响。由于碟化效应，只有少部分的接合垫4及8彼此接合，因而接合不佳。第二，由于接合面缩小，导致流经接合面的电流降低。这些问题导致大型接合垫的设计目的失效，因而有待解决。
发明内容
本发明一实施例提供一种集成电路结构，包括一半导体芯片，其还包括一第一表面以及一第一图案化接合垫，露出于第一表面。第一图案化接合垫包括彼此电性连接的多个部位以及位于其内的至少一开口。集成电路结构还包括一介电材料，填入开口的至少一部分。
本发明另一实施例提供一种集成电路结构，包括一半导体芯片，其还包括：一第一表面；一第一图案化接合垫，露出于第一表面，其中第一图案化接合垫包括彼此电性连接的多个部位以及位于这些部位之间的多个开口；多个连接结构，以连接第一图案化接合垫的这些部位；一半导体基底，位于第一图案化接合垫下方；一硅通孔电极，位于半导体基底内且电性连接至第一图案化接合垫；以及一实心接合垫，露出于第一表面。实心接合垫小于第一图案化接合垫。
本发明又另一实施例提供一种集成电路结构，包括：第一及第二半导体芯片。第一半导体芯片，包括一第一表面以及一第一图案化接合垫，露出于第一表面。第一图案化接合垫包括彼此电性连接的多个部位以及位于这些部位之间的多个开口。第二半导体芯片，包括一第二表面以及一第二图案化接合垫，露出于第二表面，且经由直接接合而接合至第一图案化接合垫。
本发明的特征的优点包括降低大型接合垫制作中的碟化效应，因而改善接合垫的品质。
附图说明
图1示出传统具有大型接合垫的接合，其中大型接合垫发生碟化效应。
图2示出根据本发明实施例的剖面示意图，其中大型接合垫内具有开口。
图3A至图3D示出图2中接合垫的平面示意图。
图4A示出图3A中接合垫沿4A-4A’线的剖面示意图。
图4B示出图3B中接合垫沿4B-4B’线的剖面示意图。
图5示出根据本发明实施例的多个硅通孔电极连接至相同大型接合垫。
图6示出芯片正面对正面(face to face)接合。
图7示出芯片正面对背面(face to back)接合。
图8A至图8C示出从相同的接合芯片对中不同面的剖面示意图。
其中，附图标记说明如下：
公知
2、6～芯片；
4、8～大型接合垫。
实施例
10、110～半导体芯片；
20～半导体基底；
24～内连结构；
26～介电层；
30、30’～金属线；
32、32’～介层窗；
40、50、501、502、503～硅通孔电极；
42、52、62、72、152～接合垫；
521～部位；
522～内连部位；
53～开口；
64、74～重布局线。
具体实施方式
以下说明本发明实施例的制作与使用。然而，必须了解的是本发明提供许多适当的实施例的发明概念，可实施于不同的特定技术背景。述及的特定实施例仅用于说明以特定的方法来制作及使用本发明，而并非用以局限本发明的范围。
本发明实施例提供一种改良的接合垫结构，其适用于半导体芯片中。本发明一实施例中，接合垫的一较佳设计为内部具有狭缝/开口，以降低局部的图案密度。其具有将碟化效应最小化的优点。以下将说明本发明诸多实施例，可使用于，例如，直接金属对金属接合(direct metal-to-metal bonding)的技术背景。然而，本发明任何的实施例亦可应用于其他技术背景。
图2示出一半导体芯片10，其为晶片的一部分。半导体芯片10包括半导体基底20，其可由一般公知的半导体材料所构成，例如硅、硅锗等等。集成电路(未示出)形成于半导体基底20的表面，其中集成电路包括互补式金属氧化物半导体(complementary metal-oxide-semiconductor，CMOS)晶体管以及其他装置，诸如电容、电阻等等。集成电路上方为内连结构24，其包括多个介电层26，包括但不限定为金属层间介电(inter-metal dielectric，IMD)层、保护(passivation)层等等。内连结构24内连至下方的集成电路，且将集成电路与硅通孔电极(TSV)40及50连接至各自的接合垫42及52，其形成于半导体芯片10的正面。在整个说明叙述中，半导体芯片10靠近内连结构24的一侧(此处为顶侧)称为正面，而与其相对的一侧则称为背面。
如所公知一般，IMD层26可由低介电常数(low-k)材料所构成，举例来说，其k值低于2.5。金属线30及介层窗(via)32形成于介电层26内，且可为利用公知镶嵌(damascene)制造工艺所构成的铜，或是由其他金属所构成，例如铝、钨、银等等。
在本发明一实施例中，半导体芯片10包括硅通孔电极40及50，其延伸贯穿基底20，且将正面的特征元件(feature)内连至基底的背面。硅通孔电极40电性连接至接合垫42，而硅通孔电极50电性连接至接合垫52，其中硅通孔电极40及50皆形成于半导体芯片的正面。接合垫42及52同时形成，因而由同一材料所构成。在本发明一实施例中，接合垫42小于接合垫52(对于上视而言)。硅通孔电极50的截面积大于或等于硅通孔电极40(对于上视而言)。因此，接合垫42及硅通孔电极40可用于传送一相对小的电流，例如信号电流，而接合垫52及硅通孔电极50可用于传送一相对大的电流，例如供电电流。接合垫42未与接合垫52电性连接。
在本发明一实施例中，接合垫42为内部不具有狭缝或开口的实心接合垫。另一方面，接合垫52内部具有图案化的开口。图3A至图3D为接合垫52的诸多可能的设计平面示意图。在整个说明叙述中，图3A至图3D所示的接合垫52称为图案化接合垫。图3A及图3B所示的接合垫52皆包括被开口53所隔开的部位521及连接部位521的内连部位522。内连部位522与部位521由同一层所构成。
另一方面，图3C示出另一实施例，其中接合垫52包括多个被开口53所隔开的分离部位521。在接合垫52所处的膜层中，分离的部位521之间并无电性连接，而是通过下方介层窗及金属线来电性连接。在一实施例中，如图2所示，分离的部位521之间的电性连接是通过金属线30’及介层窗32’。金属线30’及介层窗32’可由接合垫52正下方的一金属化层(或位于保护层内)所构成，其可为一顶部金属化层(一般称为Mtop)或一重布局(redistribution)层。在其他实施例中，分离的部位521之间的电性内连接可通过底部金属化层(一般称为M1)至顶部金属化层Mtop之间任何的金属化层。在图3A至图3C中所示的结构中，接合垫52可视为一完整的接合垫，亦即任何接合垫部位521的连接等同于其他部位的连接。
可结合图3A、3B及3C所示实施例而构成另一实施例，在该结合的实施例中，一些部位521通过多个群组的内连部位522进行内连接，而不同群组的内连部位522并未彼此连接。图3D示出一实施例，其中每一行的部位521是内连接的，而行与行之间是不连接的。此外，至少一位于下方的介层窗32’连接至每一行，且这些介层窗32’市内连接的(如图2所示)。
请参照图3A至3D，至少局部的开口53填有介电材料。请参照图2，至少开口53的下半部填有多个介电层26中顶层的材料。
采用图3A或图3B所示的实施例时，会有一个以上的介层窗32’连接至接合垫部位521，如图2所示。另外，由于部位521已内连接，仅有一个介层窗32’(请参照图2)形成且连接至单一的接合垫部位521(请参照图3A及图3B)。然而，采用图3C或图3D所示的实施例时，每一分离的部位521必须有一下方的介层窗32’与其连接。否则没有介层窗32’的部位521将无法连接至其他部位。
需注意的是依据图2所示的剖面图，接合垫52的剖面可为本体接合(solid bond)，如图4A所示，或是一连续的接合垫，如图4B所示。图4A是图3A的平面中沿4A-4A’线的剖面示意图，而图4B示出图3B的平面中沿4B-4B’线的剖面示意图。
整个半导体芯片10(也可能是整个晶片)中，临界横向尺寸(thresholdlateral dimension)较佳为既定的，且任何横向尺寸大于临界横向尺寸的接合垫的图案化设计示出于图3A至图3D。举例而言，当任何横向尺寸(宽度及/或长度)小于临界横向尺寸的接合垫时，接合垫为实心的。
请参照图2，在半导体芯片10的背面上可形成接合垫62及72。在一实施例中，接合垫62及72的规格分别相似于接合垫42及52。因此，接合垫72可大于接合垫62。此外，接合垫72的结构本质上可相同于图3A至4B所示的结构。重布局线64及74可形成于基底20的背面，以将接合垫62连接至硅通孔电极40，且将接合垫72连接至硅通孔电极50。重布局线64及74的制作细节为公知技术，在此不再予以赘述。在另一实施例中，可将硅通孔电极40及50以铜柱的形式(同样作为接合之用)露出于基底20的背面来取代接合垫62及72。
图5示出另一实施例，以利用一个以上硅通孔电极电性连接至一相同的接合垫来取代利用单一硅通孔电极内连接位于基底20两相对侧的特征元件。需注意的是虽然图5中所示的接合垫52具有分离的部位，其可具有图3A、3B、3C或3D所示的结构。另一方面，虽然图5中所示的接合垫72为一连续片，其也可具有图3A、3B、3C或3D所示的结构。因此，硅通孔电极501、502及503可通过接合垫52或72任一者而电性内连接。另外，相似于金属线30及重布局线74(请参照图2)的金属线及/或重布局线可用于内连接硅通孔电极501、502及503。
图6示出半导体芯片正面对正面(face to face)接合。半导体芯片110可具有相同或不同于图2至图5的结构。
采用本发明实施例的益处在于大型接合垫52及152的制作无须担心发生碟化效应(发生于制作接合垫52及152时所进行的化学机械研磨)。如此一来，接合垫52及152的表面更为平坦。当进行直接接合时，接合垫52有更多的部分可与接合垫152直接接合，使接合更为稳靠而能够传导更大的电流。图8A、8B及8C示出接合垫52及152之间三种可能的接合方式剖面示意图，其中由于不同的剖面位置(请参照图4A及4B)及/或接合垫52及152具有相同或不同的结构而呈现出不同的图面。
以上所述的实施例也可应用于正面对背面(face to back)接合，如图7所示。再者，同样可应用于背面对背面(back to back)接合(未示出)。本领域普通技术人员可理解其中各自的结构。
本发明实施例具有许多的有益的特点。在接合垫内形成开口/狭缝，接合垫局部的图案密度会降低，至少可降低甚至完全消除CMP所引发的碟化效应。而本发明实施例无需额外制造工艺步骤，使本发明能够在不增加制造成本的情形下获益。
虽然本发明已以较佳实施例公开如上，然其并非用以限定本发明，任何所属技术领域中具有通常知识者，在不脱离本发明之精神和范围内，当可作更动与润饰。再者，本发明之保护范围并未局限于说明书内所述特定实施例中的制造工艺、机器、制造、物质组成、装置、方法及步骤，任何所属技术领域中具有通常知识者可从本发明公开内容中理解现行或未来所发展出的制造工艺、机器、制造、物质组成、装置、方法及步骤，只要可以在此处所述实施例中实施大体相同功能或获得大体相同结果皆可使用于本发明中。因此，本发明之保护范围包括上述制造工艺、机器、制造、物质组成、装置、方法及步骤。

Claims (15)

1.一种集成电路结构，包括：
一第一半导体芯片，包括
一第一表面；
一第一图案化接合垫，露出于该第一表面，其中该第一图案化接合垫包括彼此电性连接的多个部位，且该第一图案化接合垫内包括至少一开口；以及
一介电材料，填入该开口的至少一部分。
2.如权利要求1所述的集成电路结构，其中该第一图案化接合垫包括多个内连线，电性内连接所述多个部位，且其中所述多个内连线与所述多个部位由同一层所构成。
3.如权利要求1所述的集成电路结构，其中所述多个部位为分离的，且其中该集成电路结构还包括多个内连线，电性内连接所述多个部位，且其中所述多个内连线与所述多个部位由不同层所构成。
4.如权利要求1所述的集成电路结构，还包括：
一硅通孔电极，位于该第一半导体芯片内，其中该硅通孔电极连接至该第一图案化接合垫；以及
一附加的图案化接合垫，位于该第一半导体芯片的该第一图案化接合垫的一相对侧，电性连接至该硅通孔电极。
5.如权利要求4所述的集成电路结构，其中该附加的图案化接合垫包括彼此电性连接的多个附加的部位，其中该集成电路结构还包括一附加的硅通孔电极相邻于该硅通孔电极，其中该硅通孔电极与该附加的硅通孔电极均将该第一图案化接合垫的所述多个部位的其中一个连接至该附加的图案化接合垫的所述多个附加部位的其中一个。
6.如权利要求1所述的集成电路结构，还包括一实心接合垫，与该第一图案化接合垫位于同一层位而未与其电性连接，其中该实心接合垫小于该第一图案化接合垫。
7.如权利要求1所述的集成电路结构，还包括：
一第二半导体芯片，包括
一第二表面；以及
一第二图案化接合垫，露出于该第二表面，其中该第二图案化接合垫包括彼此电性连接的多个附加的部位，且其中该第二图案化接合垫内包括至少一开口，而该第一图案化接合垫经由直接接合而接合至该第二图案化接合垫。
8.一种集成电路结构，包括：
一半导体芯片，包括
一第一表面；
一第一图案化接合垫，露出于该第一表面，其中该第一图案化接合垫包括彼此电性连接的多个部位以及位于所述多个部位之间的多个开口；
多个连接结构，以连接该第一图案化接合垫的所述多个部位；
一半导体基底，位于该第一图案化接合垫下方；
一硅通孔电极，位于该半导体基底内且电性连接至该第一图案化接合垫；以及
一实心接合垫，露出于该第一表面，其中该实心接合垫小于该第一图案化接合垫。
9.如权利要求8所述的集成电路结构，其中该半导体芯片包括：
一第二表面，相对于该第一表面；
一第二图案化接合垫，露出于该第二表面，其中该第二图案化接合垫包括彼此电性连接的多个附加的部位；以及
一附加的硅通孔电极，位于该半导体基底内且相邻于该硅通孔电极，其中该硅通孔电极与该附加的硅通孔电极均将该第一图案化接合垫的所述多个部位的其中一个连接至该第二图案化接合垫的所述多个附加部位的其中一个。
10.如权利要求9所述的集成电路结构，其中所述多个连接结构由构成该第一图案化接合垫或该第二图案化接合垫的一层所构成。
11.如权利要求9所述的集成电路结构，其中所述多个连接结构由位于该第一图案化接合垫与该半导体基底之间的一金属化层或位于该半导体基底与该第二图案化接合垫之间的一层所构成。
12.一种集成电路结构，包括：
一第一半导体芯片，包括
一第一表面；以及
一第一图案化接合垫，露出于该第一表面，其中该第一图案化接合垫包括彼此电性连接的多个部位以及位于所述多个部位之间的多个开口；以及
一第二半导体芯片，包括
一第二表面；以及
一第二图案化接合垫，露出于该第二表面，且经由直接接合而接合至该第一图案化接合垫。
13.如权利要求12所述的集成电路结构，其中该第一半导体芯片还包括：
一半导体基底，位于该第一表面下方；以及
一硅通孔电极，位于该半导体基底内，且电性连接至该第一图案化接合垫。
14.如权利要求12所述的集成电路结构，其中该第一半导体芯片还包括一实心接合垫，露出于该第一表面且未与该第一图案化接合垫电性连接，该实心接合垫小于该第一图案化接合垫，且其中该第二半导体芯片还包括一附加的实心接合垫，露出于该第二表面，该附加的接合垫接合至该实心接合垫。
15.如权利要求12所述的集成电路结构，还包括：
一第二图案化接合垫，位于该第一半导体芯片内，且位于该第一半导体芯片的该第一图案化接合垫的一相对侧；以及
多个硅通孔电极，位于该第一半导体芯片内，每一硅通孔电极将该第一图案化接合垫的所述多个部位的其中一个连接至该第二图案化接合垫的多个附加的部位的其中一个。
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