CN102569239A - 半导体封装体的接合结构、其制造方法及半导体封装体 - Google Patents

半导体封装体的接合结构、其制造方法及半导体封装体 Download PDF

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CN102569239A
CN102569239A CN2011104631748A CN201110463174A CN102569239A CN 102569239 A CN102569239 A CN 102569239A CN 2011104631748 A CN2011104631748 A CN 2011104631748A CN 201110463174 A CN201110463174 A CN 201110463174A CN 102569239 A CN102569239 A CN 102569239A
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金圣哲
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SK Hynix Inc
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Hynix Semiconductor Inc
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Priority claimed from KR1020110123017A external-priority patent/KR20120060147A/ko
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Abstract

本发明的实施例提供了一种半导体封装体的接合结构、其制造方法及半导体封装体。该半导体封装体的接合结构包括：配置为传输电信号的第一导电构件；以及配置为电连接至第一导电构件的表面并包括多个子接合垫的接合垫。

Description

半导体封装体的接合结构、其制造方法及半导体封装体
技术领域
本发明的实施例大体涉及一种半导体封装体及其制造方法，更具体涉及一种包括堆叠型半导体封装体的半导体封装体的接合结构。
背景技术
对电子产品小型化和高性能的需求随着对移动产品的需求增长而增长，因此对具有小尺寸和大容量的半导体存储器的需求增长。增加半导体存储器的存储容量的一个方法包括在一个半导体封装体中安装和装配多个半导体芯片。在此方法中，只可改变封装工艺来增加半导体存储器的存储容量。此外，增加存储容量在资金要求、研发以及开发时间方面具有很多好处。因此，半导体存储器制造商做出各种努力，试图通过具有安装在一个半导体封装体中的多个半导体芯片的多芯片封装体来增加半导体存储器的存储容量。
将多个半导体芯片安装在一个半导体封装体中的方法可包括在水平方向上安装多个半导体芯片以及在垂直方向上安装多个半导体芯片。由于电子产品的特性，为追求小型化，大多数半导体存储器制造商更优选多个芯片垂直堆叠并封装在其中的堆叠型多芯片封装体。作为堆叠型多芯片封装体的例子，已经提出使用硅通孔(though silicon via，TSV)的封装结构。使用TSV的封装体允许多个半导体芯片通过形成在各个晶圆级的半导体芯片中的TSV在垂直方向上物理和电性连接。
在使用TSV的传统堆叠型封装体中，具有TSV的半导体芯片和芯片垫通过诸如焊料的接合金属电性连接。然而，当该半导体芯片采用TSV堆叠时，TSV通过一个信号和一个链接被连接。因此，即使只有一个信号被切断，也会发生开路失效。因而，即使数千个信号中只有一个信号被切断，也将导致整个产品的失效。
发明内容
在一个实施例中，半导体封装体的接合结构包括：配置为传输电信号的第一导电构件，以及配置为电连接至该第一导电构件的表面并包括多个子接合垫的接合垫。
第一导电构件可包括TSV。全部或部分的子接合垫彼此可具有不同的高度。
接合结构可进一步包括提供在子接合垫的上表面上并将第一导电构件电连接至第二导电构件的接合构件。
接合构件可填充子接合垫的上表面上方的空间以及各个子接合垫之间的空间。
接合构件可包括各自形成在子接合垫的上表面上的多个子接合构件。
一部分的子接合垫可配置为电连接至第二导电构件，并且另一部分的子接合垫可配置为电连接至第三导电构件。
在另一实施例中，半导体封装体的接合结构的制造方法包括：在基板中形成导电构件，该导电构件配置为传输电信号；以及形成配置为电连接至该导电构件的表面并包括多个彼此间隔开的子接合垫的接合垫。
该方法进一步包括在接合垫的上表面上形成接合构件。该导电构件可包括TSV。该接合构件可包括焊料或者各向异性导电膜之一。
接合构件可包括各自形成在子接合垫的上表面上的多个子接合构件，其中该多个接合构件彼此间隔开。
形成接合垫可包括：在该基板上形成光致抗蚀剂图案，该光致抗蚀剂图案具有多个彼此间隔开的开口；通过在开口中埋入导电材料而形成导电材料层；在导电材料层的上表面上形成焊料层；以及移除该光致抗蚀剂图案，并且子接合垫和子接合构件可同时形成。
形成导电材料层或者形成焊料层可通过无电镀、电镀、真空沉积、溅射、化学气相沉积(CVD)、丝网印刷或涂覆来实施。
该方法可进一步包括在形成光致抗蚀剂图案之前在基板上形成种子层。
在另一实施例中，半导体封装体包括两个或更多个堆叠半导体芯片，每个半导体芯片配置为传输电信号并包括接合垫，该接合垫包括多个子接合垫，多个子接合垫配置为通过下半导体芯片的至少两个或更多个子接合垫与半导体芯片中的上半导体芯片电连接。
两个或更多个堆叠半导体芯片的每个半导体芯片可包括导电构件，其包括子接合垫并进一步包括TSV。全部或部分的子接合垫可具有不同的高度。
半导体封装体可进一步包括提供在子接合垫的上表面上的接合构件。
接合构件可填充子接合垫的上表面上方的空间以及各个子接合垫之间的空间。
接合构件可包括各自形成在子接合垫的上表面上的多个子接合构件。
下半导体芯片的子接合垫的一部分可配置为电连接至该上部半导体芯片，并且下半导体芯片的子接合垫的另一部分可配置为电连接至另一上半导体芯片。
附图说明
从下面结合附图的详细描述将更清楚地理解上述以及其它方面、特征及其它优点，其中：
图1是示出根据本发明实施例的半导体封装体的接合结构的局部构造的截面图；
图2是示出根据本发明实施例的半导体封装体的接合结构的局部构造的截面图；
图3至图7是示出根据本发明实施例的半导体封装体的接合结构的局部构造的截面图；
图8至图10是示出根据本发明实施例的半导体封装体的接合结构的制造方法的截面图；以及
图11至图14是示出根据本发明实施例的堆叠型半导体封装体的截面图。
具体实施方式
以下，将参考附图描述本发明的实施例。然而，实施例仅用于示例目的而不旨在限制本发明的范围。
图1是示出根据本发明实施例的半导体封装体的接合结构的局部构造的截面图。
参见图1，根据本发明的实施例的半导体封装体的该接合结构包括第一导电构件102和具有多个子接合垫104a至104d的接合垫(bonding pad)104。接合构件106可位于接合垫104的上表面上。
第一导电构件102例如可包括TSV，但是本发明的实施例并不限于此。只要导电构件具有垫连接，任何导电构件均可使用。第一导电构件102可包括选自由金(Au)、银(Ag)、铜(Cu)、铝(Al)、镍(Ni)、钨(W)、钛(Ti)、铂(Pt)、钯(Pd)、锡(Sn)、铅(Pb)、锌(Zn)、铟(In)、镉(Cd)、铬(Cr)和钼(Mo)构成的组的一种或多种金属、以及一种或多种该金属的氮化物、多晶硅和导电有机材料。该第一导电构件102可具有单层结构或多层结构。多晶硅可掺杂以提高电导性。
接合垫104包括电连接至第一导电构件102的一个表面(上表面)并彼此间隔开的多个子接合垫104a至104d。在各个子接合垫104a至104d之间，存在空的空间。图1示出四个子接合垫104a至104d，但这仅是一个示例。接合垫104可包括两个或更多个子接合垫。子接合垫104a至104d可包括选自由Au、Ag、Cu、Al、Ni、W、Ti、Pt、Pd、Sn、Pb、Zn、In、Cd、Cr和Mo构成的组的一种或多种金属、以及一种或多种该金属的氮化物、多晶硅和导电有机材料。子接合垫104a至104d可具有单层结构或多层结构。多晶硅可包括掺杂多晶硅。
接合构件106可包括形成在各个子接合垫104a至104d的上表面上的多个子接合构件106a至106d。子接合构件106a至106d可以是未连接的，即子接合构件106a至106d可彼此间隔开。子接合构件106a至106d可由诸如焊料的具有低熔点的金属形成。子接合构件106a至106d可包括Sn-Pb基合金焊料、Sn-Pb-Ag基合金焊料或者SAC(Sn-Ag-Cu)基合金焊料，但是本发明的实施例并不限制子接合构件106a至106d的材料。
在根据本发明的实施例的接合结构中，一个导电构件连接至多个子接合垫从而通过多个接触连接一个信号。因此，如果一个或多个子接合垫的连接断开，通过仍连接至该导电构件的其它子接合垫可实现信号连接。因此，信号连接的失效率可显著降低，并且结合可靠性可以提高。
图2是示出根据本发明实施例的半导体封装体的接合结构的局部构造的截面图。
参见图2，如本发明的上述实施例中所述，根据本发明的实施例的半导体封装体的接合结构包括第一导电构件102和具有多个子接合垫104a至104d的接合垫104。然而，存在于子接合垫104a至104d的上表面上的接合构件106具有非分离的结构，即接合构件106可形成为一个接合构件。接合构件106可由具有低熔点的金属(诸如焊料)形成。接合构件106可包括Sn-Pb基合金焊料、Sn-Pb-Ag基合金焊料或者SAC(Sn-Ag-Cu)基合金焊料，但是本发明的实施例并不限于接合构件106的此材料。
图3是示出根据本发明另一实施例的半导体封装体的接合结构的截面图。
参见图3，根据本发明的实施例的半导体封装体的接合结构包括第一导电构件102和具有多个子接合垫104a至104d的接合垫104。接合结构可进一步包括形成在子接合垫104a至104d的上表面上的由各向异性导电膜108组成的接合构件。由于以上已经描述第一导电构件102和包括多个子接合垫104a至104d的接合垫104，因此省略了其进一步的详细说明。
各向异性导电膜108可包括导电粒子P1。当温度和压力升高时，通过导电粒子P1可实现电接触。导电粒子P1可包括包含镍、焊料、银等的金属粒子、或碳粒子、或塑料粒子(诸如覆盖有金属层的聚苯乙烯或环氧树脂)、或覆盖有绝缘树脂的导电粒子、或包括导电材料的其它导电粒子。各向异性导电膜108可包括粘合材料，其允许将接合垫104粘附至各向异性导电膜108。粘合材料可包括选自聚乙烯或聚丙烯基热塑性树脂、环氧树脂、聚氨酯或丙烯醛基热固性树脂中的一种或多种材料，并且可以使用UV固化树脂，但是可使用的粘合材料的类型并不限于此。此外，各向异性导电膜108可包括绝缘粒子P2。
图4和图5是示出根据本发明实施例的半导体封装体的接合结构的局部构造的截面图。
参见图4和图5，根据本发明的实施例的半导体封装体的接合结构包括第一导电构件102和具有多个子接合垫104a至104d的接合垫104。接合结构可进一步包括形成在接合垫104的上表面上并具有多个子接合构件106a至106d的接合构件106。由于第一导电构件102之前已经说明，因此省略其进一步的详细说明。
如图1至图3所示的多个实施例中，接合垫104包括多个子接合垫104a至104d，然而在图4所描述的实施例中，全部或部分的子接合垫104a至104d可具有不同的高度。例如，第一和第四子接合垫104a和104d可比第二和第三子接合垫104b和104c高，第一和第四子接合垫104a和104d可具有基本相似的高度，并且第二和第三子接合垫104b和104c可具有基本相似的高度。图5所描述的实施例包括可基本接触子接合垫104a和104d的接合构件106。
图6是示出根据本发明另一实施例的半导体封装体的接合结构的局部构造的截面图。
参见图6，根据本发明的实施例的半导体封装体的接合结构包括第一导电构件102和具有多个子接合垫104a至104d的接合垫104。此外，在接合垫104的上表面上可形成接合构件106。接合构件106可作为与第二导电构件(未示出)的电性和物理连接。接合构件106可以这样的方式形成：填充子接合垫104a至104d的上表面上方的空间以及接合垫104a至104d之间的空间。如果接合构件106由焊料形成，可通过回流焊工艺填充空间。
图7是示出根据本发明另一实施例的半导体封装体的接合结构的局部构造的截面图。
参见图7，具有多个子接合垫的第一接合垫104形成在第一导电构件102之上。一部分或一些组成第一接合垫104的子接合垫可通过第一接合构件106电连接至第二导电构件202。另一部分的组成第一接合垫104的子接合垫可通过第一接合构件106电连接至第三导电构件302。第一导电构件102、第二导电构件202以及第三导电构件302可包括TSV。第一导电构件102可形成在第一芯片中，并且第二和第三导电构件202和302可形成在堆叠于第一芯片之上的第二芯片中。这样，可以说下半导体芯片可与上半导体芯片电连接。或者反过来说，上半导体芯片可与下半导体芯片电连接。在本发明的实施例中，导电构件(如图7中的102)的一个信号传输至两个或更多个导电构件(如图7中连接至第一导电构件102的第二和第三导电构件202和302)。然而，接收信号的导电构件的数目并不限于本发明实施例的两个。例如，图7中的导电构件102可配置为与任意多个导电构件连接以传输信号。
图8至图10是示出根据本发明实施例的半导体封装体的接合结构的制造方法的截面图。
参见图8，在半导体基板100中形成导电构件102，并且在基板100的上表面上施加光致抗蚀剂，并通过曝光和显影图案化以形成具有预定形状的多个开口V的光致抗蚀剂图案110。导电构件102可包括具有预定形状的导电结构如TSV。在施加光致抗蚀剂之前，可在基板100的上表面上进一步形成用于解除应力的应力缓冲层。如果开口V通过电镀被填充，则可进一步通过溅射、真空沉积或无电镀来执行形成种子层的工艺。
参见图9，多个导电材料层和焊料层随后形成以填充开口V。填充开口V的导电材料层形成多个子接合垫104a至104d，并且焊料层形成多个子接合构件106a至106d。填充开口V的用于形成子接合垫104a至104d的导电材料层和用于形成子接合构件106a至106d的焊料层可通过无电镀、电镀、真空沉积、溅射、化学气相沉积(CVD)、丝网印刷或涂覆(dispensing)来形成。
例如，开口可通过Cu电镀来填充。在此情况下，可在执行Cu电镀工艺之前形成种子金属层。Cu电镀期间使用的电镀溶液，除其他外，可包括Cu离子源、用于控制电导率的硫酸(H2SO4)、以及用于控制还原的盐酸(HCl)。电镀溶液可进一步包括附加试剂。例如，当CuSO4作为Cu离子源被加入H2SO4和水时，CuSO4分解为Cu2+离子和8O4 2-离子。在Cu电镀以后，可进一步执行金电镀以改善电特性。然而，在Cu上直接电镀金而其间没有中间层可能导致对改善整体导电性的一些局限。这是因为当直接在Cu上电镀金时，金和Cu元素趋向于朝彼此移动，这违背了通过镀金来提高电导率的初衷。因此，可在金电镀之前执行镀镍。
用于金电镀的镀液可包括氯金酸盐(chloroaurate)或金的亚硫酸盐作为金源并且氰化物基或非氰化物基化合物作为螯合剂。根据本发明的实施例，可以使用不同于氯金酸盐或金的亚硫酸盐的镀液用于金电镀。通过镍电镀形成镍层的工艺没有限制。例如，可使用包括NiSO4·6H2O(120～230g/L)、NiCL2(5～35g/L)、和H3PO4(5～35g/L)的溶液，或者可使用包括NiSO4·6H2O(120～230g/L)、Na4Cl(10～30g/L)和ZnSO4·7H2O(20～50g/L)的溶液。根据本发明的实施例，可在25至50℃的溶液温度和pH4-7的条件下形成镍层，但并不限于此。
根据本发明的实施例，通过丝网印刷可将金属膏埋入开口V中并随后干燥和烘烤以形成具有埋置于其中的导电材料的导电材料层。或者，导电材料也可以通过无电镀或CVD工艺埋入开口中。具体地，钨(W)、钛(Ti)、氮化钨或氮化钛可通过CVD工艺埋入。
参见图10，光致抗蚀剂图案110被移除以形成具有多个子接合垫104a至104d的接合垫104和具有多个子接合构件106a至106d的接合构件106。子接合构件106a至106d可由焊料形成并通过回流焊工艺回流，从而形成如图1所示的结构。
涉及半导体封装体的接合结构的制造方法的以上描述已结合本发明的实施例进行了说明，然而应当明白其它的变型也是可能的。例如，接合垫104和接合构件106可分离地形成。在此情况下，接合构件106可以不是具有多个彼此间隔开的子接合构件的接合构件，而是没有被分离的一个接合构件。另外，接合垫104可通过半导体薄膜或厚膜形成技术来形成，并且各向异性导电膜可用作接合构件106。
图11至图14是示出根据本发明实施例的堆叠型半导体封装体的截面图。
参见图11，根据本发明的实施例的堆叠型半导体封装体400包括通过包含子接合构件106a至106d的接合构件而堆叠并彼此电连接的第一芯片410和第二芯片420。第一芯片410包括第一导电构件412和第一接合垫104。第二芯片420包括第二导电构件422和第二接合垫124。可附加堆叠在第二芯片420上的第三芯片(未示出)可通过第二接合构件126被连接。
当需要时第一导电构件412和第二导电构件422的每一个可形成为具有TSV。具有垫连接的任意导电结构可用作第一和第二导电构件412和422。
第一接合垫104电连接至第一导电构件412的表面(如上表面)，并且可包括彼此间隔开的多个子接合垫104a至104d。图11示出包括四个子接合垫104a至104d的第一接合垫104的情况。然而，这仅是示例，第一接合垫104可包括两个或更多个子接合垫。与第一接合垫104类似，第二接合垫124可包括多个子接合垫。
由于导电构件412和422、接合垫104和124以及接合构件106和126在以上已经详细说明，因此省略了其进一步的详细说明。
图11示出了使用了图1所示的接合结构的堆叠型封装体。根据本发明的实施例，图2至图7所示的接合结构的实施例也可用于实现堆叠型封装体。
图12是使用了图2所示的接合结构的堆叠型封装体的截面图。正如在图2中，图12的接合构件106和126可形成为单件，即接合构件106和126分别形成为没有被分离的一个接合构件。
图13是使用了图3所示的接合结构的堆叠型封装体的截面图。正如在图3中，图13的接合构件可包括各向异性导电膜108。
图14是使用了图7所示的接合结构的堆叠型封装体的截面图。图14示出了这样的情况，其中一部分的子接合垫通过第一子接合构件106a电连接至第二导电构件202，而另一部分的子接合垫通过第四子接合构件106d电连接至第三导电构件302。
在图12至图14中，除了图11的接合垫和接合构件之外，堆叠型封装体的结构彼此相同，并且因而省略了其进一步的详细描述。此外，尽管没有示出，也可应用使用了图4至图6所示的接合结构的堆叠型封装体。
出于说明的目的，以上披露了本发明的实施例。本领域的技术人员应理解，在不脱离如所附权利要求所披露的本发明的范围和精神的情况下，各种修改、添加和替代是可能的。
本申请要求2010年12月1日和2011年11月23日在韩国知识产权局提交的第10-2010-0121245号和第10-2011-0123017号的韩国专利申请的优先权，在此其全部内容通过参考引入结合于此。

Claims (22)

1.一种半导体封装体的接合结构，包括：
配置为传输电信号的第一导电构件；以及
配置为电连接至该第一导电构件的表面并包括多个子接合垫的接合垫。
2.根据权利要求1的接合结构，其中该第一导电构件包括硅通孔。
3.根据权利要求1的接合结构，其中全部或部分的该子接合垫彼此具有不同的高度。
4.根据权利要求1的接合结构，进一步包括设置在该子接合垫的上表面上并将该第一导电构件电连接至第二导电构件的接合构件。
5.根据权利要求4的接合结构，其中该接合构件填充该子接合垫的该上表面上方的空间以及各个该子接合垫之间的空间。
6.根据权利要求4的接合结构，其中该接合构件包括多个子接合构件，每个子接合构件形成在该子接合垫中对应的一个该子接合垫的上表面上。
7.根据权利要求1的接合结构，其中一部分的该子接合垫配置为电连接至第二导电构件，并且另一部分的该子接合垫配置为电连接至第三导电构件。
8.一种半导体封装体的接合结构的制造方法，包括：
在基板中形成导电构件，该导电构件配置为传输电信号；以及
形成接合垫，该接合垫配置为电连接至该导电构件的表面并且包括多个彼此间隔开的子接合垫。
9.如权利要求8的方法，其中，该导电构件包括硅通孔。
10.如权利要求8的方法，进一步包括在该接合垫的上表面上形成接合构件。
11.如权利要求10的方法，其中，该接合构件包括焊料或各向异性导电膜。
12.如权利要求10的方法，其中，该接合构件包括多个彼此间隔开的子接合构件，其中每个子接合构件形成在该子接合垫中对应的一个该子接合垫的上表面上。
13.如权利要求12的方法，其中该接合垫包括：
在该基板上方形成光致抗蚀剂图案，该光致抗蚀剂图案具有多个彼此间隔开的开口；
通过在该开口中埋入导电材料而形成导电材料层；
在该导电材料层的上表面上形成焊料层；以及
移除该光致抗蚀剂图案，并且该子接合垫和子接合构件同时形成。
14.如权利要求13的方法，进一步包括：
该形成该导电材料层的步骤包括无电镀、电镀、真空沉积、溅射、化学气相沉积、丝网印刷以及涂覆中的一种或多种；以及
该形成该焊料层的步骤包括无电镀、电镀、真空沉积、溅射、化学气相沉积、丝网印刷或涂覆中的一种或多种。
15.如权利要求13的方法，进一步包括在形成该光致抗蚀剂图案之前在该基板上方形成种子层。
16.一种半导体封装体，包括两个或更多个堆叠半导体芯片，每个半导体芯片配置为传输电信号并包括接合垫，该接合垫包括多个子接合垫，该多个子接合垫配置为通过下半导体芯片的至少两个或更多个子接合垫与该半导体芯片中的上半导体芯片电连接。
17.如权利要求16的半导体封装体，其中两个或更多个堆叠半导体芯片的每个半导体芯片包括导电构件，该导电构件包括该子接合垫并进一步包括硅通孔。
18.如权利要求16的半导体封装体，其中全部或部分的该子接合垫具有不同高度。
19.如权利要求16的半导体封装体，进一步包括设置在该子接合垫的上表面上并配置为电连接该堆叠半导体芯片的接合构件。
20.如权利要求19的半导体封装体，其中该接合构件填充该子接合垫的该上表面上方的空间以及各个该子接合垫之间的空间。
21.如权利要求19的半导体封装体，其中该接合构件包括各自形成在子接合垫的上表面上的多个子接合构件。
22.如权利要求16的半导体封装体，其中该下半导体芯片的至少两个子接合垫配置为电连接至该上半导体芯片，并且
该下半导体芯片的该子接合垫的另一部分配置为电连接至另一上半导体芯片。
CN2011104631748A 2010-12-01 2011-12-01 半导体封装体的接合结构、其制造方法及半导体封装体 Pending CN102569239A (zh)

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