CN111710660B - 具有冗余电连接器的互连结构及相关系统与方法 - Google Patents

具有冗余电连接器的互连结构及相关系统与方法 Download PDF

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CN111710660B
CN111710660B CN202010389901.XA CN202010389901A CN111710660B CN 111710660 B CN111710660 B CN 111710660B CN 202010389901 A CN202010389901 A CN 202010389901A CN 111710660 B CN111710660 B CN 111710660B
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conductive
conductive trace
semiconductor die
semiconductor
tsvs
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CN111710660A (zh
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安尼库玛·查杜鲁
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Micron Technology Inc
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Micron Technology Inc
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Abstract

本发明涉及具有冗余电连接器的互连结构及相关系统与方法。本发明揭示具有含冗余电连接器的互连结构的半导体裸片组合件。在一个实施例中，半导体裸片组合件包含第一半导体裸片、第二半导体裸片及介于所述第一半导体裸片与所述第二半导体裸片之间的互连结构。所述互连结构包含耦合到所述第一半导体裸片的第一导电膜及耦合到所述第二半导体裸片的第二导电膜。所述互连结构进一步包含在所述第一导电膜与所述第二导电膜之间延伸且经由所述第一导电膜而彼此电耦合的多个冗余电连接器。

Description

具有冗余电连接器的互连结构及相关系统与方法
分案申请的相关信息
本申请是国际申请号为PCT/US2015/032216，申请日为2015年5月22日，发明名称为“具有冗余电连接器的互连结构及相关系统与方法”的PCT申请进入中国国家阶段后申请号为201580036987.5的中国发明专利申请的分案申请。
技术领域
所揭示的实施例涉及形成于半导体裸片组合件中的堆叠半导体裸片之间的互连结构。在若干实施例中，本发明涉及一种具有冗余导电连接器的互连结构。
背景技术
封装半导体裸片(其包含存储器芯片、微处理器芯片及成像器芯片)通常包含安装于衬底上且包围于塑料保护罩中的半导体裸片。所述裸片包含功能特征(例如存储器单元、处理器电路及成像器装置)及电连接到所述功能特征的接合垫。所述接合垫可电连接到所述保护罩外的端子以允许所述裸片连接到外部电路。
在一些裸片封装内，半导体裸片可堆叠于彼此上且通过放置于相邻裸片之间的互连件而彼此电连接。可使用金属焊料来将互连件连接到相邻裸片的接合垫。然而，金属焊料接合的一个挑战在于：金属焊料无法始终适当地接合到互连件及/或接合垫。因此，互连件可为开路的，这可引起裸片封装无法适当地运行。这又可降低制造期间的工艺产量。
发明内容
一方面，本公开涉及一种半导体裸片组合件，其包括：第一半导体裸片；第二半导体裸片；及互连结构，其将所述第一半导体裸片耦合到所述第二半导体裸片，其中所述互连结构介于所述第一半导体裸片与所述第二半导体裸片之间，且其中所述互连结构包含-第一导电膜，其耦合到所述第一半导体裸片，第二导电膜，其耦合到所述第二半导体裸片，及多个冗余电连接器，其在所述第一导电膜与所述第二导电膜之间延伸且经由所述第一导电膜而彼此电耦合。
另一方面，本公开涉及一种半导体裸片组合件，其包括：第一半导体裸片，其具有第一导电迹线；第二半导体裸片，其具有第二导电迹线；及多个冗余电连接器，其在所述第一导电迹线与所述第二导电迹线之间延伸，其中所述冗余电连接器中的每一者包含-导电部件，其耦合到所述第一导电迹线，其中所述导电部件包含端部分，及导电接合材料，其介于所述导电部件与所述第二导电迹线之间，其中所述导电接合材料接合到所述导电部件的所述端部分。
另一方面，本公开涉及一种半导体裸片组合件，其包括：第一半导体裸片，其具有导电迹线；第二半导体裸片；及多个导电部件，其耦合到所述导电迹线且朝向所述第二半导体裸片垂直延伸，其中所述导电部件经由所述导电迹线而彼此电耦合，且其中所述导电部件中的至少一者耦合到所述第二半导体裸片。
另一方面，本公开涉及一种形成半导体裸片组合件的方法，所述方法包括：在第一半导体裸片上形成第一导电膜；在第二半导体裸片上形成第二导电膜；在所述第一导电膜上形成多个冗余电连接器；及将所述冗余电连接器耦合到所述第二导电膜。
另一方面，本公开涉及一种形成半导体裸片组合件的方法，其包括：在第一半导体裸片上形成第一导电迹线；在所述第一导电迹线上形成突出远离所述第一半导体裸片的多个导电部件；在所述导电部件中的每一者上安置导电接合材料；及回焊所述导电接合材料以将所述多个导电部件中的个别者耦合到第二半导体裸片的第二导电迹线。
附图说明
图1是根据本发明的实施例而配置的半导体裸片组合件的横截面图。
图2A是根据本发明的实施例而配置的包含互连结构的半导体装置的放大横截面图。
图2B是说明可在制造期间发生的焊料接合的某些失效模式的横截面图。
图3是展示根据本发明的另一实施例而配置的互连结构方俯视平面图。
图4A到4H是说明根据本发明的所选择的实施例的用于制造互连结构的方法的各种阶段中的半导体装置的横截面图。
图5是根据本发明的实施例而配置的包含半导体裸片组合件的系统的示意图。
具体实施方式
下文描述具有含冗余电连接器的互连结构的堆叠半导体裸片组合件及相关系统与方法的若干实施例的特定细节。术语“半导体装置”及“半导体裸片”一般是指包含半导体材料的固态装置，例如逻辑装置、存储器装置或其它半导体电路、组件等等。此外，术语“半导体装置”及“半导体裸片”可指成品装置或变为成品装置之前的各种处理阶段中的组合件或其它结构。术语“衬底”可指晶片级衬底或单粒化裸片级衬底，这取决于使用所述术语的背景。相关领域的技术人员将认识到，可在晶片级或裸片级处执行本文所描述的方法的合适步骤。此外，如果上下文无另外说明，那么可使用常规半导体制造技术来形成本文所揭示的结构。可(例如)使用化学气相沉积、物理气相沉积、原子层沉积、旋转涂布及/或其它合适技术来沉积材料。类似地，可(例如)使用等离子蚀刻、湿式蚀刻、化学机械平坦化或其它合适技术来移除材料。相关领域的技术人员还应了解，本发明可具有额外实施例，且可在无下文参考图1到5所描述的实施例的若干细节的情况下实践本发明。
如本文所使用，术语“垂直”、“横向”、“上”及“下”可指半导体裸片组合件中的特征鉴于图中所展示的定向的相对方向或位置。举例来说，“上”或“最上”可指特征定位成比另一特征更靠近于页的顶部。然而，这些术语应被广义地被解释为包含具有其它定向的半导体装置。
图1是根据本发明的实施例而配置的半导体裸片组合件100(“组合件100”)的横截面图。组合件100包含由第二半导体裸片102b承载的第一半导体裸片102a的堆叠(统称为“半导体裸片102”)。第二半导体裸片102b又由中介层120承载。中介层120可包含(例如)半导体裸片、电介质间隔件及/或另一合适衬底，其具有连接于中介层120与封装衬底125之间的电连接器(未展示)，例如通孔、金属迹线等等。封装衬底125可包含(例如)中介层、印刷电路板、另一逻辑裸片或另一合适衬底，其连接到将组合件100电耦合到外部电路(未展示)的封装接触件127(例如接合垫)及电连接器128(例如焊料球)。在一些实施例中，封装衬底125及/或中介层120可经不同配置。举例来说，在一些实施例中，可省略中介层120且可将第二半导体裸片102b直接连接到封装衬底125。
组合件100可进一步包含导热罩壳110(“罩壳110”)。罩壳110可包含盖部分112及附接到盖部分112或与盖部分112一体地形成的壁部分113。盖部分112可通过第一接合材料114a(例如粘合剂)而附接到最顶部的第一半导体裸片102a。壁部分113可远离盖部分112垂直延伸且通过第二接合材料114b(例如粘合剂)而附接到第一半导体裸片102a的外围部分106(所属领域的技术人员称为“门廊”或“座架”)。除提供保护罩之外，罩壳110可充当散热器以吸收热能且使热能从半导体裸片102耗散。相应地，罩壳110可由导热材料(例如镍(Ni)、铜(Cu)、铝(Al)、具有高导热性的陶瓷材料(例如氮化铝)、及/或其它合适导热材料)制成。
在一些实施例中，第一接合材料114a及/或第二接合材料114b可由所属领域中称为“热接合材料”或“TIM”(其经设计以增加表面结(例如，在裸片表面与散热器之间)处的接触热导性)的材料制成。TIM可包含掺杂有导电材料(例如碳纳米管、焊接材料、类金刚石碳(DLC)等等)及相变材料的硅酮基脂、凝胶或粘合剂。在其它实施例中，第一接合材料114a及/或第二接合材料114b可包含其它合适材料，例如金属(例如铜)及/或其它合适导热材料。
第一及/或第二半导体裸片102的一些或全部可至少部分囊封于电介质底填材料116中。底填材料116可沉积或以其它方式形成于所述裸片的部分或全部周围及/或所述裸片的一些或全部之间以增强与裸片的机械连接及/或提供导电特征及/或结构(例如互连件)之间的电隔离。底填材料116可为非导电环氧树脂膏、毛细管底填材料、非导电膜、模制底填材料，及/或包含其它合适电绝缘材料。在若干实施例中，可基于底填材料116的导热性而选择底填材料116以增强通过组合件100的裸片的热消散。在一些实施例中，可使用底填材料116来代替第一接合材料114a及/或第二接合材料114b以将罩壳110附接到最顶部的第一半导体裸片102a。
半导体裸片102可各自由半导体衬底(例如硅、绝缘体上硅、化合物半导体(例如氮化镓)或其它合适衬底)形成。所述半导体衬底可切割成或单粒化成具有各种集成电路组件或功能特征中的任何者(例如动态随机存取存储器(DRAM)、静态随机存取存储器(SRAM)、快闪存储器或其它形式的集成电路装置，其包含存储器、处理电路、成像组件及/或其它半导体装置)的半导体裸片。在所选择的实施例中，组合件100可配置为混合存储器立方体(HMC)，其中第一半导体裸片102a提供数据存储装置(例如DRAM裸片)且第二半导体裸片102b提供HMC内的存储器控制(例如DRAM控制)。在一些实施例中，组合件100可除包含半导体裸片102中的一或多者之外还包含其它半导体裸片，及/或包含其它半导体裸片来代替半导体裸片102中的一或多者。举例来说，此类半导体裸片可包含除数据存储装置及/或存储器控制组件之外的集成电路组件。此外，尽管组合件100包含堆叠于中介层120上的9个裸片，但在其它实施例中，组合件100可包含9个以下裸片(例如6个裸片)或9个以上裸片(例如12个裸片、14个裸片、16个裸片、32个裸片等等)。举例来说，在实施例中，组合件100可包含堆叠于2个逻辑裸片上的4个存储器裸片。此外，在各种实施例中，半导体裸片102可具有不同尺寸。举例来说，在一些实施例中，第二半导体裸片102b可具有与第一半导体裸片102a中的至少一者相同的占据面积。
如图1中进一步所展示，组合件100进一步包含：多个第一导电迹线140a(“第一迹线140a”)，其位于半导体裸片102的第一侧109a(例如前侧)上；多个第二导电迹线140b(“第二迹线140b”)，其位于半导体裸片102的第二侧109b(例如后侧)上；及多个互连结构130，其使个别第一迹线140a与个别第二迹线140b相互耦合。第一迹线140a及第二迹线140b中的每一者可包含(例如)横跨半导体裸片102的一侧而横向延伸的导电线、导电板或其它导电结构。在所说明的实施例中，第一迹线140a及第二迹线140b耦合到对应穿衬底通孔(TSV)142。TSV经配置以使半导体裸片102的相对侧处的第一迹线140a及第二迹线140b相互耦合。如图中所展示，TSV 142可朝向半导体裸片102的中心安置，且第一迹线140a及第二迹线140b可从TSV 142向外展开且朝向互连结构130。然而，在其它实施例中，TSV 142、第一迹线140a及第二迹线140b及/或互连结构130可经不同布置。
互连结构130可各自包含耦合于相邻半导体裸片102的个别第一迹线140a与个别第二迹线140b之间的多个冗余电连接器134(“冗余连接器134”)。因而，每一对的第一迹线140a及第二迹线140b通过多个冗余连接器134而电及热耦合在一起。在此实施例的一个方面中，冗余连接器134可改进制造期间的工艺产量。举例来说，如下文更详细所描述，个别结构130相对于常规互连件或其它电连接器不易于开路，这是因为存在沿迹线140a及140b彼此隔开的多个冗余连接器。在此实施例的另一方面中，冗余连接器134可增强通过半导体裸片102的堆叠且朝向罩壳110的盖部分112的热传导。特定来说，冗余连接器134可提供相邻半导体裸片102之间的多个热传递路径。在若干实施例中，冗余连接器134可沿个别迹线140a及140b彼此隔开以横跨半导体裸片102而横向散发热。在额外或替代实施例中，额外冗余电连接器138(以虚线展示)可在半导体裸片102的内部部分(例如，在TSV 142之间)及/或外部部分(例如，朝向裸片102的边缘)之间延伸以进一步散发热。
图2A是根据本发明的实施例而配置的具有互连结构230的半导体装置205的放大图。如图中所展示，互连结构230包含在第一半导体衬底204a(例如半导体晶片或裸片)与第二半导体衬底204b(例如半导体晶片或裸片)之间延伸的多个冗余电连接器234(“冗余连接器234”)。冗余连接器234中的每一者包含耦合到第一衬底204a的第一导电膜或第一迹线240a的导电部件或柱232。冗余连接器234还包含耦合到第二衬底204b上的第二导电膜或第二迹线240b的第二导电部件或接合垫233(例如凸起接合垫)。导电接合材料235可形成将接合垫233耦合到对应柱232的端部分237的导电接头。导电接合材料235可包含(例如)焊料(例如金属焊料)、导电环氧树脂或导电膏。
一般来说，焊料接合材料的一个挑战在于：其无法将互连件适当地接合到接合垫。举例来说，图2B展示焊料接合材料295的若干失效模式。第一失效模式F1发生于互连件292具有小于相邻互连件(未展示)的高度的高度时。在此失效模式中，互连件292与其对应接合垫293之间的较大间隙阻止接合材料295接触接合垫293。第二失效模式F2发生于互连件292及/或接合垫293上的残余污染物(未展示)阻止接合材料295湿润到互连件292及/或接合垫293时。第三失效模式F3可归因于发生于回焊或其它加热过程期间的焊料芯吸作用。特定来说，焊料芯吸作用发生于表面张力吸引(经加热)接合材料295朝向互连件292的侧壁296且远离接合垫293时。第四失效模式F4涉及互连件292与接合垫293之间的接合材料295的开裂或破裂。开裂可(例如)发生于焊接材料消耗互连件的某些材料(例如钯(Pd))(即，与之反应)且引起接合材料295变得易碎且易于破裂时。
然而，根据本发明的若干实施例而配置的互连结构可解决常规互连件及相关结构的这些及其它限制。再次参考图2A，冗余连接器234经配置使得即使某些连接器234失效(例如，通过失效模式F1到F4中的一者)，但只要其它冗余连接器234中的至少一者保持连接到第一迹线240a及第二迹线240b，那么互连结构230就不会失效。在图2A所展示的实施例中，举例来说，高达4个冗余连接器234可失效且不使互连结构230开路。在其它实施例中，互连结构230可具有不同数目个冗余连接器，例如5个以上冗余连接器(例如6个、8个、10个或10个以上连接器)或5个以下冗余连接器(例如2个、3个或4个连接器)。在若干实施例中，冗余连接器的数目可经选择以改进制造期间的预期工艺产量。举例来说，在一些例子中，具有3个冗余连接器的互连结构可使工艺产量提高0.5％，而4个冗余连接器仅可使产量额外提高0.05％。在此方案中，3连接器配置可为比4连接器配置更可接受的设计，这是因为工艺产量的预期差值可忽略不计。
各种实施例的互连结构的另一优点在于：冗余电连接器可减小通过导电接头(例如，通过冗余互连件234的接合材料235)的电流密度。举例来说，具有10个冗余连接器的互连结构可使通过其导电接头中的每一者的电流密度减小约10倍。相关优点在于：较低电流密度可减少电迁移。举例来说，较低电流密度可减少通过锡/银基(SnAg)焊料接头的电迁移，锡/银基(SnAg)焊料接头通常比其它互连材料(例如铜)更易受电迁移影响。在一些实施例中，冗余电连接器的数目可经选择以实现与横跨互连结构的电容的潜在增加平衡的电迁移的某一减少。
各种实施例的互连结构的进一步优点在于：冗余电连接器可紧密堆积。举例来说，图3是展示根据本发明的另一实施例而配置的对应互连结构330的紧密堆积冗余电连接器334(“冗余连接器334”)的俯视平面图。如图中所展示，冗余连接器334各自形成于对应互连结构330的导电迹线340上。冗余连接器334各自具有直径d1且彼此隔开达间隔距离s1。在一个实施例中，直径d1的尺寸可近似相同于间隔距离s1。在另一实施例中，间隔距离s1可小于直径d1。举例来说，间隔距离s1可小于d1的75％，小于d1的50％，或小于d1的25％。相比之下，常规互连件无法以此方式紧密堆积，这是因为存在金属焊料可桥接互连件且引起电短接的风险。然而，因为冗余连接器334彼此电耦合(即，经由导电迹线340)，所以电短接不会造成此风险。
图4A到4H是说明根据本发明的所选择的实施例的用于制造互连结构的方法的各种阶段中的半导体装置405的部分横截面图。首先参考图4A，半导体装置405包含第一衬底404a(例如硅晶片或裸片)及形成于第一衬底404a上的第一电介质材料450a(例如氧化硅)。第一电介质材料450a经图案化以暴露衬底接触件407(例如铜接合垫)。第一电介质材料450a还可经图案化以暴露第一衬底404a的其它衬底接触件(未展示)，例如连接到第一衬底404a的集成电路(IC)装置(例如存储器；未展示)的衬底接触件。半导体装置405进一步包含形成于第一电介质材料450a及衬底接触件407上的经图案化的第一导电膜或第一导电迹线440a(例如铜或铜合金膜)。
图4B展示在第一电介质材料450a中形成掩模460(例如光致抗蚀剂掩模、硬掩模等等)及开口452之后的半导体装置405。可凭借通过对应掩模开口461移除(例如，蚀刻)第一电介质材料450a的部分而形成开口452。如图4B中所展示，开口452可暴露下伏第一导电迹线440a的部分。
图4C展示在第一导电迹线440a上形成导电部件或柱432之后的半导体装置405。在若干实施例中，可通过将晶种材料472(例如铜)沉积于掩模开口461(图4B)的侧壁462上且接着将导电材料470(例如铜)电镀到晶种材料472上而形成柱432。在所说明的实施例中，还可将势垒材料474(例如镍)及界面材料475(例如钯)依序电镀到导电材料470上。在其它实施例中，可使用其它沉积技术(例如溅镀)来代替电镀。
图4D展示在第一衬底404a中形成开口408且在柱432上形成保护材料463之后的半导体装置405。如图中所展示，开口408延伸通过第一衬底404a且使衬底接触件407的部分朝向开口408的底部暴露。在若干实施例中，可通过首先使第一衬底404a变薄(例如，经由蚀刻、背面研磨等等)且接着移除衬底材料(例如，经由蚀刻)而形成开口408。在所说明的实施例中，保护材料或保护膜463(例如聚化膜)可在制造期间保护柱432。
图4E展示形成TSV 442、第二电介质材料450b、及第二导电膜或第二导电迹线440b之后的半导体装置405。可通过使用导电材料476(例如铜或铜合金)填充第一衬底404a中的开口408(图4D)而形成TSV 442。在若干实施例中，可以类似于第一导电迹线440a及第一电介质材料450a的方式的方式形成第二导电迹线440b及第二电介质材料450b。
图4F展示在第二电介质材料450b中形成掩模465及开口453之后的半导体装置405。可凭借通过对应掩模开口466移除(例如，蚀刻)第二电介质材料450b的部分而形成开口453。如图4F中所展示，第二电介质材料450b中的开口453可暴露下伏第二导电迹线440b的部分。
图4G展示在第二导电迹线440b上形成导电部件或接合垫433之后的半导体装置405。类似于柱432，可通过将晶种材料477(例如铜)沉积到掩模开口466(图4F)的侧壁467及/或第二导电迹线440b上且接着将导电材料478(例如铜)电镀到晶种材料477上而形成接合垫433。在一些实施例中，接合垫433可包含依序电镀到导电材料478上的势垒材料484(例如镍)及界面材料485(例如钯)。
图4H展示移除掩模465及保护膜463(图4G)且在柱432的端部分437上形成接合材料435(例如金属焊料)之后的半导体装置405。在一个实施例中，接合材料435可为电镀材料。在另一实施例中，接合材料435可呈焊料球的形式。无论何种情况，可加热(例如，回焊)接合材料435且使接合材料435与第二衬底404b的对应接合垫433接触。在回焊之后，可允许接合材料435冷却且固化成将柱432附接到接合垫433的导电接头。在若干实施例中，接合垫433的结构及功能可大体上类似于第一衬底404a的接合垫433(图4G)的结构及功能。
上文参考图1到4H所描述的互连结构及/或半导体裸片组合件的任一者可并入到许多更大及/或更复杂系统(其代表实例是图5中示意性地所展示的系统590)的任何者中。系统590可包含半导体裸片组合件500、电源592、驱动器594、处理器596及/或其它子系统或组件598。半导体裸片组合件500可包含大体上类似于上文所描述的堆叠半导体裸片组合件的特征的特征，且可因此包含增强热消散的各种特征。所得系统590可执行各种功能中的任何者，例如存储器存储、数据处理及/或其它合适功能。因此，代表系统590可包含(但不限于)手持式装置(例如移动电话、平板计算机、数字阅读器及数字音频播放器)、计算机及电器。系统590的组件可容纳于单个单元中或分布于多个互连单元上(例如，通过通信网路)。系统590的所述组件还可包含远程装置及各种各样的计算机可读媒体中的任何者。
应从上述内容了解，本文已出于说明的目的而描述本发明的特定实施例，但可在不背离本发明的情况下进行各种修改。举例来说，尽管相对于HMC而描述半导体裸片组合件的实施例中的若干者，但在其它实施例中，半导体裸片组合件可配置为其它存储器装置或其它类型的堆叠裸片组合件。另外，尽管已在所说明的实施例中将某些特征或组件展示为具有某些布置或配置，但其它布置及配置是可能的。举例来说，尽管在所说明的实施例中在前端金属化之后(即，在形成衬底接触件407之后)形成TSV 442(图4E)，但在其它实施例中，可在前端金属化之前或与前端金属化同时地形成TSV 442。此外，尽管在所说明的实施例中将柱接合到凸起垫，但在其它实施例中，可将柱接合到其它结构或直接接合到导电迹线。此外，尽管已在与新技术的某些实施例的上下文中描述与所述实施例相关的优点，但其它实施例还可展现此类优点且未必需要所有实施例展现落于本技术的范围内的此类优点。因此，本发明及相关技术可涵盖本文未清楚地展示或描述的其它实施例。

Claims (20)

1.一种半导体装置，其包括：
半导体衬底；
多个穿衬底通孔TSV，其延伸穿过所述半导体衬底；
导电迹线，其设置在所述半导体衬底的表面上并电耦合到所述多个TSV；以及
多个冗余电连接器，其通过所述导电迹线与所述多个TSV电耦合。
2.根据权利要求1所述的半导体装置，其中所述多个冗余电连接器在第一方向上远离所述导电迹线而延伸，且所述多个TSV在与所述第一方向大致相反的第二方向上远离所述导电迹线而延伸。
3.根据权利要求1所述的半导体装置，其进一步包括：
衬底触点，其耦合到所述导电迹线的一部分并且直接置于所述导电迹线与所述多个TSV中的至少一个TSV之间。
4.根据权利要求1所述的半导体装置，其中所述导电迹线是第一导电迹线，并且所述表面是所述半导体衬底的第一表面，其中所述多个TSV从所述第一表面延伸到与所述第一表面相对的所述半导体衬底的第二表面，所述半导体装置进一步包括：
第二导电迹线，其设置在所述第二表面上并电耦合到所述多个TSV；以及
多个导电接合垫，其电耦合到所述第二导电迹线。
5.根据权利要求4所述的半导体装置，其中耦合到所述第一导电迹线的所述多个冗余电连接器沿第一方向远离所述半导体衬底而延伸，且耦合到所述第二导电迹线的所述多个导电接合垫沿与所述第一方向大致相反的第二方向远离所述半导体衬底而延伸。
6.根据权利要求1所述的半导体装置，其进一步包括：
在所述半导体衬底的所述表面的上方的电介质材料，其中所述导电迹线至少部分地延伸穿过所述电介质材料。
7.根据权利要求6所述的半导体装置，其中所述电介质材料包括暴露所述导电迹线的部分的多个开口，其中所述多个冗余电连接器形成在所述多个开口中。
8.根据权利要求1所述的半导体装置，其中所述多个冗余电连接器从所述导电迹线延伸并穿过设置在所述半导体衬底的所述表面的上方的电介质材料的一部分。
9.根据权利要求1所述的半导体装置，其中所述多个冗余电连接器中的每一者包括：
导电柱，其耦合到所述导电迹线，以及
导电接合材料，其接合到所述导电柱。
10.根据权利要求9所述的半导体装置，其中所述导电柱包括铜且所述导电接合材料包括焊料。
11.根据权利要求9所述的半导体装置，其中所述导电柱包括端部，且其中所述导电接合材料和所述导电柱在所述端部处形成导电接头。
12.根据权利要求9所述的半导体装置，其中所述导电柱包括大体上垂直的侧壁和覆盖所述侧壁的至少一部分的势垒层和/或晶种材料。
13.一种半导体裸片组合件，其包括：
第一半导体裸片，其包括多个穿衬底通孔TSV和设置在所述第一半导体裸片的第一表面上的第一导电迹线，所述第一导电迹线电耦合到所述多个TSV；
第二半导体裸片，其包括设置在所述第二半导体裸片的第二表面上的第二导电迹线；以及
多个冗余电连接器，其将所述第一导电迹线电耦合到所述第二导电迹线且通过所述第一导电迹线与所述多个TSV电耦合。
14.根据权利要求13所述的半导体裸片组合件，其中所述多个TSV是第一多个TSV，且其中所述第二半导体裸片包括第二多个TSV，所述第二导电迹线电耦合到所述第二多个TSV。
15.根据权利要求14所述的半导体裸片组合件，其中：
所述第一导电迹线通过直接位于所述第一导电迹线与所述第一多个TSV中的至少一个TSV之间的衬底触点而耦合到所述第一多个TSV中的至少一个TSV；且
所述第二导电迹线直接连接到所述第二多个TSV中的至少一个TSV。
16.根据权利要求13所述的半导体裸片组合件，其中所述多个冗余电连接器中的每一者包括：
导电柱，其耦合到所述第一导电迹线；
接合垫，其耦合到所述第二导电迹线；和
导电接合材料，其位于所述导电柱和所述接合垫之间。
17.根据权利要求16所述的半导体裸片组合件，其中所述导电柱和所述接合垫包括铜，且所述导电接合材料包括焊料。
18.根据权利要求16所述的半导体裸片组合件，其中所述导电柱包括端部，且其中所述导电接合材料形成将所述结合垫耦合到所述导电柱的所述端部的导电接头。
19.根据权利要求16所述的半导体裸片组合件，其中，所述导电柱和所述接合垫分别包括大致垂直的侧壁，所述侧壁的至少一部分被势垒层和/或晶种材料覆盖。
20.根据权利要求13所述的半导体裸片组合件，其中：
所述第一半导体裸片是第一逻辑裸片或第一存储裸片；和
所述第二半导体裸片是第二逻辑裸片或第二存储器裸片。
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