TWI455214B - 用於資料處理系統之整合模組 - Google Patents

用於資料處理系統之整合模組 Download PDF

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TWI455214B
TWI455214B TW098103270A TW98103270A TWI455214B TW I455214 B TWI455214 B TW I455214B TW 098103270 A TW098103270 A TW 098103270A TW 98103270 A TW98103270 A TW 98103270A TW I455214 B TWI455214 B TW I455214B
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Taiwan
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carrier
integrated module
substrate
crucible
dies
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TW098103270A
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English (en)
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TW200943440A (en
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Bing Dang
John Ulrich Knickerbocker
Cornelia Kang-I Tsang
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Ibm
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    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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Description

用於資料處理系統之整合模組
本發明大體係關於一種改良型資料處理系統。更具體言之，本發明係針對在整合模組內封裝複數個微電子組件以賦能較高資料處理系統效能。
如今，使用封裝於經常被稱作系統晶片(SoC)之單晶粒上之矽電路存在許多優點。一種該優點在於：此單晶粒可提供為提供最終產品功能所需要之總功能。因此，若製造產率在此單晶粒上較高，則可降低產品成本。
先前已提議包括在單晶圓上經處理之眾多功能且藉由諸如導線結合或覆晶技術之方式而互連以提供允許系統機器操作之互連方法之機器的構思。然而，以競爭性成本在晶圓上製造極大SoC之當前能力具有實際限制。因此，半導體晶粒尺寸如今視應用而定，且可在實際產率的情況下(尤其在晶粒可具有(諸如)大於108 個電路之高電路計數時)在自用於有限效能應用之小於5mm×5mm之較低尺寸至用於高效能應用之約20mm×20mm至25mm×25mm之上限的範圍內。若所要系統功能或效能需要藉由具有高晶粒至晶粒互連性之多個晶粒而對2XN、4XN、8XN或更多積體電路進行槓桿作用，則基於矽之封裝、堆疊晶粒或其中之組合可最佳地適合於滿足此等應用。
說明性實施例提供一種用於整合模組之改良型裝置。具有貫穿矽導通孔(through-silicon via)之矽載體具有連接至矽載體之頂面的複數個晶粒。另外，基板連接至矽載體之底面。基板經由貫穿矽導通孔而耦接至複數個晶粒。
在隨附申請專利範圍中闡明被認為係本發明之特性的新穎特徵。然而，本發明自身以及其較佳使用模式、另外目標及優點將藉由在閱讀時結合隨附圖式而參考說明性實施例之以下詳細描述而被最佳地理解。
現參看諸圖且尤其參看圖1，提供模組總成之例示性方塊圖，其中可實施說明性實施例。應瞭解，圖1僅為例示性的且不意欲確定或暗示關於不同說明性實施例之任何限制。可對經描繪之模組總成進行許多修改。
圖1描繪根據說明性實施例之模組總成的例示性方塊圖。模組總成100為電組件及/或光學組件，其能夠在諸如電腦之電子設備內執行諸如處理及儲存資料之複數個功能。模組總成100包括整合模組102及印刷電路板(PCB)104。
整合模組102為自含式組件且可根據需要而自PCB 104連接及斷開。整合模組102藉由包括諸如晶粒106之兩個或兩個以上晶粒或半導體晶片而整合複數個功能性。晶粒106為小半導電材料塊體，在該等半導電材料塊體上製造給定功能性電路。晶粒106可(例如)為高輸入/輸出場可程式化閘陣列(FPGA)、特殊應用積體電路(ASIC)、微處理器、動態隨機存取記憶體(DRAM)、快取記憶體，或其任何組合。晶粒106向整合模組102提供功能性及處理能力。亦可將晶粒106認為係三維(3D)多高變薄晶粒或在一晶粒內含有3D積體電路，其中3D晶粒具有在垂直尺度上之一個以上位準處所製造的電晶體，而非僅具有平面電路晶片。
整合模組102亦包括高密度冷卻蓋或熱散播器124。冷卻蓋124使來自晶粒106之熱耗散以用於增加晶粒106之效能。冷卻蓋124可(例如)由Cu、Al、、陶瓷材料或另一導熱材料製成。冷卻蓋124可直接接觸晶粒106。或者，可將熱介面材料(TIM)置放於晶粒106與冷卻蓋124之間以用於自晶粒106至冷卻蓋124之熱傳遞。此熱介面材料可(例如)為導熱膏(諸如，Shin-Etsu熱膏)、金屬(諸如，銦或替代組合物焊料)，或聚合物黏接劑(諸如，Sylguard黏接劑)。另外，亦可將此熱介面材料置放於整合模組102內之其他組件周圍，以及晶粒106與冷卻蓋124之間。
冷卻蓋124附著至蓋罩126。蓋罩126可包括可附著至Si基板114之隔片128。然而，應注意，冷卻蓋124、蓋罩126及隔片128皆可為一個組件之一部分。又，應注意，蓋罩126及隔片128可充當用於整合模組102之保護覆蓋物且充當用於熱介面材料之固持器。
晶粒106藉由晶粒至矽載體互連110而連接至Si載體108。晶粒至矽載體互連110可(例如)為諸如PbSn、SnAg、Cu或SnCu之焊料、Cu至Cu互連、Au至Au互連、AuSn互連，或替代導電互連。晶粒至矽載體互連110支援精細間距互連(諸如，200微米間距、小於50微米間距或小於10微米間距)。另外，晶粒至矽載體互連110支援大於106 /cm2 之互連密度。
矽載體108為極薄層，諸如，對於200微米或甚至50微米之互連間距而言，其厚度小於150微米。對於小於10微米之互連間距而言，Si載體108之厚度可小於20微米或甚至小於10微米。具有精細間距互連之矽封裝可提供晶粒或晶粒堆疊106之間的高頻寬互連。由於Si載體108極薄，故其可經受處置中或來自熱應力及機械應力之變形及/或破裂。Si載體108提供向互連提供佈線之被動功能。另外，Si載體108可視情況包括(例如)解耦電容器、電阻器、電感器，及/或諸如電壓調節器、記憶體電路或其他主動電路之整合主動設備。與離散電容器相比，解耦電容器位於晶粒下方以節省空間且改良效能。電壓調節器提供將電壓個別地調節或分段至每一晶粒或在一晶粒內將電壓進行分段之能力以支援多個電壓位準。電壓調節器亦提供在模組內將分段進行電力開啟或電力關閉且在晶粒或晶粒堆疊內將分段進行電力開啟或電力關閉之能力。
另外，Si載體108包括貫穿矽導通孔或電鍍通孔112。貫穿矽導通孔112允許整合模組102之不同組件經封裝成更靠近在一起以藉由消除針對長金屬導線之需要而提供更快、更小且更低功率之資料處理系統。不同組件之此壓緊性顯著地減少整合模組102之總尺寸且提高資料在整合模組102之功能之間流動的速度。貫穿矽導通孔112為經由矽載體108而蝕刻之孔，其係由諸如Cu或W之金屬或某其他類型之導電材料填充。另外，貫穿矽導通孔112可包含用於垂直導體之單垂直孔、多個孔、桿體及/或環形形狀(亦即，類圓環形狀)且含有連接至用於電互連之頂部表面及底部表面之頂部導電襯墊及底部導電襯墊、導通孔及接點。
Si載體108藉由Si載體至Si基板互連116而連接至Si基板114。Si載體至Si基板互連116類似於晶粒至矽載體互連110。另外，如圖1之此說明性實例中所展示，Si載體至Si基板互連116可(例如)包含相對較大長橢圓形導電襯墊或凸塊。此等長橢圓形導電襯墊可用以容納在最大距離至中立位置之區域中之潛在組件未對準。
Si基板114為整合模組102之基層且可由矽材料、氧化物、氮化物及關聯導體製成。然而，Si基板114可替代地由陶瓷、玻璃陶瓷、玻璃、有機物及/或此等矽及封裝材料與此等關聯導體之組合製成。Si基板或封裝基板114充當用於矽載體108之機械支撐物及用於PCB 104之緩衝器。Si基板114包括貫穿矽導通孔118。封裝基板114包括垂直導通孔及/或引腳通孔118。貫穿矽導通孔118類似於貫穿矽導通孔112，或可在陶瓷或有機封裝中為垂直導通孔。
導電柱120增加Si載體114與PCB 104之間的互連高度。因此，導電柱120可減少由Si載體114與PCB 104之間的CTE失配所引起的有效熱應力。導電柱120可(例如)由Cu柱或焊料柱製成。或者，導電柱120可為球狀柵格陣列(BGA)、平台柵格陣列，或引腳互連。
Si基板114藉由互連122而連接至PCB 104。互連122可(例如)為導電襯墊或凸塊，諸如，焊料凸塊、金球、模製螺柱，或導電塑料。或者，互連122可為用於收納引腳互連之插座。
因此，整合模組102使用表面黏著技術(SMT)而連接至PCB 104。SMT為用於建構電子電路之方法，其中諸如整合模組102之表面黏著組件直接黏著至PCB 104之表面上。覆晶為一種類型之用於不需要任何導線結合之半導體設備的表面黏著技術。消除結合導線可將連接之延遲電感及電容減少十倍且可將電路徑縮短25倍至100倍。其結果為較高速度互連。
PCB 104機械地支撐諸如整合模組102之電子組件且將其電子地連接至其他電子組件。PCB 104可(例如)為類似於習知晶片載體之基底低溫共燒陶瓷(LTCC)基板。或者，PCB 104可為有機基板載體。另外，PCB 104可在其底部表面上包括習知結合襯墊BGA以用於表面黏著至(例如)主機板。此外，PCB 104可併有除了整合模組102之外的其他電子晶片，諸如，微處理器或控制晶片。
因此，說明性實施例基於將複數個大晶粒互連至矽載體及關聯模組總成上而提供一種用於整合模組之結構。更特定言之，說明性實施例係針對一種減輕與將矽電路及晶粒整合至矽載體上相關聯之問題的結構，矽載體連接至陶瓷或有機基板(在需要時與關聯加強件一起)。舉例而言，說明性實施例減輕歸因於Si載體與PCB之間的CTE失配而在互連上所誘導的應力。
對於最終產品及消費者而言，將多個晶粒整合於矽載體上允許較高效能、較小尺寸、較低功率、模組化設計及較低成本。因此，說明性實施例提供一種用以使用矽載體及關聯模組總成而對多個半導體晶片進行槓桿作用且整合此等多個晶片之方式。另外，說明性實施例藉由貫穿矽導通孔技術而利用晶粒、主動電路及/或被動電路之間的佈線而對矽載體進行槓桿作用。
根據說明性實施例，將多個晶粒整合至矽封裝模組總成上可經製造且使用精細間距互連而組裝至基底基板封裝。模組總成可支撐小尺度之矽載體或可支撐可大於20mm×20mm、大於30mm×30mm或甚至大於40mm×40mm之較大尺寸之矽載體。另外，模組總成可具有自晶粒至標準尺寸之矽封裝之互連尺寸(諸如，200微米間距，或非常小之50微米間距，或甚至為小於10微米之間距)。模組總成亦可支撐連接至大尺寸(其可大於200微米間距)之基底基板封裝之矽載體。
現參看圖2，根據說明性實施例而描繪矽載體封裝之例示性方塊圖。Si載體封裝200包括諸如圖1中之Si載體108之Si載體202。Si載體202整合晶粒204、206、208及210。晶粒204、206、208及210可(例如)為圖1中之晶粒或3D變薄晶粒堆疊106。
應注意，儘管Si載體202在此例示性說明中包括晶粒之2X2陣列，但說明性實施例不限制於此。Si載體202可(例如)包括晶粒之2XN陣列、4XN陣列、6XN陣列、8XN陣列或更多陣列，其中N可等於任何正整數。另外，晶粒204、206、208及210可表示晶粒之堆疊或晶粒與3D變薄晶粒堆疊之組合。換言之，每一晶粒可具有藉由用於垂直互連之貫穿矽導通孔而堆疊於其頂部上的一或多個變薄晶粒。
現參看圖3，根據說明性實施例而描繪具有窗框加強件之整合模組的例示性方塊圖。模組總成300類似於圖1中之模組總成100。模組總成300包括諸如圖1中之整合模組102及PCB 104之整合模組302及PCB 304。
整合模組302包括諸如圖1中之冷卻蓋124、晶粒106、Si載體108及Si基板114之冷卻蓋303、晶粒306、Si載體308及基板310。整合模組302亦包括在Si載體308與基板310之間的窗框加強件312。然而，應注意，儘管窗框加強件312在此特定說明中經描繪為僅在Si載體308與基板310之間，但窗框312亦可在Si載體308之外部邊緣周圍延伸、在晶粒306周圍延伸且接觸冷卻蓋303。窗框加強件312可(例如)由厚Si、Mo、W或陶瓷材料製成。
窗框加強件312附著至Si載體308以藉由減少由歸因於Si載體308與PCB 304之間的大CTE失配之熱偏移所引起的Si載體308之變形而增加Si載體308之機械完整性。因此，可減少互連上之應力。另外，窗框加強件312形成中心窗框區域或缺乏結構之中心區域。加強件312之此窗框設計使互連能夠群集於為有機基板之大基板(諸如，基板310)之中心區域處。
中心區域互連314可減少到達對於Si載體308與基板310之間的互連之中立位置的距離。因此，減少中心區域互連314上之應力。中心區域互連314類似於圖1中之Si載體至Si基板互連116。另外，在此說明性實例中，整合模組302包括用於與PCB 304之SMT互連之BGA 316。BGA 316類似於圖1中之導電柱120。
現參看圖4，根據說明性實施例而描繪具有完全加強件之整合模組的例示性方塊圖。模組總成400類似於圖3中之模組總成300。模組總成400包括諸如圖3中之整合模組302及PCB 304之整合模組402及PCB 404。
整合模組402包括諸如圖3中之冷卻蓋303、晶粒306、Si載體308及基板310之冷卻蓋406、晶粒408、Si載體410及基板412。另外，整合模組402亦包括在Si載體410與基板412之間的完全加強件414。不同於圖3中之未包括用以建立窗框之中心區域的窗框加強件312，完全加強件414完全地填充Si載體410與基板412之間的區域以增強Si載體410之機械完整性。除了機械支撐功能之外，完全加強件414可支撐機械功能、電功能、熱功能及/或光學功能之組合。
完全加強件414包括電導通孔416。類似於圖3中之中心區域互連314，電導通孔416位於完全加強件414之中心區域以減輕組件之CTE失配。又，完全加強件414可包括除了電導通孔416之外或代替電導通孔416之佈線(諸如，X-Y佈線)以分布電力及接地。
另外，完全加強件414可包括諸如環氧黏接劑、柔性黏接劑、高溫黏接劑(諸如，基於聚醯亞胺之黏接劑)或替代材料之黏接劑以用於機械黏接至Si載體410及基板412以改良機械完整性。此外，除了增加機械完整性之外，黏接劑可提供增強型互連腐蝕保護。完全加強件414可支援自(例如)非常小於104 /cm2 至大於106 /cm2 之互連密度。
現參看圖5，根據說明性實施例而展示說明用於製造矽載體之例示性製程的流程圖。圖5所示之製程可用以製造諸如圖1中之Si載體108之Si載體。
該製程在組裝器(諸如，人或機器)擷取晶圓以用於製造Si載體(步驟502)時開始。接著，組裝器對晶圓執行朝向貫穿矽導通孔(諸如，圖1中之貫穿矽導通孔112)之深反應式離子蝕刻(RIE)(步驟504)。然後，組裝器(諸如)藉由熱氧化而使任何電導通孔絕緣且(諸如)藉由襯套晶種(liner-seed)(諸如，Ta/TaN，及(諸如)藉由CVD、W或電鍍Cu之導體)而使任何電導通孔金屬化(步驟506)。
隨後，組裝器跳越步驟508且建構諸如電容器、電感器、後段製程(BEOL)佈線、導通孔、襯墊及層間介電之被動電路以提供晶粒互連。所得組件可包括在晶圓上之被動組件，諸如，平行板電容器、電感器或其任何組合。接著，組裝器使用諸如後段製程(BEOL)佈線之佈線而互連被動組件(步驟510)。接著，組裝器將處置晶圓附著至晶圓以用於安全處置(步驟512)、使晶圓變薄(步驟514)，且將背面氧化物沈積至晶圓(步驟516)。然後，組裝器將板襯墊及導電凸塊(諸如，圖1中之Si載體至Si基板互連116)沈積至晶圓(步驟518)。
接著，組裝器分割晶圓(步驟520)。隨後，組裝器測試Si載體之適當功能(步驟522)。該製程此後終止。
針對圖5之替代製程流程可包括在晶圓上建構半導體設備，諸如，電路、電阻器、電感器、電壓調節器、解耦電容器或其任何組合。在此替代製程中，組裝器在步驟506中利用諸如熱氧化之介電絕緣體沈積。隨後，組裝器(諸如)藉由多晶矽而執行臨時導通孔填充步驟。然後，組裝器執行前段製程電路製造(步驟508)。接著，組裝器移除臨時導通孔填充。然後，組裝器(諸如)藉由Ta/TaN而執行襯套晶種沈積且(諸如)藉由W或Cu(諸如，電鍍Cu)之化學氣相沈積而執行金屬化。接著，組裝器使用諸如步驟510中之後段製程(BEOL)佈線之佈線而互連設備。
針對圖5之另一替代製程流程可包括後導通孔製程。在此替代製程中，在(諸如)藉由步驟506中之熱氧化之介電絕緣體沈積之後，其繼之以(諸如)藉由多晶矽之臨時導通孔填充步驟、步驟508中之前段製程電路製造、步驟510中之後段製程(BEOL)佈線、步驟512中之處置晶圓附著及步驟514中之晶圓變薄，組裝器移除臨時導通孔填充。另外，組裝器(諸如)藉由Ta/TaN而執行襯套晶種沈積且(諸如)藉由Cu(諸如，電鍍Cu)而執行金屬化。另外，組裝器在步驟516中沈積背面氧化物(諸如，PECVD)及/或在步驟518中沈積Cu/Ni/Au板襯墊及焊料。
現參看圖6，根據說明性實施例而展示說明用於將矽載體附著至基底基板之例示性製程的流程圖。圖6所示之製程可用以組裝諸如圖1中之模組總成100之模組總成。
該製程開始於組裝器將諸如圖1中之Si載體108之Si載體附著至諸如圖1中之基板114之基底陶瓷基板(步驟602)時。基底陶瓷基板可(例如)為LTCC基板。在步驟602中將Si載體附著至基底陶瓷基板之後，組裝器釋放處置晶圓(步驟604)且將諸如圖1中之晶粒106之複數個晶粒或晶粒堆疊附著至Si載體(步驟606)。
接著，組裝器將熱介面材料及整合模組硬體(諸如，圖1中之冷卻蓋124、蓋罩126及隔片128)附著至基底陶瓷基板(步驟608)。隨後，組裝器透過測試證實整合模組(諸如圖1中之整合模組102)正適當地運行(步驟610)。然後，組裝器使用SMT而將適當運行之整合模組附著至諸如圖1中之PCB 104之PCB(步驟612)。該製程此後終止。
現參看圖7，根據說明性實施例而展示說明用於將矽載體附著至加強件及基底基板之例示性製程的流程圖。圖7所示之製程可用以組裝諸如圖3中之模組總成300之模組總成。
該製程在組裝器將諸如圖3中之Si載體308之大Si載體附著至諸如圖3中之加強件312之加強件(步驟702)時開始。接著，組裝器將具有經附著加強件之大Si載體附著至諸如圖3中之基板310之基底有機基板(步驟704)。在步驟702及步驟704中將大Si載體附著至加強件及基底有機基板之後，組裝器釋放處置晶圓(步驟706)且將諸如圖3中之晶粒306之複數個晶粒附著至大Si載體(步驟708)。
接著，組裝器將熱介面材料及整合模組硬體(諸如，冷卻蓋303)附著至加強件及基底有機基板(步驟710)。然後，組裝器測試諸如圖3中之整合模組302之整合模組之適當功能(步驟712)。隨後，組裝器使用SMT而將適當運行之整合模組附著至諸如圖3中之PCB 304之PCB(步驟714)。該製程此後終止。
因此，說明性實施例提供一種用於包括高階晶粒至晶粒互連性之改良型整合模組的方法及裝置，其使用較大的薄Si載體以增加資料處理系統效能。上文所描述之電路為用於積體電路晶片之設計的一部分。晶片設計係以圖形電腦程式設計語言而建立，且儲存於電腦儲存媒體(諸如，碟片、磁帶、實體硬碟機，或(諸如)在儲存存取網路中之虛擬硬碟機)中。若設計者未製造晶片或未製造用以製造晶片之光微影光罩，則設計者藉由實體方式(例如，藉由提供儲存設計之儲存媒體的複本)或電子地(例如，經由網際網路)而將所得設計直接或間接傳輸至該等實體。接著將所儲存設計轉換為適當格式(例如，GDSII)以用於製造光微影光罩，其通常包括待形成於晶圓上的在討論中之晶片設計之多個複本。光微影光罩用以界定晶圓之待蝕刻或另外處理的區域(及/或其上之層)。
已出於說明及描述之目的而呈現本發明之描述，且該描述不意欲為詳盡的或將本發明限於所揭示之形式。許多修改及變化對於一般熟習此項技術者而言將顯而易見。選擇及描述實施例，以便最佳地解釋本發明之原理、實際應用，且使一般熟習此項技術者能夠針對具有適合於所涵蓋之特定用途之各種修改的各種實施例而理解本發明。
100．．．模組總成
102．．．整合模組
104．．．印刷電路板(PCB)
106．．．晶粒/晶粒堆疊
108．．．Si載體
110．．．晶粒至矽載體互連
112．．．貫穿矽導通孔/電鍍通孔
114．．．Si基板/封裝基板/Si載體
116．．．Si載體至Si基板互連
118．．．貫穿矽導通孔/垂直導通孔/引腳通孔
120．．．導電柱
122．．．互連
124．．．冷卻蓋/熱散播器
126．．．蓋罩
128．．．隔片
200．．．Si載體封裝
202．．．Si載體
204．．．晶粒
206．．．晶粒
208．．．晶粒
210．．．晶粒
300．．．模組總成
302．．．整合模組
303．．．冷卻蓋
304．．．印刷電路板(PCB)
306．．．晶粒
308．．．Si載體
310．．．基板
312．．．窗框加強件
314．．．中心區域互連
316．．．球狀柵格陣列(BGA)
400．．．模組總成
402．．．整合模組
404．．．印刷電路板(PCB)
406．．．冷卻蓋
408．．．晶粒
410．．．Si載體
412．．．基板
414．．．完全加強件
416．．．電導通孔
圖1為根據說明性實施例之模組總成的例示性方塊圖；
圖2為根據說明性實施例之矽或體封裝的例示性方塊圖；
圖3為根據說明性實施例之具有窗框加強件之整合模組的例示性方塊圖；
圖4為根據說明性實施例之具有完全加強件之整合模組的例示性方塊圖；
圖5為說明根據說明性實施例之用於製造矽載體之例示性製程的流程圖；
圖6為說明根據說明性實施例之用於將矽載體附著至基底基板之例示性製程的流程圖；且
圖7為說明根據說明性實施例之用於將矽載體附著至加強件及基底基板之例示性製程的流程圖。
100．．．模組總成
102．．．整合模組
104．．．印刷電路板(PCB)
106．．．．．．晶粒/晶粒堆疊
108．．．Si載體
110．．．晶粒至矽載體互連
112．．．貫穿矽導通孔/電鍍通孔
114．．．Si基板/封裝基板/Si載體
116．．．Si載體至Si基板互連
118．．．貫穿矽導通孔/垂直導通孔/引腳通孔
120．．．導電柱
122．．．互連
124．．．冷卻蓋/熱散播器
126．．．蓋罩
128．．．隔片

Claims (19)

  1. 一種整合模組，其包含：一矽載體，其具有貫穿矽導通孔，其中複數個晶粒連接至該矽載體之一頂面，其中該複數個晶粒與該矽載體之間的一互連密度大於103 /cm2 ；及一基板，其連接至該矽載體之一底面，其中該基板經由該等貫穿矽導通孔而耦接至該複數個晶粒。
  2. 如請求項1之整合模組，其中該矽載體包括電壓調節器，且其中該等電壓調節器將電壓分段至該複數個晶粒以在該複數個晶粒之間提供複數個電壓位準，且其中該等電壓調節器在該整合模組內將分段進行電力開啟及電力關閉。
  3. 如請求項2之整合模組，其中一電壓調節器在一晶粒內將電壓位準進行分段以在該晶粒內提供複數個電壓位準，且其中該電壓調節器在該晶粒內將分段進行電力開啟及電力關閉。
  4. 如請求項1之整合模組，其中該矽載體包括解耦電容器。
  5. 如請求項1之整合模組，其中該矽載體之一尺寸大於20毫米×20毫米。
  6. 如請求項1之整合模組，其中該複數個晶粒與該矽載體之間的一互連間距小於200微米。
  7. 如請求項1之整合模組，其中該矽載體具有一小於100微米之間距。
  8. 如請求項1之整合模組，其中該矽載體與該基板之間的一互連間距小於或等於200微米。
  9. 如請求項1之整合模組，其中該複數個晶粒接觸一冷卻蓋，且其中該冷卻蓋使來自該複數個晶粒之熱耗散。
  10. 如請求項9之整合模組，其中一熱介面材料插入於該冷卻蓋與該複數個晶粒之間，且其中該熱介面材料為一導熱膏、一金屬或一聚合物黏接劑中之一者。
  11. 如請求項1之整合模組，其中該複數個晶粒執行複數個功能。
  12. 如請求項1之整合模組，其中一加強件附著於該矽載體與該基板之間，且其中該加強件向該矽載體提供機械支撐以防止歸因於該矽載體與一印刷電路板之間的一熱膨脹係數失配之變形，且其中該加強件包括導通孔及X-Y佈線中之至少一者。
  13. 如請求項12之整合模組，其中該加強件為一窗框加強件，且其中該窗框加強件提供該矽載體與該基板之間的中心互連以減少該矽載體與該基板之間的互連應力。
  14. 如請求項1之整合模組，其中該矽載體與該基板之間的一互連包括長橢圓形導電襯墊。
  15. 如請求項1之整合模組，其中該整合模組經表面黏著至一印刷電路板。
  16. 如請求項12之整合模組，其中一黏接劑用以將該加強件附著至該矽載體及該基板，且其中該黏接劑向該矽載體與該基板之間的互連提供機械支撐及腐蝕保護。
  17. 如請求項1之整合模組，其中該複數個晶粒中之一或多者具有堆疊於頂部上之一或多個晶粒。
  18. 一種用於組裝一模組總成之方法，該方法包含：在一矽載體上建構複數個設備；互連該矽載體上之該複數個設備；將複數個導電凸塊沈積於該矽載體之一第一表面上及該矽載體之一第二表面上；及經由該複數個導電凸塊而將複數個晶粒附著至該矽載體之該第一表面且將一基板附著至該矽載體之該第二表面以形成一整合模組，其中該複數個晶粒與該矽載體之間的一互連密度大於103 /cm2 。
  19. 如請求項18之方法，其進一步包含：將一加強件附著於該基板與該矽載體之該第二表面之間以防止該矽載體歸因於該矽載體與該印刷電路板之間的一熱膨脹係數失配之變形。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10504881B2 (en) 2014-04-29 2019-12-10 Micron Technology, Inc. Stacked semiconductor die assemblies with support members and associated systems and methods

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7173590B2 (en) * 2004-06-02 2007-02-06 Sony Corporation Pixel circuit, active matrix apparatus and display apparatus
JP2015060097A (ja) 2013-09-19 2015-03-30 ソニー株式会社 光伝送モジュール
JP2009231635A (ja) * 2008-03-24 2009-10-08 Shinko Electric Ind Co Ltd 配線基板及びその製造方法、及び半導体装置及びその製造方法
JP5150518B2 (ja) * 2008-03-25 2013-02-20 パナソニック株式会社 半導体装置および多層配線基板ならびにそれらの製造方法
US7928562B2 (en) * 2008-07-22 2011-04-19 International Business Machines Corporation Segmentation of a die stack for 3D packaging thermal management
US9406561B2 (en) * 2009-04-20 2016-08-02 International Business Machines Corporation Three dimensional integrated circuit integration using dielectric bonding first and through via formation last
US8295056B2 (en) * 2009-07-22 2012-10-23 International Business Machines Corporation Silicon carrier structure and method of forming same
US9721868B2 (en) * 2009-07-30 2017-08-01 Taiwan Semiconductor Manufacturing Company, Ltd. Three dimensional integrated circuit (3DIC) having a thermally enhanced heat spreader embedded in a substrate
US9999129B2 (en) 2009-11-12 2018-06-12 Intel Corporation Microelectronic device and method of manufacturing same
US8455356B2 (en) 2010-01-21 2013-06-04 International Business Machines Corporation Integrated void fill for through silicon via
TWI419302B (zh) * 2010-02-11 2013-12-11 Advanced Semiconductor Eng 封裝製程
JP5609144B2 (ja) * 2010-02-19 2014-10-22 ソニー株式会社 半導体装置および貫通電極のテスト方法
US8901747B2 (en) 2010-07-29 2014-12-02 Mosys, Inc. Semiconductor chip layout
US8595429B2 (en) 2010-08-24 2013-11-26 Qualcomm Incorporated Wide input/output memory with low density, low latency and high density, high latency blocks
US20120068339A1 (en) * 2010-09-21 2012-03-22 Mosys, Inc. VLSI Package for High Performance Integrated Circuit
US8105875B1 (en) * 2010-10-14 2012-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Approach for bonding dies onto interposers
US8936966B2 (en) 2012-02-08 2015-01-20 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods for semiconductor devices
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8421245B2 (en) 2010-12-22 2013-04-16 Intel Corporation Substrate with embedded stacked through-silicon via die
TWI483355B (zh) * 2011-10-25 2015-05-01 Nat Chip Implementation Ct Nat Applied Res Lab 模組化積體電路之製造方法
TWI449152B (zh) 2011-12-21 2014-08-11 Ind Tech Res Inst 半導體元件堆疊結構
US8697542B2 (en) 2012-04-12 2014-04-15 The Research Foundation Of State University Of New York Method for thin die-to-wafer bonding
US8680674B2 (en) * 2012-05-31 2014-03-25 Freescale Semiconductor, Inc. Methods and structures for reducing heat exposure of thermally sensitive semiconductor devices
US8563403B1 (en) 2012-06-27 2013-10-22 International Business Machines Corporation Three dimensional integrated circuit integration using alignment via/dielectric bonding first and through via formation last
US9093429B2 (en) 2012-06-27 2015-07-28 Freescale Semiconductor, Inc. Methods and structures for reducing heat exposure of thermally sensitive semiconductor devices
US9319586B2 (en) * 2013-01-24 2016-04-19 Stmicroelectronics S.R.L. Method and device for stabilizing video sequences, related video-capture apparatus and computer-program product
US9331054B2 (en) * 2013-03-14 2016-05-03 Mediatek Inc. Semiconductor package assembly with decoupling capacitor
US9886072B1 (en) 2013-06-19 2018-02-06 Altera Corporation Network processor FPGA (npFPGA): multi-die FPGA chip for scalable multi-gigabit network processing
US9627365B1 (en) 2015-11-30 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-layer CoWoS structure
JP6862087B2 (ja) * 2015-12-11 2021-04-21 株式会社アムコー・テクノロジー・ジャパン 配線基板、配線基板を有する半導体パッケージ、およびその製造方法
US9831148B2 (en) 2016-03-11 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package including voltage regulators and methods forming same
WO2018106226A1 (en) * 2016-12-07 2018-06-14 Intel Corporation Multi-chip packages and sinterable paste for use with thermal interface materials
KR20180112463A (ko) * 2017-04-04 2018-10-12 에스케이하이닉스 주식회사 팬 아웃 웨이퍼 레벨 패키지 제조 방법
US11024590B2 (en) * 2017-12-29 2021-06-01 Seagate Technology Llc And placement of de-coupling capacitors for PDN design
US11081392B2 (en) * 2018-09-28 2021-08-03 Taiwan Semiconductor Manufacturing Co., Ltd. Dicing method for stacked semiconductor devices
CN112542391B (zh) * 2020-12-04 2022-11-11 上海易卜半导体有限公司 芯片互联方法、互联器件以及形成封装件的方法
US11450622B2 (en) * 2021-01-20 2022-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010037565A1 (en) * 1998-12-03 2001-11-08 Chandrika Prasad Process for forming a multi-level thin-film electronic packaging structure
US20040245965A1 (en) * 2002-03-28 2004-12-09 Zhang Michael T. Shunt voltage regulator and method of using
CN1629671A (zh) * 2003-12-17 2005-06-22 国际商业机器公司 用于光互连模块的硅载体
US20060131719A1 (en) * 2003-05-30 2006-06-22 Seiko Epson Corporation Semiconductor device, electronic device, electronic apparatus, and method of manufacturing semiconductor device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7189595B2 (en) * 2001-05-31 2007-03-13 International Business Machines Corporation Method of manufacture of silicon based package and devices manufactured thereby
JP3583396B2 (ja) * 2001-10-31 2004-11-04 富士通株式会社 半導体装置の製造方法、薄膜多層基板及びその製造方法
US6974330B2 (en) * 2002-08-08 2005-12-13 Micron Technology, Inc. Electronic devices incorporating electrical interconnections with improved reliability and methods of fabricating same
US7736950B2 (en) * 2003-11-10 2010-06-15 Stats Chippac, Ltd. Flip chip interconnection

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010037565A1 (en) * 1998-12-03 2001-11-08 Chandrika Prasad Process for forming a multi-level thin-film electronic packaging structure
US20040245965A1 (en) * 2002-03-28 2004-12-09 Zhang Michael T. Shunt voltage regulator and method of using
US20060131719A1 (en) * 2003-05-30 2006-06-22 Seiko Epson Corporation Semiconductor device, electronic device, electronic apparatus, and method of manufacturing semiconductor device
CN1629671A (zh) * 2003-12-17 2005-06-22 国际商业机器公司 用于光互连模块的硅载体

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10504881B2 (en) 2014-04-29 2019-12-10 Micron Technology, Inc. Stacked semiconductor die assemblies with support members and associated systems and methods
US11101262B2 (en) 2014-04-29 2021-08-24 Micron Technology, Inc. Stacked semiconductor die assemblies with support members and associated systems and methods
US11855065B2 (en) 2014-04-29 2023-12-26 Micron Technology, Inc. Stacked semiconductor die assemblies with support members and associated systems and methods

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