CN112542391B - 芯片互联方法、互联器件以及形成封装件的方法 - Google Patents

芯片互联方法、互联器件以及形成封装件的方法 Download PDF

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CN112542391B
CN112542391B CN202011408981.5A CN202011408981A CN112542391B CN 112542391 B CN112542391 B CN 112542391B CN 202011408981 A CN202011408981 A CN 202011408981A CN 112542391 B CN112542391 B CN 112542391B
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chip
interconnection
pads
bumps
layer
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CN112542391A (zh
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李维平
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Shanghai Yibu Semiconductor Co ltd
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Shanghai Yibu Semiconductor Co ltd
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Priority to CN202011408981.5A priority Critical patent/CN112542391B/zh
Publication of CN112542391A publication Critical patent/CN112542391A/zh
Priority to KR1020210171478A priority patent/KR102665955B1/ko
Priority to TW110145134A priority patent/TWI823201B/zh
Priority to US17/542,417 priority patent/US20220181297A1/en
Priority to US17/542,416 priority patent/US20220181296A1/en
Priority to US17/542,415 priority patent/US12087734B2/en
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Abstract

本发明提供了芯片互联方法、互联器件以及形成封装件的方法，该芯片互联方法包括：将第一芯片和第二芯片设置于载体表面，其中，第一芯片的上方表面形成有多个第一凸点，第二芯片的上方表面形成有多个第二凸点，第一凸点的接触面小于第二凸点；将互联器件附接至第一芯片和第二芯片的部分上方表面，互联器件的一侧表面形成有用于接合至多个第一凸点的多个第一焊盘以及用于接合至多个第二凸点的多个第二焊盘，其中，将互联器件的多个第一焊盘对准接合至多个第一凸点，以使互联器件的多个第二焊盘和多个第二凸点实现自对准接合。利用上述方法，避免由于误差而导致的难以对准接合的问题。

Description

芯片互联方法、互联器件以及形成封装件的方法
技术领域
本发明属于半导体领域，具体涉及芯片互联方法、互联器件以及形成封装件的方法。
背景技术
本部分旨在为权利要求书中陈述的本发明的实施方式提供背景或上下文。此处的描述不因为包括在本部分中就承认是现有技术。
随着人工智能时代的到来，半导体集成电路的发展趋势是功能越多且计算速度越快。由于“摩尔定律”，如果简单使用大芯片的SOC集成来满足这个发展趋势，无疑会使电路设计的难度越来越高，制造成本越来越昂贵。更为实际的解决方案则是采用多个小芯片的异质集成技术来完成功能集成的目的。基于此，目前对于高端封装的重要任务是发展高效率，高密度的多芯片互联技术，通过裸芯片之间的直接联接来形成芯片的物理层功能区块，以此来代替大芯片的SOC集成，实现低成本和高自由度，并具有相同的功能性。
现有的多芯片互联技术中，在半导体芯片的封装过程中难以避免地存在安装误差，导致难以实现多芯片与互联器件之间的对准接合。
发明内容
针对上述现有技术中存在的问题，提出了芯片互联方法、互联器件以及形成封装件的方法，利用这种方法、器件和封装件，能够解决上述问题。
本发明提供了以下方案。
第一方面，提供一种芯片互联方法，包括：将第一芯片和第二芯片设置于载体表面，其中，第一芯片的上方表面形成有多个第一凸点，第二芯片的上方表面形成有多个第二凸点，第一凸点的接触面小于第二凸点；将互联器件附接至第一芯片和第二芯片的部分上方表面，互联器件的一侧表面形成有用于接合至多个第一凸点的多个第一焊盘以及用于接合至多个第二凸点的多个第二焊盘，其中，将互联器件的多个第一焊盘对准接合至多个第一凸点，以使互联器件的多个第二焊盘和多个第二凸点实现自对准接合。
在一些可能的实施方式中，第一芯片的多个第一凸点为多个高密度凸点，第二芯片的多个第二凸点为多个低密度凸点。
在一些可能的实施方式中，在互联器件的多个第一焊盘和多个第二焊盘之间形成有扇出电路，以使每组芯片包含的第一芯片通过互联器件能够电性连接至第二芯片。
在一些可能的实施方式中，互联器件形成为具有垂直互联通孔的互联器件。
在一些可能的实施方式中，互联器件形成为无源器件或有源器件。
第二方面，提供一种互联器件，互联器件的一侧表面形成有多个第一焊盘和多个第二焊盘，其中，多个第一焊盘用于接合至第一芯片，多个第二焊盘用于接合至第二芯片；互联器件的多个第一焊盘和多个第二焊盘之间形成有扇出电路，用于实现多个第一焊盘和多个第二焊盘之间的电性连接。
在一些可能的实施方式中，互联器件形成为具有垂直互联通孔的互联器件。
在一些可能的实施方式中，互联器件形成为无源器件或有源器件。
在一些可能的实施方式中，互联器件采用半导体材料，包括以下中的一种或多种：硅(Si)、碳化硅(SiC)、砷化镓(GaAs)、氮化镓(GaN)。
在一些可能的实施方式中，互联器件采用无机材料，包括以下中的一种或多种：玻璃、陶瓷。
在一些可能的实施方式中，互联器件采用封装基板材料，包括以下中的一种或多种：印刷电路基板(PCB)，塑封基板(EMC)，柔性电路基板。
在一些可能的实施方式中，互联器件采用金属基板材料，包括以下中的一种或多种：铜、铝。
在一些可能的实施方式中，互联器件附带具有集成电路、微机电系统(MEMS)、光电元器件以及被动元器件(IPD)的功能。
第三方面，提供一种形成封装件的方法，包括：提供载体和至少一组芯片，其中每组芯片至少包括第一芯片和第二芯片；将每组芯片包含的第一芯片和第二芯片正面朝上装设于载体的表面，其中第一芯片的上方表面具有第一凸点，第二芯片的上方表面具有第二凸点；利用如第一方面的方法将互联器件附接至每组芯片包含的第一芯片和第二芯片的部分上方表面，以使每组芯片包含的第一芯片通过互联器件能够电性连接至第二芯片；在第一芯片和第二芯片的周围形成一塑封层，其中第一芯片、第二芯片和互联器件嵌于塑封层内；在塑封层远离载体的一侧表面进行减薄处理，以暴露出第一芯片的第一凸点和第二芯片的第二凸点；在塑封层暴露出第一凸点和第二凸点的一侧表面形成第三凸点；以及，移除载体。
在一些可能的实施方式中，芯片组数大于1，方法还包括：移除载体之后，对形成的封装件进行切割以获得多个单元封装体，其中每个单元封装体包含一组芯片。
本申请实施例采用的上述至少一个技术方案能够达到以下有益效果：可以理解，在半导体芯片的封装过程中，难以避免地存在安装误差，本实施例中，第二凸点由于其更大的接触面积而具有更大的容纳误差空间，通过先精确对准接合第一凸点和第一焊盘，由此互联器件的多个第二焊盘能够自对准接合至具有更大的容纳误差空间的多个第二凸点上。避免由于误差而导致的难以对准接合的问题。
应当理解，上述说明仅是本发明技术方案的概述，以便能够更清楚地了解本发明的技术手段，从而可依照说明书的内容予以实施。为了让本发明的上述和其它目的、特征和优点能够更明显易懂，以下特举例说明本发明的具体实施方式。
附图说明
通过阅读下文的示例性实施例的详细描述，本领域普通技术人员将明白本文所述的优点和益处以及其他优点和益处。附图仅用于示出示例性实施例的目的，而并不认为是对本发明的限制。而且在整个附图中，用相同的标号表示相同的部件。在附图中：
图1为根据本发明一实施例的形成封装件的方法的流程示意图；
图2A至图2E为根据本发明一实施例在形成封装件的过程中的中间阶段的截面示意图；
图3A至图3C为根据本发明另一实施例在进行芯片互联的过程中的示意图；
图4为根据本发明一实施例的使用互联器件的堆叠芯片封装件的结构示意图。
在附图中，相同或对应的标号表示相同或对应的部分。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施例。虽然附图中显示了本公开的示例性实施例，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施例所限制。相反，提供这些实施例是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，将互联器件13附接至第一芯片11和第二芯片12的上方表面可以包括第一芯片11、第二芯片12和互联器件13直接接触形成的实施例，并且也可以包括在第一芯片11、第二芯片12和互联器件13之间可以形成额外的部件，从而使得第一芯片11、第二芯片12和互联器件13可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
应理解，诸如“包括”或“具有”等术语旨在指示本说明书中所公开的特征、数字、步骤、行为、部件、部分或其组合的存在，并且不旨在排除一个或多个其他特征、数字、步骤、行为、部件、部分或其组合存在的可能性。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上方”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
另外还需要说明的是，在不冲突的情况下，本发明中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本发明。
图1为根据本申请一实施例的形成封装件的方法100的流程示意图。如图1所示，该方法100可以包括步骤101～102。
步骤101、将第一芯片和第二芯片设置于载体表面。
参考图2A，可以按照事先设计好的预设芯片间距或预设芯片摆放位置将第一芯片11和第二芯片12正面朝上装设于载体10的表面。第一芯片11的上方表面具有第一凸点21，第二芯片12的上方表面具有第二凸点22，凸点也可称为芯片管脚，将芯片具有芯片管脚的一侧表面称之为正面，将与正面相对的一侧表面称之为背面。例如，在一些实施例中，第一凸点21和第二凸点22可以形成为由导电材料制成的焊料凸点，导电材料包括Cu、Ag、Au等或它们的合金，也可以包括其他材料。例如，在一些实施例中，可以使用诸如封装机器的自动化机器或手工地将两个或多个芯片联接至载体10。在一些实施例中，可以使用粘合膜(未示出)或管芯贴膜(未示出)将第一芯片11和第二芯片12的背面联接至载体10的任意一侧面，使得第一芯片11和第二芯片12的正面远离载体10向外示出，在半导体封装中，也可称之为正面朝上(face-up)。
参考图3A，示出了第一芯片11和第二芯片12的顶视示意图。在本实施例中，第一芯片11和第二芯片12并排间隔地设置在载体表面，第一芯片的第一边缘区域和第二芯片的第二边缘区域分布在第一芯片和第二芯片之间的间隙两侧。第一芯片11的第一边缘区域中包含多个第一凸点21，第二芯片的第二边缘区域中包含多个第二凸点22。其中，第一凸点21的接触面小于第二凸点22。
可以理解，在半导体芯片的封装过程中，难以避免地存在安装误差。在步骤101中，将第一芯片11和第二芯片12装设于载体10的一侧表面时，可能会产生一定程度的安装间距误差。比如，第一芯片11和第二芯片12之间的实际芯片间距相较于事先设计好的预设芯片间距更近或者更远。又比如，事先设计好的芯片摆放位置为第一芯片11和第二芯片12并排平行地摆放，而实际摆放过程中，第一芯片11和第二芯片12并未能完全平行地摆放，而是存在角度误差。诸如此类的安装误差难以避免地存在于芯片摆放的过程中。
步骤102、将互联器件附接至第一芯片和第二芯片的部分上方表面。
参考图3B，其中，互联器件13的一侧表面形成有多个第一焊盘131和多个第二焊盘132，多个第一焊盘131用于接合至第一芯片11上方表面形成的多个第一凸点21，多个第二焊盘132用于接合至第二芯片12上方表面形成的多个第二凸点22。
在本实施例中，互联器件13用于跨越第一芯片和第二芯片之间的间隙而附接在第一芯片的第一边缘区域和第二芯片的第二边缘区域上方。互联器件13的一侧表面分布的多个第一焊盘131用于与第一边缘区域中包含多个第一凸点21相互接合，分布的多个第二焊盘132用于与第二边缘区域中包含多个第二凸点22相互接合。应当理解，互联器件中的多个第一焊盘131和多个第二焊盘132的焊盘位置是由预设芯片摆放位置以及第一芯片11、第二芯片12上的凸点分布位置而确定的。比如，当在芯片设计中所确定的第一芯片11和第二芯片12之间的芯片间距较宽时，图3A所示出的第一芯片11和第二芯片12需按照设计的较宽的芯片间距进行摆放，图3B所示出的互联器件13也同样被设计为更宽，具体而言，互联器件13中第一焊盘区域和第二焊盘区域之间的宽度更宽。换言之，在理想情况下，也即不存在上述安装误差的情况下，互联器件13可以附接在第一芯片11和第二芯片12的上方，且互联器件13中的多个第一焊盘131和多个第二焊盘132能够同时精准地接合至第一芯片和第二芯片上方的对应凸点上。
由于在步骤101中，难以避免地存在安装误差。本实施例中，将互联器件13附接至第一芯片11和第二芯片12的上方表面的具体安装步骤为：将互联器件13的多个第一焊盘对准接合至多个第一凸点，以使互联器件13的多个第二焊盘132自对准接合至第二芯片的多个第二凸点22，换言之，以已经对准接合的多个第一凸点21和第一焊盘131为参考基准，使互联器件13的多个第二焊盘132基于器件自身张力而自对准接合至多个第二凸点。
参见图3C，本实施例中，通过先精确对准第一凸点21和第一焊盘131，能够实现第一凸点21和第一焊盘131之间的对准接合，互联器件的多个第一焊盘131和多个第一凸点21互相接合之后，互联器件的实际放置位置已经确定下来。此时第二凸点22由于其更大的接触面积而具有更大的容纳误差空间，基于互联器件13的自身张力，多个第二焊盘132能够自对准接合至具有更大的容纳误差空间的多个第二凸点上。由此，能够实现多个第一凸点21和多个第一焊盘131之间的对准接合，多个第二凸点22和多个第二焊盘132之间的自动对准接合，避免由于误差而导致的难以对准接合的问题。
在一些实施方式中，第一凸点21和第一焊盘131可以具有相同或类似的形状、大小的接触面，由此可以便于第一凸点21和第一焊盘131之间的精确对准。避免或减小因为第一凸点21和第一焊盘131之间的对准误差而额外导致第二凸点22和第二焊盘132之间产生的对准误差增加。
在一些实施方式中，参见图3A，第一芯片11的多个第一凸点21为多个高密度凸点，第二芯片12的多个第二凸点22为多个低密度凸点。由此，高密度第一凸点21和第一焊盘131能够实现对准接合，而低密度第一凸点22由于其更大的接触面积而具有更大的容纳误差空间，避免由于误差而导致的难以对准接合的问题。
在一些实施方式中，参见图3B，在互联器件13的多个第一焊盘131和多个第二焊盘132之间形成有扇出(fan-out)电路133，扇出电路133用于使联接的一组第一焊盘和第二焊盘之间电性联接，从而在将互联器件13附接在第一芯片11和第二芯片12上之后，使第一芯片11通过互联器件13能够电性连接至第二芯片12。
在一些另外的实施方式中，在互联器件13的多个第一焊盘131和多个第二焊盘132之间也可以形成其他任何类型的互联电路，只要该互联电路能够实现任一个或多个第一焊盘131和任一个或多个第二焊盘132之间的电性联接即可。
在一些实施方式中，第一焊盘131的接触面小于第二焊盘132的接触面，由此第二焊盘132由于其更大的接触面积而具有更大的容纳误差空间，在第一焊盘131和第一凸点21对准接合之后，互联器件13的具有更大的容纳误差空间的多个第二焊盘132能够自对准接合至具有更大的容纳误差空间的多个第二凸点上。进一步提高了误差容错程度。
本申请实施例还提供一种互联器件，图3B示出了该互联器件13的结构示意图。
参见图3，该互联器件13的一侧表面形成有多个第一焊盘131和多个第二焊盘132，其中，多个第一焊盘131用于接合至第一芯片，多个第二焊盘132用于接合至第二芯片；互联器件13的多个第一焊盘131和多个第二焊盘132之间形成有扇出电路133，用于实现多个第一焊盘和多个第二焊盘之间的电性连接。
在一些可能的实施方式中，互联器件形成为具有垂直互联通孔的互联器件。
在一些可能的实施方式中，互联器件形成为无源器件或有源器件。
在一些可能的实施方式中，互联器件采用半导体材料，包括以下中的一种或多种：硅(Si)、碳化硅(SiC)、砷化镓(GaAs)、氮化镓(GaN)。
在一些可能的实施方式中，互联器件采用无机材料，包括以下中的一种或多种：玻璃、陶瓷。
在一些可能的实施方式中，互联器件采用封装基板材料，包括以下中的一种或多种：印刷电路基板(PCB)，塑封基板(EMC)，柔性电路基板。
在一些可能的实施方式中，互联器件采用金属基板材料，包括以下中的一种或多种：铜、铝。
在一些可能的实施方式中，互联器件附带具有集成电路、微机电系统(MEMS)、光电元器件以及被动元器件(IPD)的功能。本申请实施例还提供了一种形成封装件的方法。图2A-图2E示出本申请一实施例的过程中的中间阶段的截面示意图。
该方法包括：提供载体10和至少一组芯片，其中每组芯片至少包括第一芯片11和第二芯片12；参见图2A，将每组芯片包含的第一芯片11和第二芯片12正面朝上装设于载体10的表面，其中第一芯片11的上方表面具有第一凸点21，第二芯片12的上方表面具有第二凸点22；利用如上述实施例的方法将互联器件13附接至每组芯片包含的第一芯片11和第二芯片12的部分上方表面，以使每组芯片包含的第一芯片11通过互联器件13能够电性连接至第二芯片12；参见图2B，在第一芯片11和第二芯片12的周围形成一塑封层30，其中第一芯片11、第二芯片12和互联器件13嵌于塑封层30内；参见图2C，在塑封层30远离载体10的一侧表面进行减薄处理，以暴露出第一芯片11的第一凸点21和第二芯片12的第二凸点22；参见图2D，在塑封层30暴露出第一凸点21和第二凸点22的一侧表面形成第三凸点40；以及，参见图2E，移除载体10。
在一种可能的实施方式中，上述芯片组数大于1，方法还包括：移除载体10之后，对形成的封装件进行切割以获得多个单元封装体，其中每个单元封装体包含一组芯片。由此可以实现大规模封装。
本申请实施例提供的芯片互联方法和互联器件同样应用于芯片堆叠形式的半导体封装件中。例如，参见图4，可以提供载体10和多层芯片；参见图4，可以将第一层芯片包含的第一芯片11和第二芯片12正面朝上装设于载体10的表面；利用如图1所示的芯片互联方法将互联器件13附接至第一层芯片包含的第一芯片11和第二芯片12的部分上方表面，以使第一层芯片包含的第一芯片11通过互联器件13能够电性连接至第二芯片12；将第二层芯片包含的第三芯片14和第四芯片15正面朝上装设于第一芯片11、第二芯片12的上方表面，且分布在互联器件13的两侧，利用如图1所示的芯片互联方法将互联器件16附接至第二层芯片包含的第三芯片14和第四芯片15的部分上方表面，可以使第二层芯片包含的第三芯片14通过互联器件16能够电性连接至第四芯片15，并且同时连接至互联器件13。通过互联器件13、16，第一层芯片包含的第一芯片11、第二芯片12以及第二层芯片包含的第三芯片14、第四芯片15均能够实现电性连接。由此，利用互联器件可以实现多层芯片之间的电性连接。
虽然已经参考若干具体实施方式描述了本发明的精神和原理，但是应该理解，本发明并不限于所公开的具体实施方式，对各方面的划分也不意味着这些方面中的特征不能组合以进行受益，这种划分仅是为了表述的方便。本发明旨在涵盖所附权利要求的精神和范围内所包括的各种修改和等同布置。

Claims (15)

1.一种芯片互联方法，其特征在于，应用于芯片堆叠形式的半导体封装件，包括：
将第一层的第一芯片和第二芯片设置于载体表面，其中，所述第一芯片的上方表面形成有多个第一凸点，所述第二芯片的上方表面形成有多个第二凸点，所述第一凸点的接触面小于所述第二凸点；
将互联器件附接至所述第一芯片和所述第二芯片的部分上方表面，所述互联器件的一侧表面形成有用于接合至所述多个第一凸点的多个第一焊盘以及用于接合至所述多个第二凸点的多个第二焊盘，其中，将所述互联器件的多个所述第一焊盘对准接合至多个所述第一凸点，以使所述互联器件的多个所述第二焊盘自对准接合至所述第二芯片的多个所述第二凸点；其中，所述第一焊盘的接触面小于所述第二焊盘的接触面；
将第二层的第三芯片和第四芯片设置于所述第一芯片、所述第二芯片的上方表面，且分布在互联器件的两侧，另一互联器件附接至所述第三芯片和所述第四芯片的部分上方表面，并且连接至所述互联器件。
2.根据权利要求1所述的方法，其特征在于，所述第一芯片的多个所述第一凸点为多个高密度凸点，所述第二芯片的多个所述第二凸点为多个低密度凸点。
3.根据权利要求1所述的方法，其特征在于，在所述互联器件的多个所述第一焊盘和多个所述第二焊盘之间形成有扇出电路，以使每组芯片包含的所述第一芯片通过所述互联器件能够电性连接至所述第二芯片。
4.根据权利要求1-3中任一项所述的方法，其特征在于，所述互联器件形成为具有垂直互联通孔的互联器件。
5.根据权利要求1-3中任一项所述的方法，其特征在于，所述互联器件形成为无源器件或有源器件。
6.一种互联器件，其特征在于，应用于芯片堆叠形式的半导体封装件，其中，
所述互联器件的一侧表面形成有多个第一焊盘和多个第二焊盘，其中，所述多个第一焊盘用于接合至第一芯片的多个第一凸点，所述多个第二焊盘用于接合至第二芯片的多个第二凸点，所述第一凸点的接触面小于所述第二凸点，所述第一焊盘与所述第一凸点的接触面相同；
所述互联器件的所述多个第一焊盘和所述多个第二焊盘之间形成有扇出电路，用于实现所述多个第一焊盘和所述多个第二焊盘之间的电性连接；其中，所述第一焊盘的接触面小于所述第二焊盘的接触面；
第二层的第三芯片和第四芯片设置于所述第一芯片、所述第二芯片的上方表面，且分布在互联器件的两侧，另一互联器件附接至所述第三芯片和所述第四芯片的部分上方表面，并且连接至所述互联器件。
7.根据权利要求6所述的互联器件，其特征在于，所述互联器件形成为具有垂直互联通孔的互联器件。
8.根据权利要求6所述的互联器件，其特征在于，所述互联器件形成为无源器件或有源器件。
9.根据权利要求6所述的互联器件，其特征在于，所述互联器件采用半导体材料，包括以下中的一种或多种：硅(Si)、碳化硅(SiC)、砷化镓(GaAs)、氮化镓(GaN)。
10.根据权利要求6所述的互联器件，其特征在于，所述互联器件采用无机材料，包括以下中的一种或多种：玻璃、陶瓷。
11.根据权利要求6所述的互联器件，其特征在于，所述互联器件采用封装基板材料，包括以下中的一种或多种：印刷电路基板(PCB)、塑封基板(EMC)、柔性电路基板。
12.根据权利要求6所述的互联器件，其特征在于，所述互联器件采用金属基板材料，包括以下中的一种或多种：铜、铝。
13.根据权利要求6所述的互联器件，其特征在于，所述互联器件附带具有集成电路、微机电系统(MEMS)、光电元器件以及被动元器件(IPD)的功能。
14.一种形成封装件的方法，其特征在于，包括：
提供载体和多层芯片，其中第一层芯片至少包括第一芯片和第二芯片；
将第一层芯片包含的所述第一芯片和所述第二芯片正面朝上装设于所述载体的表面，其中第一芯片的上方表面具有第一凸点，第二芯片的上方表面具有第二凸点；
利用如权利要求1-5中任一项所述的方法将互联器件附接至第一层芯片包含的所述第一芯片和所述第二芯片的部分上方表面，以使第一层芯片包含的所述第一芯片通过所述互联器件能够电性连接至所述第二芯片；
将第二层的第三芯片和第四芯片设置于第一层芯片的上方表面，且分布在所述互联器件的两侧，另一互联器件附接至所述第三芯片和所述第四芯片的部分上方表面，并且连接至所述互联器件；
在所述第一层芯片和所述第二层芯片的周围形成一塑封层，其中所述第一层芯片、所述第二层芯片、所述互联器件和所述另一互联器件嵌于塑封层内；
在所述塑封层远离载体的一侧表面进行减薄处理，以暴露出顶层芯片的凸点；
在所述塑封层暴露出所述凸点的一侧表面形成第三凸点；以及，
移除所述载体。
15.根据权利要求14所述的形成封装件的 方法，其特征在于，每层芯片的芯片组数大于1，所述方法还包括：移除所述载体之后，对形成的所述封装件进行切割以获得多个单元封装体，其中每个所述单元封装体包含一组芯片。
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