JP2017517888A - 冗長電気コネクタを有する相互接続構造と、それに関連するシステムおよび方法 - Google Patents
冗長電気コネクタを有する相互接続構造と、それに関連するシステムおよび方法 Download PDFInfo
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- JP2017517888A JP2017517888A JP2016569053A JP2016569053A JP2017517888A JP 2017517888 A JP2017517888 A JP 2017517888A JP 2016569053 A JP2016569053 A JP 2016569053A JP 2016569053 A JP2016569053 A JP 2016569053A JP 2017517888 A JP2017517888 A JP 2017517888A
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- Prior art keywords
- conductive
- semiconductor die
- trace
- redundant electrical
- electrical connectors
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Classifications
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Abstract
Description
Claims (34)
- 第一の半導体ダイと、
第二の半導体ダイと、
前記第一の半導体ダイを前記第二の半導体ダイに結合する相互接続構造であって、前記相互接続構造は、前記第一の半導体ダイと前記第二の半導体ダイとの間にあり、前記相互接続構造は、
前記第一の半導体ダイに結合された第一の導電性膜と、
前記第二の半導体ダイに結合された第二の導電性膜と、
前記第一の導電性膜と前記第二の導電性膜との間に延び、前記第一の導電性膜を介して互いに電気的に結合された複数の冗長電気コネクタと、
を含む、相互接続構造と、
を含む、
半導体ダイアセンブリ。 - 前記冗長電気コネクタのうちの少なくとも一つは、前記第二の導電性膜から分離される、
請求項1に記載の半導体ダイアセンブリ。 - 前記冗長電気コネクタは、
前記第一の導電性膜に結合された導電性部材と、
前記導電性部材に結合されたはんだ材料と、
を各々含み、
少なくとも一つの前記冗長電気コネクタの前記はんだ材料は、前記第二の導電性膜と前記導電性部材を電気的に接続できない、
請求項1に記載の半導体ダイアセンブリ。 - 前記第一の半導体ダイは第一の基板と、前記第一の基板を通って延びる第一の基板貫通ビア(TSV)とを含み、前記第一のTSVは、前記第一の導電性膜に結合され、
前記第二の半導体ダイは、第二の基板と、前記第二の基板を通って延びる第二のTSVとを含み、前記第二のTSVは、前記第二の導電性膜に結合される、
請求項1に記載の半導体ダイアセンブリ。 - 前記第一の半導体ダイは、基板と前記基板を通って延びる基板貫通ビア(TSV)とを含み、前記TSVは、前記第一の導電性膜に結合され、
前記冗長電気コネクタの内の少なくとも一つは、前記TSVと、前記第二の導電性膜との間に延びる、
請求項1に記載の半導体ダイアセンブリ。 - 前記第一および第二の導電性膜の各々は、導電性トレースを含む、
請求項1に記載の半導体ダイアセンブリ。 - 前記第一の半導体ダイは論理ダイまたはメモリダイであり、
前記第二の半導体ダイは、論理ダイまたはメモリダイである、
請求項1に記載の半導体ダイアセンブリ。 - 第一の導電性トレースを有する第一の半導体ダイと、
第二の導電性トレースを有する第二の半導体ダイと、
前記第一の導電性トレースと、前記第二の導電性トレースとの間に延びる複数の冗長電気コネクタであって、前記冗長電気コネクタの各々は、
前記第一の導電性トレースに結合された導電性部材であって、端部を含む、導電性部材と、
前記導電性部材と前記第二の導電性トレースとの間の導電性接合材料であって、前記導電性部材の前記端部に接合される、導電性接合材料と、
を含む、冗長電気コネクタと、
を含む、
半導体ダイアセンブリ。 - 前記冗長電気コネクタのうちの少なくとも一つの前記導電性接合材料は、前記導電性部材の前記端部にのみ接合される、
請求項8に記載の半導体ダイアセンブリ。 - 前記冗長電気コネクタのうちの少なくとも別の一つは、前記第一の導電性トレースに電気的に結合される、
請求項9に記載の半導体ダイアセンブリ。 - 前記冗長電気コネクタのうちの全ては、前記第一の導電性トレースに結合される、
請求項8に記載の半導体ダイアセンブリ。 - 前記冗長電気コネクタのうちの全てよりは少ない冗長電気コネクタが、前記第一の導電性トレースに結合される、
請求項8に記載の半導体ダイアセンブリ。 - 前記冗長電気コネクタの各々は、前記導電性接合材料と前記第二の導電性トレースとの間にボンドパッドをさらに含む、
請求項8に記載の半導体ダイアセンブリ。 - 前記冗長電気コネクタのうちの少なくとも一つの前記導電性接合材料は、前記ボンドパッドに接合されていない、
請求項13に記載の半導体ダイアセンブリ。 - 前記導電性部材の各々は、前記第二の導電性トレースに向かって突出する導電性柱部を含む、
請求項8に記載の半導体ダイアセンブリ。 - 前記導電性部材の各々は、
前記第二の導電性トレースに結合されたレイズドボンドと、
前記第一の導電性トレースに結合され、前記レイズドボンドパッドに向かって突出する導電性柱部と、
を含む、
請求項8に記載の半導体ダイアセンブリ。 - 前記導電性接合材料は、金属はんだを含む、
請求項8に記載の半導体ダイアセンブリ。 - 前記第一の半導体ダイは、基板と、前記基板を通って延びる基板貫通ビア(TSV)とを含み、前記TSVは、前記第一の導電性トレースに結合される、
請求項8に記載の半導体ダイアセンブリ。 - 導電性トレースを有する第一の半導体ダイと、
第二の半導体ダイと、
前記導電性トレースに結合され、前記第二の半導体ダイに向かって垂直方向に延びる複数の導電性部材であって、前記導電性部材は、前記導電性トレースを介して互いに電気的に結合され、前記導電性部材の少なくとも一つは、前記第二の半導体ダイに結合される、複数の導電性部材と、
を含む、
半導体ダイアセンブリ。 - 前記導電性部材は、互いから横方向に離隔され、前記第一の半導体ダイと前記第二の半導体ダイとの間で熱を伝達するように構成される、
請求項19に記載の半導体ダイアセンブリ。 - 前記第二の半導体ダイを支持するパッケージ基板と、
筐体内に前記第一および第二の半導体ダイを少なくとも部分的に包囲する熱伝導性ケーシングと、
をさらに含む、
請求項20に記載の半導体ダイアセンブリ。 - 前記第二の半導体ダイは、第二の導電性トレースを含み、
前記導電性部材の一つ以上は、金属はんだで前記第二の導電性トレースに結合される、
請求項19に記載の半導体ダイアセンブリ。 - 半導体ダイアセンブリを形成する方法であって、
第一の半導体ダイ上に第一の導電性膜を形成することと、
第二の半導体ダイ上に第二の導電性膜を形成することと、
前記第一の導電性膜上に複数の冗長電気コネクタを形成することと、
前記第二の導電性膜に前記冗長電気コネクタを結合することと、
を含む、
方法。 - 前記冗長電気コネクタを前記第二の導電性膜に結合することは、前記冗長電気コネクタの各々と、前記第二の導電性膜との間にはんだ接合を形成することを含む、
請求項23に記載の方法。 - 前記冗長電気コネクタを前記第二の導電性膜に結合することは、前記冗長電気コネクタの各々と、前記第二の導電性膜上の対応するボンドパッドとの間にはんだ接合を形成することを含む、
請求項23に記載の方法。 - 前記冗長電気コネクタのうちの少なくとも一つの前記はんだ接合は、前記冗長電気コネクタのうちの少なくとも一つを、前記ボンドパッドのうちの対応する一つと、電気的に接続できない、
請求項25に記載の方法。 - 前記第一の半導体ダイの基板を通って延びる基板貫通ビア(TSV)を形成することをさらに含み、前記第一の導電性膜を形成することは、前記第一の導電性膜に前記TSVを結合することをさらに含む、
請求項25に記載の方法。 - 前記第一の導電性膜を形成することは、第一の導電性トレースを形成することをさらに含み、
前記第二の導電性膜を形成することは、第二の導電性トレースを形成することをさらに含む、
請求項25に記載の方法。 - 半導体ダイアセンブリを形成する方法であって、
第一の半導体ダイ上に第一の導電性トレースを形成することと、
前記第一の導電性トレース上に、前記第一の半導体ダイから突出する複数の導電性部材を形成することと、
前記導電性部材の各々に接する導電性接合材料を配置することと、
第二の半導体ダイの第二の導電性トレースに、前記複数の導電性部材の個々の一つを結合するために、前記導電性接合材料をリフローすることと、
を含む、
方法。 - 前記導電性接合材料を配置することは、前記導電性部材の各々に接する金属はんだを配置することを含む、
請求項29に記載の方法。 - 前記導電性接合材料をリフローした後、少なくとも前記導電性部材に接する前記導電性接合材料は、前記第二の導電性トレースとのはんだ接合部を形成できない、
請求項29に記載の方法。 - 前記導電性接合材料をリフローすることは、前記第二の導電性トレース上のボンドパッドと、前記導電性部材の対応する一つとの間の前記導電性接合材料をリフローすることを含む、
請求項29に記載の方法。 - 前記導電性部材を形成することは、前記第一の導電性トレース上に複数の導電性柱部を形成することを含む、
請求項29に記載の方法。 - 前記第一の半導体ダイは、基板と、前記基板を通って延びる基板貫通ビア(TSV)とを含み、
前記第一のトレースは、前記TSVから横方向に延び、
前記導電性部材を形成することは、前記TSVと前記第二のトレースとの間に一つ以上の前記導電性部材を形成することを含む、
請求項29に記載の方法。
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CN106489201B (zh) | 2020-05-26 |
US9356009B2 (en) | 2016-05-31 |
CN111710660A (zh) | 2020-09-25 |
EP3149770A1 (en) | 2017-04-05 |
EP3149770A4 (en) | 2018-01-24 |
US20160268235A1 (en) | 2016-09-15 |
US20180026015A1 (en) | 2018-01-25 |
US11233036B2 (en) | 2022-01-25 |
KR20170008303A (ko) | 2017-01-23 |
EP3149770B1 (en) | 2022-04-20 |
US9818728B2 (en) | 2017-11-14 |
US20210202446A1 (en) | 2021-07-01 |
US20190157246A1 (en) | 2019-05-23 |
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US11626388B2 (en) | 2023-04-11 |
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