TWI570866B - 具有備份電連接器之互連結構及相關系統與方法 - Google Patents

具有備份電連接器之互連結構及相關系統與方法 Download PDF

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TWI570866B
TWI570866B TW104117024A TW104117024A TWI570866B TW I570866 B TWI570866 B TW I570866B TW 104117024 A TW104117024 A TW 104117024A TW 104117024 A TW104117024 A TW 104117024A TW I570866 B TWI570866 B TW I570866B
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conductive
semiconductor die
trace
electrical connectors
conductive film
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TW104117024A
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TW201606972A (zh
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安尼庫瑪 查杜魯
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美光科技公司
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Description

具有備份電連接器之互連結構及相關系統與方法
所揭示之實施例係關於形成於一半導體晶粒總成中之堆疊半導體晶粒之間之互連結構。在若干實施例中，本發明係關於一種具有備份導電連接器之互連結構。
封裝半導體晶粒(其包含記憶體晶片、微處理器晶片及成像器晶片)通常包含安裝於一基板上且包圍於一塑膠保護罩中之一半導體晶粒。該晶粒包含功能特徵(諸如記憶體胞、處理器電路及成像器裝置)及電連接至該等功能特徵之接合墊。該等接合墊可電連接至該保護罩外之端子以允許該晶粒連接至外部電路。
在一些晶粒封裝內，半導體晶粒可堆疊於彼此上且藉由放置於相鄰晶粒之間之互連件而彼此電連接。可使用金屬焊料來將互連件連接至相鄰晶粒之接合墊。然而，金屬焊料接合之一挑戰在於：金屬焊料無法始終適當地接合至互連件及/或接合墊。因此，互連件可為開路的，其可引起晶粒封裝無法適當地運行。此接著可降低製造期間之製程良率。
100‧‧‧半導體晶粒總成
102‧‧‧半導體晶粒
102a‧‧‧第一半導體晶粒
102b‧‧‧第二半導體晶粒
106‧‧‧周邊部分
109a‧‧‧第一側
109b‧‧‧第二側
110‧‧‧導熱罩殼
112‧‧‧蓋部分
113‧‧‧壁部分
114a‧‧‧第一接合材料
114b‧‧‧第二接合材料
116‧‧‧介電側填滿材料
120‧‧‧中介層
125‧‧‧封裝基板
127‧‧‧封裝接觸件
128‧‧‧電連接器
130‧‧‧互連結構
134‧‧‧備份電連接器
138‧‧‧備份電連接器
140a‧‧‧第一導電跡線
140b‧‧‧第二導電跡線
142‧‧‧基板通孔(TSV)
204a‧‧‧第一半導體基板
204b‧‧‧第二半導體基板
205‧‧‧半導體裝置
230‧‧‧互連結構
232‧‧‧柱
233‧‧‧接合墊
234‧‧‧備份電連接器
235‧‧‧導電接合材料
237‧‧‧端部分
240a‧‧‧第一跡線
240b‧‧‧第二跡線
292‧‧‧互連件
293‧‧‧接合墊
295‧‧‧焊料接合材料
296‧‧‧側壁
330‧‧‧互連結構
334‧‧‧備份電連接器
340‧‧‧導電跡線
404a‧‧‧第一基板
404b‧‧‧第二基板
405‧‧‧半導體裝置
407‧‧‧基板接觸件
408‧‧‧開口
432‧‧‧柱
433‧‧‧接合墊
435‧‧‧接合材料
437‧‧‧端部分
440a‧‧‧第一導電跡線
440b‧‧‧第二導電跡線
442‧‧‧基板通孔(TSV)
450a‧‧‧第一介電材料
450b‧‧‧第二介電材料
452‧‧‧開口
453‧‧‧開口
460‧‧‧遮罩
461‧‧‧遮罩開口
462‧‧‧側壁
463‧‧‧保護材料/保護膜
465‧‧‧遮罩
466‧‧‧遮罩開口
467‧‧‧側壁
470‧‧‧導電材料
472‧‧‧晶種材料
474‧‧‧障壁材料
475‧‧‧界面材料
476‧‧‧導電材料
477‧‧‧晶種材料
478‧‧‧導電材料
484‧‧‧障壁材料
485‧‧‧界面材料
500‧‧‧半導體晶粒總成
590‧‧‧系統
592‧‧‧電源
594‧‧‧驅動器
596‧‧‧處理器
598‧‧‧子系統/組件
d1‧‧‧直徑
F1‧‧‧第一失效模式
F2‧‧‧第二失效模式
F3‧‧‧第三失效模式
F4‧‧‧第四失效模式
s1‧‧‧間隔距離
圖1係根據本發明之一實施例而組態之一半導體晶粒總成之一橫 截面圖。
圖2A係根據本發明之一實施例而組態之包含一互連結構之一半導體裝置之一放大橫截面圖。
圖2B係繪示可在製造期間發生之焊料接合之某些失效模式的一橫截面圖。
圖3係展示根據本發明之另一實施例而組態之互連結構方一俯視平面圖。
圖4A至圖4H係繪示根據本發明之選定實施例之用於製造互連結構之一方法之各種階段中之一半導體裝置的橫截面圖。
圖5係根據本發明之實施例而組態之包含一半導體晶粒總成之一系統之一示意圖。
下文描述具有含備份電連接器之互連結構之堆疊半導體晶粒總成及相關系統與方法之若干實施例之特定細節。術語「半導體裝置」及「半導體晶粒」一般係指包含半導體材料之一固態裝置，諸如一邏輯裝置、記憶體裝置或其他半導體電路、組件等等。此外，術語「半導體裝置」及「半導體晶粒」可係指一成品裝置或變為一成品裝置之前之各種處理階段中之一總成或其他結構。術語「基板」可係指一晶圓級基板或一單粒化晶粒級基板，其取決於其中使用該術語之內文。熟習相關技術者將認識到，可在晶圓級或晶粒級處執行本文所描述之方法之適合步驟。此外，若內文無另外說明，則可使用習知半導體製造技術來形成本文所揭示之結構。可(例如)使用化學氣相沈積、物理氣相沈積、原子層沈積、旋轉塗佈及/或其他適合技術來沈積材料。類似地，可(例如)使用電漿蝕刻、濕式蝕刻、化學機械平坦化或其他適合技術來移除材料。熟習相關技術者亦應瞭解，本發明可具有額外實施例，且可在無下文參考圖1至圖5所描述之實施例之細節之若干者 之情況下實踐本發明。
如本文所使用，術語「垂直」、「橫向」、「上」及「下」可係指半導體晶粒總成中之特徵鑑於圖中所展示之定向之相對方向或位置。例如，「上」或「最上」可係指一特徵定位成比另一特徵更靠近於一頁之頂部。然而，此等術語應被廣泛地被解釋為包含具有其他定向之半導體裝置。
圖1係根據本發明之一實施例而組態之一半導體晶粒總成100(「總成100」)之一橫截面圖。總成100包含由一第二半導體晶粒102b承載之第一半導體晶粒102a之一堆疊(統稱為「半導體晶粒102」)。接著，第二半導體晶粒102b由一中介層120承載。中介層120可包含(例如)一半導體晶粒、一介電間隔件及/或另一適合基板，其具有連接於中介層120與一封裝基板125之間之電連接器(圖中未展示)，諸如通孔、金屬跡線等等。封裝基板125可包含(例如)一中介層、一印刷電路板、另一邏輯晶粒或另一適合基板，其連接至將總成100電耦合至外部電路(圖中未展示)之封裝接觸件127(例如接合墊)及電連接器128(例如焊料球)。在一些實施例中，封裝基板125及/或中介層120可經不同組態。例如，在一些實施例中，可省略中介層120且可將第二半導體晶粒102b直接連接至封裝基板125。
總成100可進一步包含一導熱罩殼110(「罩殼110」)。罩殼110可包含一蓋部分112及附接至蓋部分112或與蓋部分112一體地形成之一壁部分113。蓋部分112可藉由一第一接合材料114a(例如一黏著劑)而附接至最頂部之第一半導體晶粒102a。壁部分113可遠離蓋部分112垂直延伸且藉由一第二接合材料114b(例如一黏著劑)而附接至第一半導體晶粒102a之一周邊部分106(熟習技術者稱為一「門廊」或「座架」)。除提供一保護罩之外，罩殼110可充當一散熱器以吸收熱能且使熱能自半導體晶粒102耗散。相應地，罩殼110可由一導熱材料(諸 如鎳(Ni)、銅(Cu)、鋁(Al)、具有高導熱性之陶瓷材料(例如氮化鋁)、及/或其他適合導熱材料)製成。
在一些實施例中，第一接合材料114a及/或第二接合材料114b可由此項技術中稱為「熱接合材料」或「TIM」(其經設計以增加表面接面(例如，在一晶粒表面與一散熱器之間)處之接觸熱導性)之材料製成。TIM可包含摻雜有導電材料(例如碳奈米管、焊接材料、類鑽石碳(DLC)等等)及相變材料之聚矽氧基脂、凝膠或黏著劑。在其他實施例中，第一接合材料114a及/或第二接合材料114b可包含其他適合材料，諸如金屬(例如銅)及/或其他適合導熱材料。
第一及/或第二半導體晶粒102之部分或全部可至少部分囊封於一介電側填滿材料116中。側填滿材料116可沈積或依其他方式形成於該等晶粒之部分或全部周圍及/或該等晶粒之部分或全部之間以增強與一晶粒之一機械連接及/或提供導電特徵及/或結構(例如互連件)之間之電隔離。側填滿材料116可為一非導電環氧膏、一毛細管側填滿材料、一非導電膜、一模製側填滿材料，及/或包含其他適合電絕緣材料。在若干實施例中，可基於側填滿材料116之導熱性而選擇側填滿材料116以增強通過總成100之晶粒之熱消散。在一些實施例中，可使用側填滿材料116來代替第一接合材料114a及/或第二接合材料114b以將罩殼110附接至最頂部之第一半導體晶粒102a。
半導體晶粒102可各由一半導體基板(諸如矽、絕緣體上矽、化合物半導體(例如氮化鎵)或其他適合基板)形成。該半導體基板可切割成或單粒化成具有各種積體電路組件或功能特徵之任何者(諸如動態隨機存取記憶體(DRAM)、靜態隨機存取記憶體(SRAM)、快閃記憶體或其他形式之積體電路裝置，其包含記憶體、處理電路、成像組件及/或其他半導體裝置)之半導體晶粒。在選定實施例中，總成100可組態為一混合記憶體立方體(HMC)，其中第一半導體晶粒102a提供資料儲 存器(例如DRAM晶粒)且第二半導體晶粒102b提供HMC內之記憶體控制(例如DRAM控制)。在一些實施例中，總成100可除包含半導體晶粒102之一或多者之外，亦包含其他半導體晶粒，及/或包含其他半導體晶粒來代替半導體晶粒102之一或多者。例如，此等半導體晶粒可包含除資料儲存器及/或記憶體控制組件之外之積體電路組件。此外，儘管總成100包含堆疊於中介層120上之9個晶粒，但在其他實施例中，總成100可包含9個以下晶粒(例如6個晶粒)或9個以上晶粒(例如12個晶粒、14個晶粒、16個晶粒、32個晶粒等等)。例如，在一實施例中，總成100可包含堆疊於2個邏輯晶粒上之4個記憶體晶粒。此外，在各種實施例中，半導體晶粒102可具有不同尺寸。例如，在一些實施例中，第二半導體晶粒102b可具有相同於第一半導體晶粒102a之至少一者之佔據面積。
如圖1中進一步所展示，總成100進一步包含：複數個第一導電跡線140a(「第一跡線140a」)，其等位於半導體晶粒102之一第一側109a(例如前側)上；複數個第二導電跡線140b(「第二跡線140b」)，其等位於半導體晶粒102之一第二側109b(例如一後側)上；及複數個互連結構130，其等使個別第一跡線140a與個別第二跡線140b相互耦合。第一跡線140a及第二跡線140b之各者可包含(例如)橫跨半導體晶粒102之一側而橫向延伸之一導電線、一導電板或其他導電結構。在所繪示之實施例中，第一跡線140a及第二跡線140b耦合至對應基板通孔(TSV)142。TVS經組態以使半導體晶粒102之相對側處之第一跡線140a及第二跡線140b相互耦合。如圖中所展示，TSV 142可朝向半導體晶粒102之中心安置，且第一跡線140a及第二跡線140b可自TSV 142向外展開且朝向互連結構130。然而，在其他實施例中，TSV 142、第一跡線140a及第二跡線140b、及/或互連結構130可經不同配置。
互連結構130可各包含耦合於相鄰半導體晶粒102之個別第一跡 線140a與個別第二跡線140b之間之複數個備份電連接器134(「備份連接器134」)。因而，各對之第一跡線140a及第二跡線140b藉由複數個備份連接器134而電及熱耦合在一起。在此實施例之一態樣中，備份連接器134可改良製造期間之製程良率。例如，如下文更詳細所描述，個別結構130不易於相對於習知互連件或其他電連接器而開路，此係因為存在沿跡線140a及140b彼此隔開之複數個備份連接器。在此實施例之另一態樣中，備份連接器134可增強通過半導體晶粒102之堆疊且朝向罩殼110之蓋部分112之熱傳導。特定言之，備份連接器134可提供相鄰半導體晶粒102之間之多個傳熱路徑。在若干實施例中，備份連接器134可沿個別跡線140a及140b彼此隔開以橫跨半導體晶粒102而橫向散發熱。在額外或替代實施例中，額外備份電連接器138(以虛線展示)可在半導體晶粒102之內部部分(例如，在TVS 142之間)與外部部分(例如，朝向晶粒102之邊緣)之間延伸以進一步散發熱。
圖2A係根據本發明之一實施例而組態之具有一互連結構230之一半導體裝置205之一放大圖。如圖中所展示，互連結構230包含在一第一半導體基板204a(例如一半導體晶圓或晶粒)與一第二半導體基板204b(例如一半導體晶圓或晶粒)之間延伸之複數個備份電連接器234(「備份連接器234」)。備份連接器234之各者包含耦合至第一基板204a之一第一導電膜或第一跡線240a之一導電構件或柱232。備份連接器234亦包含耦合至第二基板204b上之一第二導電膜或第二跡線240b之一第二導電構件或接合墊233(例如一凸起接合墊)。一導電接合材料235可形成將接合墊233耦合至一對應柱232之一端部分237之一導電接頭。導電接合材料235可包含(例如)焊料(例如金屬焊料)、一導電環氧樹脂或一導電膏。
一般而言，焊料接合材料之一挑戰在於：其無法將一互連件適當地接合至一接合墊。例如，圖2B展示一焊料接合材料295之若干失 效模式。一第一失效模式F1發生於一互連件292具有小於相鄰互連件(圖中未展示)之高度的一高度時。在此失效模式中，互連件292與其對應接合墊293之間之較大間隙阻止接合材料295接觸接合墊293。一第二失效模式F2發生於互連件292及/或接合墊293上之剩餘污染物(圖中未展示)阻止接合材料295濕潤至互連件292及/或接合墊293時。一第三失效模式F3可歸因於發生於回焊或其他加熱程序期間之焊料芯吸作用。特定言之，焊料芯吸作用發生於表面張力吸引(經加熱)接合材料295朝向互連件292之側壁296且遠離接合墊293時。一第四失效模式F4涉及互連件292與接合墊293之間之接合材料295之開裂或破裂。開裂可(例如)發生於一焊接材料消耗一互連件之某些材料(例如鈀(Pd))(即，與之反應)且引起接合材料295變得易碎且易於破裂時。
然而，根據本發明之若干實施例而組態之互連結構可解決習知互連件及相關結構之此等及其他限制。再次參考圖2A，備份連接器234經組態使得即使某些連接器234失效(例如，藉由失效模式F1至F4之一者)，但只要其他備份連接器234之至少一者保持連接至第一跡線240a及第二跡線240b，則互連結構230不會失效。在圖2A所展示之實施例中，例如，高達4個備份連接器234可失效且不使互連結構230開路。在其他實施例中，互連結構230可具有不同數目個備份連接器，諸如5個以上備份連接器(例如6個、8個、10個或10個以上連接器)或5個以下備份連接器(例如2個、3個或4個連接器)。在若干實施例中，備份連接器之數目可經選擇以改良製造期間之一預期製程良率。例如，在一些例項中，具有3個備份連接器之一互連結構可使製程良率提高0.5%，而4個備份連接器僅可使良率額外提高0.05%。在此一方案中，3連接器組態可為比4連接器組態更可接受之一設計，此係因為製程良率之預期差值可忽略不計。
各種實施例之互連結構之另一優點在於：備份電連接器可減小 通過一導電接頭(例如，通過備份互連件234之接合材料235)之電流密度。例如，具有10個備份連接器之一互連結構可使通過其導電接頭之各者之電流密度減小約10倍。一相關優點在於：較低電流密度可減少電遷移。例如，一較低電流密度可減少通過錫/銀基(SnAg)焊料接頭之電遷移，錫/銀基(SnAg)焊料接頭通常比其他互連材料(例如銅)更易受電遷移影響。在一些實施例中，備份電連接器之數目可經選擇以達成與橫跨互連結構之電容之一潛在增加平衡之電遷移之某一減少。
各種實施例之互連結構之一進一步優點在於：備份電連接器可緊密堆積。例如，圖3係展示根據本發明之另一實施例而組態之對應互連結構330之緊密堆積備份電連接器334(「備份連接器334」)的一俯視平面圖。如圖中所展示，備份連接器334各形成於一對應互連結構330之一導電跡線340上。備份連接器334各具有一直徑d1且彼此隔開達一間隔距離s1。在一實施例中，直徑d1之尺寸可近似相同於間隔距離s1。在另一實施例中，間隔距離s1可小於直徑d1。例如，間隔距離s1可小於d1之75%，小於d1之50%，或小於d1之25%。相比而言，習知互連件無法依此一方式緊密堆積，此係因為存在金屬焊料可橋接互連件且引起電短路之一風險。然而，因為備份連接器334彼此電耦合(即，經由導電跡線340)，所以電短路不會造成此一風險。
圖4A至圖4H係繪示根據本發明之選定實施例之用於製造互連結構之一方法之各種階段中之一半導體裝置405之一部分橫截面圖。首先參考圖4A，半導體裝置405包含一第一基板404a(例如一矽晶圓或晶粒)及形成於第一基板404a上之一第一介電材料450a(例如氧化矽)。第一介電材料450a經圖案化以暴露一基板接觸件407(例如一銅接合墊)。第一介電材料450a亦可經圖案化以暴露第一基板404a之其他基板接觸件(圖中未展示)，諸如連接至第一基板404a之一積體電路(IC)裝置(例如記憶體；圖中未展示)之基板接觸件。半導體裝置405進 一步包含形成於第一介電材料450a及基板接觸件407上之一圖案化第一導電膜或第一導電跡線440a(例如一銅或銅合金膜)。
圖4B展示在第一介電材料450a中形成一遮罩460(例如一光阻遮罩、硬遮罩等等)及開口452之後之半導體裝置405。可藉由透過對應遮罩開口461移除(例如，蝕刻)第一介電材料450a之部分而形成開口452。如圖4B中所展示，開口452可暴露下伏第一導電跡線440a之部分。
圖4C展示在第一導電跡線440a上形成導電構件或柱432之後之半導體裝置405。在若干實施例中，可藉由將一晶種材料472(例如銅)沈積於遮罩開口461(圖4B)之側壁462上且接著將一導電材料470(例如銅)電鍍至晶種材料472上而形成柱432。在所繪示之實施例中，亦可將一障壁材料474(例如鎳)及一界面材料475(例如鈀)依序電鍍至導電材料470上。在其他實施例中，可使用其他沈積技術(諸如濺鍍)來代替電鍍。
圖4D展示在第一基板404a中形成一開口408且在柱432上形成一保護材料463之後之半導體裝置405。如圖中所展示，開口408延伸穿過第一基板404a且使基板接觸件407之一部分朝向開口408之底部暴露。在若干實施例中，可藉由首先使第一基板404a變薄(例如，經由蝕刻、背面研磨等等)且接著移除基板材料(例如，經由一蝕刻)而形成開口408。在所繪示之實施例中，保護材料或保護膜463(例如聚化膜)可在製造期間保護柱432。
圖4E展示形成一TSV 442、一第二介電材料450b、及一第二導電膜或第二導電跡線440b之後之半導體裝置405。可藉由使用一導電材料476(諸如銅或銅合金)填充第一基板404a中之開口408(圖4D)而形成TSV 442。在若干實施例中，可依類似於第一導電跡線440a及第一介電材料450a之方式的一方式形成第二導電跡線440b及第二介電材料450b。
圖4F展示在第二介電材料450b中形成一遮罩465及開口453之後之半導體裝置405。可藉由透過對應遮罩開口466移除(例如，蝕刻)第二介電材料450b之部分而形成開口453。如圖4F中所展示，第二介電材料450b中之開口453可暴露下伏第二導電跡線440b之部分。
圖4G展示在第二導電跡線440b上形成導電構件或接合墊433之後之半導體裝置405。類似於柱432，可藉由將一晶種材料477(例如銅)沈積至遮罩開口466(圖4F)之側壁467及/或第二導電跡線440b上且接著將一導電材料478(例如銅)電鍍至晶種材料477上而形成接合墊433。在一些實施例中，接合墊433可包含依序電鍍至導電材料478上之一障壁材料484(例如鎳)及一界面材料485(例如鈀)。
圖4H展示移除遮罩465及保護膜463(圖4G)且在柱432之端部分437上形成一接合材料435(例如金屬焊料)之後之半導體裝置405。在一實施例中，接合材料435可為一電鍍材料。在另一實施例中，接合材料435可呈一焊料球之形式。無論何種情況，可加熱(例如，回焊)接合材料435且使接合材料435與一第二基板404b之對應接合墊433接觸。在回焊之後，可允許接合材料435冷卻且固化成將柱432附接至接合墊433之導電接頭。在若干實施例中，接合墊433之結構及功能可大體上類似於第一基板404a之接合墊433(圖4G)之結構及功能。
上文參考圖1至圖4H所描述之互連結構及/或半導體晶粒總成之任何者可併入至諸多更大及/或更複雜系統(其之一代表實例係圖5中示意性地所展示之系統590)之任何者中。系統590可包含一半導體晶粒總成500、一電源592、一驅動器594、一處理器596及/或其他子系統或組件598。半導體晶粒總成500可包含大體上類似於上文所描述之堆疊半導體晶粒總成之特徵的特徵，且可因此包含增強熱消散之各種特徵。所得系統590可執行各種功能之任何者，諸如記憶體儲存、資料處理及/或其他適合功能。相應地，代表系統590可包含(但不限於) 手持式裝置(例如行動電話、平板電腦、數位閱讀器及數位音訊播放器)、電腦及電器。系統590之組件可收容於一單一單元中或分佈於多個互連單元上(例如，透過一通信網路)。系統590之該等組件亦可包含遠端裝置及各種電腦可讀媒體之任何者。
應自上述內容瞭解，本文已為繪示之目的而描述本發明之特定實施例，但可在不背離本發明之情況下進行各種修改。例如，儘管相對於HMC而描述半導體晶粒總成之實施例之若干者，但在其他實施例中，半導體晶粒總成可組態為其他記憶體裝置或其他類型之堆疊晶粒總成。另外，儘管已在所繪示之實施例中將某些特徵或組件展示為具有某些配置或組態，但其他配置及組態係可行的。例如，儘管在所繪示之實施例中於前端金屬化之後(即，在形成基板接觸件407之後)形成TSV 442(圖4E)，但在其他實施例中，可在前端金屬化之前或與前端金屬化同時地形成TSV 442。此外，儘管在所繪示之實施例中將柱接合至凸起墊，但在其他實施例中，可將柱接合至其他結構或直接接合至一導電跡線。再者，儘管已在與新技術之某些實施例之內文中描述與該等實施例相關之優點，但其他實施例亦可展現此等優點且未必需要所有實施例展現落於本發明之範疇內之此等優點。相應地，本發明及相關技術可涵蓋本文未清楚地展示或描述之其他實施例。
100‧‧‧半導體晶粒總成
102a‧‧‧第一半導體晶粒
102b‧‧‧第二半導體晶粒
106‧‧‧周邊部分
109a‧‧‧第一側
109b‧‧‧第二側
110‧‧‧導熱罩殼
112‧‧‧蓋部分
113‧‧‧壁部分
114a‧‧‧第一接合材料
114b‧‧‧第二接合材料
116‧‧‧介電側填滿材料
120‧‧‧中介層
125‧‧‧封裝基板
127‧‧‧封裝接觸件
128‧‧‧電連接器
130‧‧‧互連結構
134‧‧‧備份電連接器
138‧‧‧備份電連接器
140a‧‧‧第一導電跡線
140b‧‧‧第二導電跡線
142‧‧‧基板通孔(TSV)

Claims (32)

  1. 一種半導體晶粒總成，其包括：一第一半導體晶粒；一第二半導體晶粒；及一互連結構，其將該第一半導體晶粒耦合至該第二半導體晶粒，其中該互連結構介於該第一半導體晶粒與該第二半導體晶粒之間，且其中該互連結構包含一第一導電膜，其耦合至該第一半導體晶粒，一第二導電膜，其耦合至該第二半導體晶粒，及複數個備份電連接器，其等在該第一導電膜與該第二導電膜之間延伸且附接至該第一導電膜及該第二導電膜，其中所有該等備份電連接器經由該第一導電膜而彼此電耦合。
  2. 如請求項1之半導體晶粒總成，其中該互連結構進一步包括另一備份電連接器，該另一備份電連接器附接至該第一導電膜且與該第二導電膜分離。
  3. 如請求項1之半導體晶粒總成，其中該等備份電連接器各包含：一導電構件，其耦合至該第一導電膜；及一焊接材料，其耦合至該導電構件，其中該互連結構進一步包括另一備份電連接器，該另一備份電連接器具有耦合至該第一導電膜之一導電構件及一焊接材料，該焊接材料無法將該另一備份電連接器之該導電構件與該第二導電膜電連接。
  4. 如請求項1之半導體晶粒總成，其中：該第一半導體晶粒包含一第一基板及延伸穿過該第一基板之一第一基板通孔(TSV)，其中該第一TSV耦合至該第一導電膜； 且該第二半導體晶粒包含一第二基板及延伸穿過該第二基板之一第二TSV，其中該第二TSV耦合至該第二導電膜。
  5. 如請求項1之半導體晶粒總成，其中：該第一半導體晶粒包含一基板及延伸穿過該基板之一基板通孔(TSV)，其中該TSV耦合至該第一導電膜；且該等備份電連接器之至少一者在該TSV與該第二導電膜之間延伸。
  6. 如請求項1之半導體晶粒總成，其中該第一導電膜及該第二導電膜之各者包含一導電跡線。
  7. 如請求項1之半導體晶粒總成，其中：該第一半導體晶粒係一邏輯晶粒或一記憶體晶粒；且該第二半導體晶粒係一邏輯晶粒或一記憶體晶粒。
  8. 一種半導體晶粒總成，其包括：一第一半導體晶粒，其具有一第一導電跡線；一第二半導體晶粒，其具有一第二導電跡線；及複數個備份電連接器，其等在該第一導電跡線與該第二導電跡線之間延伸，其中該等備份電連接器之各者包含一導電構件，其耦合至該第一導電跡線，其中該導電構件包含一端部分，及一導電接合材料，其介於該導電構件與該第二導電跡線之間，其中該導電接合材料接合至該導電構件之該端部分，其中所有該等備份電連接器附接至該第一導電跡線。
  9. 如請求項8之半導體晶粒總成，其中該等備份電連接器之至少一者之該導電接合材料僅接合至該導電構件之該端部分。
  10. 如請求項8之半導體晶粒總成，其中所有該等備份電連接器耦合 至該第二導電跡線。
  11. 如請求項8之半導體晶粒總成，其中並非所有該等備份電連接器耦合至該第二導電跡線。
  12. 如請求項8之半導體晶粒總成，其中該等備份電連接器之各者進一步包含介於該導電接合材料與該第二導電跡線之間之一接合墊。
  13. 如請求項12之半導體晶粒總成，其中該等備份電連接器之至少一者之該導電接合材料未接合至該接合墊。
  14. 如請求項8之半導體晶粒總成，其中該等導電構件之各者包含朝向該第二導電跡線突出之一導電柱。
  15. 如請求項8之半導體晶粒總成，其中該等導電構件之各者包含：一凸起接合墊，其耦合至該第二導電跡線；及一導電柱，其耦合至該第一導電跡線且朝向該凸起接合墊突出。
  16. 如請求項8之半導體晶粒總成，其中該導電接合材料包含金屬焊料。
  17. 如請求項8之半導體晶粒總成，其中該第一半導體晶粒包含一基板及延伸穿過該基板之一基板通孔(TSV)，其中該TSV耦合至該第一導電跡線。
  18. 一種半導體晶粒總成，其包括：一第一半導體晶粒，其具有一第一導電跡線；一第二半導體晶粒，其具有一第二導電跡線；及複數個備份導電構件，其等耦合至該第一導電跡線且朝向該第二半導體晶粒垂直延伸，其中該等備份導電構件經由該第一導電跡線而彼此電耦合，且其中所有該等導電構件耦合至該第二半導體晶粒之該第二導電跡線。
  19. 如請求項18之半導體晶粒總成，其中該等備份導電構件彼此橫向隔開且經組態以在該第一半導體晶粒與該第二半導體晶粒之間傳熱。
  20. 如請求項19之半導體晶粒總成，其進一步包括：一封裝基板，其承載該第二半導體晶粒；及一導熱罩殼，其將該第一半導體晶粒及該第二半導體晶粒至少部分地圍封於一封閉體內。
  21. 一種形成一半導體晶粒總成之方法，該方法包括：在一第一半導體晶粒上形成一第一導電膜；在一第二半導體晶粒上形成一第二導電膜；在該第一導電膜上形成複數個備份電連接器，其中所有該等備份電連接器附接至該第一導電膜；及將該等備份電連接器耦合至該第二導電膜。
  22. 如請求項21之方法，其中將該等備份電連接器耦合至該第二導電膜包含：在該等備份電連接器之各者與該第二導電膜之間形成一焊料接合。
  23. 如請求項21之方法，其中將該等備份電連接器耦合至該第二導電膜包含：在該等備份電連接器之各者與該第二導電膜上之一對應接合墊之間形成一焊料接合。
  24. 如請求項23之方法，其中該等備份電連接器之至少一者之該焊料接合無法將該等備份電連接器之至少一者與該等接合墊之一對應者電連接。
  25. 如請求項23之方法，其進一步包括：形成延伸穿過該第一半導體晶粒之一基板之一基板通孔(TSV)，其中形成該第一導電膜進一步包含將該TSV耦合至該第一導電膜。
  26. 如請求項23之方法，其中： 形成該第一導電膜進一步包含：形成一第一導電跡線；且形成該第二導電膜進一步包含：形成一第二導電跡線。
  27. 一種形成一半導體晶粒總成之方法，其包括：在一第一半導體晶粒上形成一第一導電跡線；在該第一導電跡線上形成突出遠離該第一半導體晶粒之複數個導電構件，其中所有該等導電構件附接至該第一導電跡線；在該等導電構件之各者上安置一導電接合材料；及回焊該導電接合材料以將該複數個導電構件之個別者耦合至一第二半導體晶粒之一第二導電跡線。
  28. 如請求項27之方法，其中安置該導電接合材料包含：在該等導電構件之各者上安置金屬焊料。
  29. 如請求項27之方法，其中在回焊該導電接合材料之後，該等導電構件之至少一者上之該導電接合材料無法形成具有該第二導電跡線之一焊料接頭。
  30. 如請求項27之方法，其中回焊該導電接合材料包含：回焊該第二導電跡線上之接合墊與該等導電構件之對應者之間之該導電接合材料。
  31. 如請求項27之方法，其中形成該等導電構件包含：在該第一導電跡線上形成複數個導電柱。
  32. 如請求項27之方法，其中：該第一半導體晶粒包含一基板及延伸穿過該基板之一基板通孔(TSV)；該第一跡線遠離該TSV橫向延伸；且形成該等導電構件包含：在該TSV與該第二跡線之間形成一或多個該等導電構件。
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