CN101783329B - 半导体元件及其制法 - Google Patents

半导体元件及其制法 Download PDF

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CN101783329B
CN101783329B CN2010100025087A CN201010002508A CN101783329B CN 101783329 B CN101783329 B CN 101783329B CN 2010100025087 A CN2010100025087 A CN 2010100025087A CN 201010002508 A CN201010002508 A CN 201010002508A CN 101783329 B CN101783329 B CN 101783329B
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semiconductor substrate
lining
silicon
dielectric layer
hole
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CN101783329A (zh
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陈明发
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种半导体元件及其制法。半导体基材具有一硅通孔，此硅通孔具有气隙介于硅通孔与半导体基材之间。形成一开口且此开口部分地穿过半导体基材。开口于其内侧形成第一衬层且被导电材料所填充。半导体基材的背侧被薄化以露出第一衬层，其随后被移除并被具有低介电常数或超低介电常数材料的第二介电层取代。本发明使用一低介电常数衬层或超低介电常数衬层，而不需担心其他工艺中对低介电常数材料造成的伤害。

Description

半导体元件及其制法
技术领域
本发明涉及一种集成电路(integrated circuit)，且特别涉及一种具有硅通孔(through-silicon via)的半导体元件。
背景技术
自从集成电路(integrated circuit，IC)发明以来，由于各种电子元件(例如：晶体管、二极管、电阻、电容等)的集成密度(integration density)持续改善，致使半导体工业经历了快速的成长。集成密度(integration density)的改善主要来自于最小特征尺寸(minimum feature size)的递减，因而能够将更多元件整合在一指定区域中。
这些集成密度(integration density)的改善基本上是二维(2D)空间的改善，改善这些集成元件在半导体晶片表面上所占据的体积。虽然在光刻(lithography)工艺方面的技术改革已大幅改善二维(2D)集成电路(IC)结构，然而在二维空间内可达成的密度仍有其物理上的极限，而这些极限之一就是制作这些元件所需要的最小尺寸。此外，当越多元件需设置于单一芯片时，则需要越复杂的芯片设计。
为了更进一步增加电路密度，已有研究开始发展三维(3D)集成电路(IC)。在一典型的三维(3D)集成电路(IC)构装工艺中，将两晶粒(die)粘接在一起，并在基材上的每一晶粒(die)与接触垫(contact pad)之间形成电性连接(electrical connection)。例如，试图将两晶粒(die)以彼此顶端对顶端的方式互相接合。随后再将此堆叠好的晶粒(die)接合到一载体基材(carrier substrate)上，并利用焊线(wire bond)接合使每一晶粒(die)上的接触垫(contact pad)与载体基材(carrier substrate)上的接触垫(contact pad)之间形成电性连接。然而，为了形成焊线连接(wire bonding)，此种研究需要一面积大于晶粒(die)的载体基材(carrier substrate)。
最近有越来越多的研究着重于硅通孔(through-silicon via，TSVs)。一般而言，通过蚀刻一通过基材的垂直通道，并将导电材料(例如铜)填充于该通道中而形成硅通孔(TSVs)。在将导电材料(例如铜)填充于该通道中之前，沿着该通道的侧壁形成一介电质衬层(liner)，该介电质衬层(liner)通常为四乙基硅酸盐(tetra-ethyl ortho-silicate，TEOS)。然而，四乙基硅酸盐(TEOS)的介电常数(dielectric constant)约为4.2，因此造成潜在的大电容。此大电容可能会对电阻电容(RC)电路的效能表现产生负面影响。
因此业界急需要一种形成硅通孔(TSVs)较佳的结构与方法。
发明内容
为减轻、解决或预防上述及其他问题，并且实现技术上的优势，下文特举出本发明的实施例，其提供具有硅通孔(through-silicon via)的半导体元件。
本发明提供一种半导体元件，包括：一具有一电路侧(circuit side)与一相对于该电路侧的背侧(backside)的半导体基材；一硅通孔延伸穿过该半导体基材；以及一第一介电层设置于该硅通孔与该半导体基材之间，其中该第一介电层延伸至该半导体基材的背侧表面的至少一部分上。
本发明另外提供一种半导体元件的制法，包括以下步骤，其中该制法包括：提供一半导体基材，其中该半导体基材具有一第一侧与相对于该第一侧的第二侧；形成一开口从该半导体基材的第一侧延伸到该半导体基材之中；形成一第一衬层(liner)沿着该开口的侧边；形成一导电材料于该开口中的第一衬层之上；薄化该半导体基材的第二侧，因而曝露至少一部分的第一衬层；移除介于该导体材料与该半导体基材之间的至少一部分第一衬层；以及移除之后，形成一第二衬层于该导电材料与该半导体基材之间。
本发明又包括一种半导体元件的制法，包括以下步骤：提供一半导体基材，其中该半导体基材具有一自电路侧(circuit side)延伸且部分穿过该半导体基材的硅通孔，以及一介于该半导体基材与该硅通孔之间的一第一衬层；薄化该半导体基材的背侧，因而曝露至少一部分的第一衬层；移除介于该硅通孔与该半导体基材之间的至少一部分第一衬层，因而形成一位于该半导体基材背侧之上且围绕该硅通孔的开口；以及形成一第二衬层于该开口中。
本发明使用一低介电常数衬层或超低介电常数衬层，而不需担心其他工艺中对低介电常数材料造成的伤害。例如，因为第二衬层是于工艺的后期形成，因此第二衬层在蚀刻工艺(例如干式蚀刻工艺、湿式蚀刻工艺、化学机械研磨等等)中将不会受到伤害。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出较佳实施例，并配合所附附图，作详细说明如下。
附图说明
图1～4为一系列剖面图，用以说明本发明的半导体元件的一实施例的工艺中间阶段。
并且，上述附图中的附图标记说明如下：
110～半导体基材
112～电路系统
116～层间介电层(inter-layer dielectric，ILD)
118～接触插塞(contact)
120～金属间介电层(inter-metal dielectric，IMD)
122～接点(contact)
124～硅通孔(through-silicon via)
126～第一衬层(first liner)
128～导线(conductive line)
130～保护层
132～接触插塞(contact)
134～载体基材(carrier substrate)
136～粘着剂(adhesive)
310～气隙(air gap)
410～第二衬层(second liner)
具体实施方式
以下特举出本发明的实施例，并配合所附附图作详细说明。以下实施例的元件和设计为了简化所公开的发明，并非用以限定本发明。
图1到图4显示形成一具有硅通孔(through-silicon via)的晶粒(die)的中间阶段，其中硅通孔(through-silicon via)适用于三维(3D)集成电路(例如：一堆叠晶粒结构(stacked die configuration))或一背侧接合结构(backside bondingconfiguration)。在本发明的各实施例与附图之中，相同的元件用相同的元件参考符号标示。
请参见图1，此图显示一半导体基材110具有电路112形成于其中。半导体基材110可包括，例如掺杂或未掺杂的硅块材(bulk silicon)，或一绝缘层上覆半导体(semiconductor-on-insulator，SOI)基材的主动层(active layer)。一般而言，一绝缘层上覆半导体(SOI)基材包括一半导体材料层(例如硅)形成于一绝缘体层上，其中绝缘体层材料可能包括，例如一埋藏氧化层(buried-oxidelayer，BOX)或是一氧化硅层。此绝缘体层通常形成在基材上，一般如硅基材或玻璃基材上，也可使用其他基材，例如多层(multi-layered)基材或梯度(gradient)基材。
形成于半导体基材110上的电路112可为适用于特殊应用的任何类型的电路。在一实施例中，此电路包括形成于基材上的电子元件，且此电子元件上覆盖一或多层介电层。可于介电层之间形成金属层，以传递电子元件之间的电子信号。电子元件也可形成在一或多层介电层中。
举例而言，电路112可包含多种N型金属-氧化物半导体(N-typemetal-oxide semiconductor，NMOS)及/或P型金属-氧化物半导体(P-typemetal-oxide semiconductor，PMOS)元件，例如晶体管、电容、电阻、二极管、光电二极管(photo-diodes)、保险丝等等，上述元件相互连接以进行一或多种功能。此功能可包括存储器结构、处理器结构(processing structures)、感测器、放大器、配电系统(power distribution)、输入/输出电路(input/output circuitry)等等。本领域普通技术人员应可了解，上述实施例仅为进一步解释所公开的发明，并非用以限定本发明。对于一指定的应用，也可使用其他合适的电路。
图1也显示层间介电层(inter-layer dielectric，ILD)116。此层间介电层(ILD)116的组成材料可包括一低介电常数(low-K)材料，例如磷硅玻璃(phosphosilicate glass，PSG)、硼磷硅玻璃(borophosphosilicate glass，BPSG)、氟硅玻璃(fluorinated silicate glass，FSG)、碳氧化硅(SiOxCy)、旋转涂布式玻璃(Spin-On-Glass)、旋转涂布式高分子(Spin-On-Polymers)、碳化硅(siliconcarbon)材料及其化合物、复合材料或上述的组合等等。而此层间介电层(ILD)116的形成方法可使用此技术领域中所熟知的任何合适方法，例如旋转涂布法(spinning)、化学气相沉积法(chemical vapor deposition，CVD)及等离于体增强型化学气相沉积法(plasma-enhanced CVD，PECVD)。须注意的是，层间介电层(ILD)116可包括多层介电层。
接触插塞(contact)118穿透层间介电层(ILD)116而形成，以提供对于电路112的电性接触(electrical contact)。此接触插塞(contact)118的形成，例如，利用光刻(photolithography)技术在层间介电层(ILD)116上沉积并图案化一光致抗蚀剂材料，由此露出一部分的层间介电层(ILD)116以将其转变成接触插塞(contact)118。可利用蚀刻工艺，例如非等向性干式蚀刻工艺(anisotropic dryetch process)在层间介电层(ILD)116中制造开口。此开口较佳使用扩散阻障层(diffusion barrier layer)及/或粘着层作为衬层，并且填充导电材料。此扩散阻障层(diffusion barrier layer)较佳包括一或多层的氮化钽(tantalum nitride，TaN)、钽(tantalum，Ta)、氮化钛(titanium nitride，TiN)、钛(titanium，Ti)、钨化钴(CoW)等等。而导电材料包括铜、钨、铝、银及上述的组合，或其他类似的材料，以形成如图1所显示的接触插塞(contact)118。
一或多层的金属间介电层(inter-metal dielectric，IMD)120及其相关的金属层(图中未显示)形成于层间介电层(ILD)116上。一般而言，利用此一或多层的金属间介电层(IMD)120及其相关的金属层使电路彼此互相连接，以形成外部电性接触(external electrical connection)。形成此金属间介电层(IMD)120的材料较佳为低介电常数(low-K)材料，例如以等离子体增强型化学气相沉积法(PECVD)技术或高密度等离子体化学气相沉积(high-density plasma CVD，HDPCVD)等等方法所形成的氟硅玻璃(FSG)，且此金属间介电层(IMD)120可能包括中间蚀刻停止层(intermediate etch stop layers)。在金属间介电层(IMD)的最上层形成接点(contact)122以提供一外部电性连接(external electricalconnection)。
值得注意的是，一或多层的蚀刻停止层(etch stop layers)(图中并未显示)形成于相邻的两介电层之间，例如，层间介电层(ILD)116与金属间介电层(IMD)120之间。一般而言，蚀刻停止层(etch stop layers)于形成通孔(vias)及/或接触插塞(contact)时，提供停止蚀刻工艺的机制。形成此蚀刻停止层(etchstop layers)的材料较佳为具有与相邻的层(例如，位于下方的半导体基材110、位于上方的层间介电层(ILD)116及金属间介电层(IMD)120)不同蚀刻选择性的介电材料。在一实施例中，形成蚀刻停止层(etch stop layers)的材料可包括氮化硅(silicon nitride SiN)、碳氮化硅(silicon nitricarbide，SiCN)、碳氧化硅(silicon oxycarbide，SiCO)、氮化碳(carbon nitride，CN)及上述的组合，或类似的材料，且此蚀刻停止层(etch stop layers)是通过化学气相沉积(CVD)或等离子体增强型化学气相沉积法(PECVD)技术所形成。
图1中也显示出一硅通孔(through-silicon via)124，其通过任意适当方法所形成。举例而言，通过一或多次的蚀刻工艺、研磨、激光工艺等等，形成延伸至半导体基材中110的开口(openings)。此开口较佳于其内侧形成一衬层，例如一第一衬层(first liner)126，此衬层作为隔离层。第一衬层126较佳包括一或多层的四乙基硅酸盐(TEOS)，然而也可使用其他材料。如同下文的详细说明，由于在随后的工艺步骤中，将移除一部分的第一衬层126，因此第一衬层126需使用一既容易加工又容易移除，同时对其他结构造成很少伤害或几乎不造成伤害的材料。
可于第一衬层(first liner)126的表面上形成且图案化得到保护层130，例如一聚亚酰胺(polyimide)材料。之后通过例如电镀(electroplating)技术将导电材料(例如铜、钨、铝、银及其组合等等)填充于开口中，以形成硅通孔124。也可使用其他材料，包括导电扩散阻障层(conductive diffusion barrier layer)，例如氮化钽(tantalum nitride，TaN)、钽(tantalum，Ta)、氮化钛(titanium nitride，TiN)、钛(titanium，Ti)、钨化钴(CoW)，或类似的材料。
接触插塞(contact)132，例如由铜、钨、锡铜合金(CuSn)、锡金合金(AuSn)、金铟合金(InAu)、锡铅合金(PbSn)，或类似的材料所形成的金属凸块(metalbumps)，与导线(conductive line)128形成电性接触，并且利用粘着剂(adhesive)136与载体基材(carrier substrate)134相粘接。一般而言，在后续的工艺步骤中，此载体基材134提供暂时的机械与结构支撑。在此方法中，将可降低甚或避免对半导体基材110所造成的伤害。载体基材134可包括，例如玻璃、氧化硅、氧化铝或类似的材料。粘着剂136可为任何适合的粘着剂，例如一紫外线(UV)胶，当其曝露于紫外线中将会丧失其粘着性。
值得注意的是，第一衬层126所选用的材料必须使第一衬层126与其周遭材料(例如半导体基材110、硅通孔124及任何相关的层间介电层(ILD)116及金属间介电层(IMD)120及/或蚀刻停止层(etch stop layers)的材料)具有高蚀刻选择性(high-etch selectivity)。如同下文的详细说明，在随后的工艺步骤中将移除第一衬层126，高蚀刻选择性(high-etch selectivity)将使第一衬层126的移除对其他层材料造成很少伤害或几乎不造成伤害。
值得注意的是，硅通孔124在附图中是自金属间介电层(IMD)120的上表面延伸至半导体基材110中，此结构仅为示范之用，因此也可采用其他的排列方式。在另一实施例中，硅通孔124是自层间介电层(ILD)116或半导体基材110的上表面开始延伸。例如，在一实施例中，于形成接触插塞(contact)118之后，通过一或多次的蚀刻工艺、研磨、激光工艺或其他类似工艺，产生延伸至半导体基材中110的开口而形成硅通孔124。上述开口较佳于其内侧形成一当作隔离层的衬层，例如第一衬层(first liner)126，并于开口中填充一如上文所述的导电材料。随后于硅通孔上形成金属间介电层(IMD)120，并且视需要的利用金属层(metallization layers)对硅通孔产生外部电性连接。
图示中的范例也显示，用以形成硅通孔124的导电材料延伸至介电层(例如金属间介电层(IMD)120)上表面。在本实施例中，硅通孔124与导线128可以由单一导电层形成，且此导线128使接点(contact)122与硅通孔124相互连接。在其他实施例中，硅通孔124可不与半导体基材110上的电路相互连接。在本实施例中，硅通孔124提供一电性连接，使形成于另一半导体基材(图中未显示)上的电路与基材背侧(backside)或基材电路侧(circuit side)相互连接。
依据本发明的一实施例，图2显示一薄化工艺(thinning process)，其实施在半导体基材110背侧(backside)上，以曝露第一衬层(first liner)126。此薄化工艺可通过蚀刻工艺及/或平坦化工艺，例如机械研磨(mechanical grinding)工艺或是化学机械研磨(chemical mechanical polishing，CMP)工艺。举例而言，初始阶段可实施平坦化工艺，例如机械研磨或化学机械研磨(CMP)工艺，以曝露第一衬层126，随后可实施一或多次对于第一衬层126与半导体基材110具有高蚀刻速率选择性(etch-rate selectivity)的湿式蚀刻工艺，以留下从半导体基材110背侧(backside)延伸突出的硅通孔124，如图2所示。此蚀刻工艺可为，例如，使用溴化氢/氧气(HBr/O2)等离子体、溴化氢/氯气/氧气(HBr/Cl2/O2)等离子体、六氟化硫/氯气(SF6/Cl2)等离子体、六氟化硫(SF6)等离子体等等的干式蚀刻工艺。值得注意的是，在其他实施例中，硅通孔124可能不从半导体基材110背侧(backside)延伸出来。
依据本发明的一实施例，图3显示一蚀刻工艺，其作用在于移除至少一部分的第一衬层126。实施一或多次对于第一衬层126与其周遭材料(例如半导体基材110、层间介电层(ILD)116、金属间介电层(IMD)120的材料、硅通孔124的导电材料及/或蚀刻停止层(etch stop layers)的材料)具有高蚀刻速率选择性(etch-rate selectivity)的湿式蚀刻工艺，结果可于硅通孔124周围形成一气隙(air gap)310。
在一实施例中，第一衬层126由四乙基硅酸盐(tetra-ethyl ortho-silicate，TEOS)所形成，可通过，例如，使用二氟化二卤(X2F2)等离子体的干式蚀刻工艺移除此第一衬层(first liner)126，也可通过湿式蚀刻工艺将其移除。
在一实施例中，图3也显示气隙(air gap)310延伸至硅通孔124的整个深度，并且延伸至金属间介电层(IMD)120的表面上。在此实施例中，气隙(airgap)310延伸至金属间介电层(IMD)120(或是层间介电层(ILD)116)的上表面。其他表面，例如由与第一衬层126具有高蚀刻速率选择性的材料所形成的接点(contact)122，可能导致蚀刻工艺的停止。此蚀刻工艺也可为时间控制式蚀刻(timed etch)，通过控制蚀刻时间以控制第一衬层(first liner)126移除的量。
依据本发明的一实施例，图4显示一第二衬层(second liner)410形成于半导体基材110(或是可能形成于半导体基材110表面上的原生氧化层(nativeoxide))背侧(backside)上，并且介于硅通孔124的导电材料与其周遭材料之间。形成此第二衬层(second liner)410的材料较佳为低介电常数(low-K)材料或超低介电常数(extra low-K，ELK)材料。此第二衬层(second liner)410也可使用聚亚酰胺(polyimide)材料。一般而言，低介电常数(low-K)材料具有一介电常数低于约3.5，而超低介电常数(extra low-K，ELK)材料则具有一介电常数低于约2.8。本领域普通技术人员应了解使用一低介电常数材料(例如低介电常数(loW-K)材料或超低介电常数(extra low-K，ELK)材料)与四乙基硅酸盐(tetra-ethyl ortho-silicate，TEOS)相比，可降低介电常数，进而可降低电容。
适合的低介电常数(low-K)材料包括氟硅玻璃(fluorinated silicate glass，FSG)、含碳或尚含有氮、氢、氧及上述的组合的介电材料。可通过，例如旋转涂布工艺(spin coating process)形成此第二衬层410。形成第二衬层410之后，可实施固化步骤，例如可利用紫外光(UV)进行紫外光固化步骤，固化低介电常数(low-K)材料或超低介电常数(extra low-K，ELK)材料，也可使用其他固化方法。
如图4所示，形成第二衬层410的材料延伸至半导体基材110背侧(backside)上，从而提供介于硅通孔124延伸突出部分与半导体基材110之间的绝缘层。值得注意的是，在一实施例中，为了使硅通孔124从第二衬层(second liner)410之上表面延伸突出，可能需要进行另一蚀刻工艺。特别是当第二衬层410通过形成顺应层(conformal layer)的方法形成时，此第二衬层410可能延伸至硅通孔124突出部分之上。在本实施例中，可沉积并图案化掩模(mask)，以曝露出第二衬层410位于硅通孔124突出部分之上，并且实施蚀刻工艺以移除第二衬层410曝露的部分，因而曝露出硅通孔124。若第二衬层410通过自平坦化(self-planarizing)工艺(例如旋涂工艺(spin-onprocess))形成，则不需实施上述工艺。
之后，为完成适用于特定领域的半导体元件，也可实施其他后段工艺(back-end-of-line，BEOL)。例如，可移除载体基材(carrier substrate)134，可于基材电路侧(circuit side)及背侧(backside)形成凸块底层金属(under-bumpmetallization)及接触插塞(contact)，可形成封装材料(encapsulant)，可实施切割(singulation)工艺以分割出单一晶粒(die)，可实施晶片级(wafer-level)或晶粒级(die-level)堆叠等等。值得注意的是，本发明所列举的实施例可应用于多种不同情况。例如，本发明所列举的实施例可应用于晶粒对晶粒(die-to-die)接合结构(bonding configuration)、晶粒对晶片(die-to-wafer)接合结构(bondingconfiguration)或晶片对晶片(wafer-to-wafer)接合结构(bonding configuration)。
本领域普通技术人员应了解上述工艺使用一低介电常数(low-K)衬层(liner)或超低介电常数(extra low-K，ELK)衬层，而不需担心其他工艺中对低介电常数(low-K)材料造成的伤害。例如，因为第二衬层(second liner)是于工艺的后期形成，因此第二衬层在蚀刻工艺(例如干式蚀刻工艺、湿式蚀刻工艺、化学机械研磨(CMP)等等)中将不会受到伤害。
虽然本发明已以多个较佳实施例公开如上，然而其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视随附的权利要求所界定的范围为准。

Claims (13)

1.一种半导体元件，包括：
一具有一电路侧与一相对于该电路侧的背侧的半导体基材；
一硅通孔延伸穿过该半导体基材；以及
一第一介电层设置于该硅通孔与该半导体基材之间，其中该第一介电层延伸至该半导体基材的背侧表面的至少一部分上，
该硅通孔的一部分从该第一介电层延伸突出，
该第一介电层延伸至该半导体基材电路侧的一第二介电层之上，电路位于所述第二介电层下方的层间介电层中。
2.如权利要求1所述的半导体元件，其中该第一介电层的介电常数低于3.5。
3.如权利要求1所述的半导体元件，其中该硅通孔的一部分从该半导体基材的背侧延伸突出。
4.一种半导体元件的制法，包括以下步骤：
提供一半导体基材，其中该半导体基材具有一第一侧与相对于该第一侧的第二侧；
形成一开口从该半导体基材的第一侧延伸到该半导体基材之中；
形成一第一衬层沿着该开口的侧壁；
形成一导电材料于该开口中的第一衬层之上；
薄化该半导体基材的第二侧，因而曝露至少一部分的第一衬层；
移除介于该导体材料与该半导体基材之间的至少一部分第一衬层；以及
移除之后，形成一第二衬层于该导电材料与该半导体基材之间。
5.如权利要求4所述的半导体元件的制法，其中该第一衬层包括一介电常数高于3.5的材料，该第二衬层包括一介电常数低于3.5的材料。
6.如权利要求4所述的半导体元件的制法，其中该第二衬层包括聚亚酰胺。
7.如权利要求4所述的半导体元件的制法，其中该薄化该半导体基材的第二侧的步骤包括蚀刻该半导体基材的第二侧，使得一部分的导电材料从该半导体基材的第二侧延伸突出。
8.如权利要求4所述的半导体元件的制法，其中该第二衬层延伸至该半导体基材第一侧的一介电层上。
9.如权利要求8所述的半导体元件的制法，其中该移除步骤包括移除至少一部分位于该半导体基材第一侧的该介电层上的第一衬层。
10.一种半导体元件的制法，包括以下步骤：
提供一半导体基材，其中该半导体基材具有一自电路侧延伸且部分穿过该半导体基材的硅通孔，以及一介于该半导体基材与该硅通孔之间的一第一衬层；
薄化该半导体基材的背侧，因而曝露至少一部分的第一衬层；
移除介于该硅通孔与该半导体基材之间的至少一部分第一衬层，因而形成一位于该半导体基材背侧之上且围绕该硅通孔的开口；以及
形成一第二衬层于该开口中。
11.如权利要求10所述的半导体元件的制法，其中该第二衬层延伸至该半导体基材背侧的一部分上。
12.如权利要求10所述的半导体元件的制法，其中该第二衬层包括一介电常数低于该第一衬层的介电材料。
13.如权利要求10所述的半导体元件的制法，其中该第二衬层延伸至该半导体基材电路侧的一部分上。
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US10707149B2 (en) 2020-07-07
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