JP6035520B2 - 半導体装置およびその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 131
- 238000004519 manufacturing process Methods 0.000 title claims description 33
- 239000000758 substrate Substances 0.000 claims description 83
- 238000000034 method Methods 0.000 claims description 72
- 239000011229 interlayer Substances 0.000 claims description 42
- 239000010410 layer Substances 0.000 claims description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 16
- 230000004888 barrier function Effects 0.000 claims description 12
- 238000000137 annealing Methods 0.000 claims description 10
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- 239000010949 copper Substances 0.000 description 11
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 238000001039 wet etching Methods 0.000 description 6
- 238000001459 lithography Methods 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
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- 238000007747 plating Methods 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
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- 230000010354 integration Effects 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
以下、本発明の第1の実施形態について図面を参照しながら説明する。
以下、本発明の第2の実施形態について図面を参照しながら説明する。
12 第1層間絶縁膜
13 コンタクトプラグ
14 貫通電極孔
15 絶縁膜
16 バリア膜
17 導電膜
18 貫通電極
19 (貫通電極側面の)空隙
20 第1配線層
21 第2層間絶縁膜
22 ストレスライナー膜
23 メモリチップ
24 ロジックチップ
25 貫通電極
26 マイクロバンプ
27 チップ間充填材
Claims (13)
- 半導体基板と、
前記半導体基板内に形成された貫通電極と、
前記半導体基板と前記貫通電極との間に介在するように形成された絶縁膜と、
前記半導体基板上に、前記貫通電極と所定距離だけ離間して形成されたトランジスタとを備え、
前記半導体基板と前記貫通電極との間における前記半導体基板の表面近傍領域には、前記絶縁膜が存在せず、前記半導体基板、前記貫通電極および前記表面近傍領域下に存在する前記絶縁膜とによって直接囲まれた空隙が形成されている半導体装置。 - 前記貫通電極は、前記半導体基板上に形成された第1層間絶縁膜中を貫通するように形成されており、
前記空隙は前記第1層間絶縁膜中にも形成されている請求項1に記載の半導体装置。 - 前記所定距離と前記空隙の前記半導体基板表面からの深さとは実質的に同等である請求項1または2に記載の半導体装置。
- 前記貫通電極上にさらに第1配線層を有し、
前記空隙内の一部には、前記第1配線層が埋め込まれている請求項1〜3のうちのいずれか1項に記載の半導体装置。 - 前記絶縁膜はシリコン窒化膜からなる請求項1〜4のうちのいずれか1項に記載の半導体装置。
- 前記貫通電極上およびその周辺部を除く前記半導体基板上に、前記トランジスタに応力を印加するストレスライナー膜が形成されている請求項1〜5のうちのいずれか1項に記載の半導体装置。
- 前記貫通電極は外側のバリア膜と内側の導電膜とからなる請求項1〜6のうちのいずれか1項に記載の半導体装置。
- 半導体基板上にトランジスタを含む第1層間絶縁膜を形成する工程(a)と、
前記トランジスタから所定距離だけ離れた前記第1層間絶縁膜内および前記半導体基板内に貫通孔を形成する工程(b)と、
前記貫通孔の内壁面上に絶縁膜を形成する工程(c)と、
前記工程(c)の後に、前記貫通孔内に導電膜を埋め込んで貫通電極を形成する工程(d)と、
前記工程(d)の後に、前記半導体基板をアニール処理する工程(e)と、
前記第1層間絶縁膜および前記半導体基板と、前記貫通電極との間に介在する前記絶縁膜の上部を除去し、前記半導体基板の表面近傍領域において、前記半導体基板と前記貫通電極との間に、前記半導体基板、前記貫通電極および前記表面近傍領域下に存在する前記絶縁膜とによって直接囲まれた空隙を形成する工程(f)とを備えた半導体装置の製造方法。 - 前記工程(f)では、前記所定距離と前記空隙の前記半導体基板表面からの深さとが実質的に同等になるように、前記絶縁膜の上部を除去する請求項8に記載の半導体装置の製造方法。
- 前記工程(f)の後に、前記貫通電極上を含む前記第1層間絶縁膜上に第1配線層を形成する工程(g)をさらに備え、
前記工程(g)では前記空隙内の一部に、前記第1配線層が埋め込まれる請求項8または9に記載の半導体装置の製造方法。 - 前記工程(a)と前記工程(b)との間に、
前記半導体基板上に、前記トランジスタに応力を印加するストレスライナー膜を形成する工程(i)と、
前記ストレスライナー膜における前記貫通電極上およびその周辺部を除去する工程(j)と、をさらに備えた請求項8〜10のうちのいずれか1項に記載の半導体装置の製造方法。 - 前記絶縁膜はシリコン窒化膜からなる請求項8〜11のうちのいずれか1項に記載の半導体装置の製造方法。
- 前記貫通電極は外側のバリア膜と内側の導電膜とからなる請求項8〜12のうちのいずれか1項に記載の半導体装置の製造方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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JP2012101097 | 2012-04-26 | ||
JP2012101097 | 2012-04-26 | ||
PCT/JP2012/007841 WO2013160976A1 (ja) | 2012-04-26 | 2012-12-07 | 半導体装置およびその製造方法 |
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JPWO2013160976A1 JPWO2013160976A1 (ja) | 2015-12-21 |
JP6035520B2 true JP6035520B2 (ja) | 2016-11-30 |
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US (1) | US9024390B2 (ja) |
JP (1) | JP6035520B2 (ja) |
WO (1) | WO2013160976A1 (ja) |
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US9337225B2 (en) * | 2013-09-13 | 2016-05-10 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and manufacturing method thereof |
US10847442B2 (en) * | 2014-02-24 | 2020-11-24 | Micron Technology, Inc. | Interconnect assemblies with through-silicon vias and stress-relief features |
JP6113679B2 (ja) * | 2014-03-14 | 2017-04-12 | 株式会社東芝 | 半導体装置 |
US9455220B2 (en) | 2014-05-31 | 2016-09-27 | Freescale Semiconductor, Inc. | Apparatus and method for placing stressors on interconnects within an integrated circuit device to manage electromigration failures |
US9466569B2 (en) | 2014-11-12 | 2016-10-11 | Freescale Semiconductor, Inc. | Though-substrate vias (TSVs) and method therefor |
TWI717846B (zh) | 2018-09-25 | 2021-02-01 | 精材科技股份有限公司 | 晶片封裝體及其製造方法 |
CN111599671A (zh) * | 2019-02-21 | 2020-08-28 | 东莞新科技术研究开发有限公司 | 一种长形条半导体背面开槽以消除应力的方法 |
JP2020145293A (ja) | 2019-03-05 | 2020-09-10 | キオクシア株式会社 | 半導体装置 |
US10896848B1 (en) * | 2019-10-15 | 2021-01-19 | Nanya Technology Corporation | Method of manufacturing a semiconductor device |
JP2020102656A (ja) * | 2020-04-06 | 2020-07-02 | キヤノン株式会社 | 半導体装置および半導体装置の製造方法 |
US20220319959A1 (en) * | 2021-04-01 | 2022-10-06 | Changxin Memory Technologies, Inc. | Semiconductor structure, method for forming same and stacked structure |
CN115172326A (zh) * | 2021-04-01 | 2022-10-11 | 长鑫存储技术有限公司 | 半导体结构及其形成方法 |
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JP2868008B1 (ja) | 1997-11-21 | 1999-03-10 | 日本電気株式会社 | 半導体装置及びその製造方法 |
JP2002289623A (ja) | 2001-03-28 | 2002-10-04 | Toshiba Corp | 半導体装置及びその製造方法 |
JP5026025B2 (ja) | 2006-08-24 | 2012-09-12 | 株式会社フジクラ | 半導体装置 |
JP4961185B2 (ja) | 2006-09-28 | 2012-06-27 | 株式会社日立製作所 | 半導体装置の製造方法 |
US7973409B2 (en) * | 2007-01-22 | 2011-07-05 | International Business Machines Corporation | Hybrid interconnect structure for performance improvement and reliability enhancement |
JP5242070B2 (ja) | 2007-03-29 | 2013-07-24 | 株式会社フジクラ | 貫通配線基板 |
US8049310B2 (en) * | 2008-04-01 | 2011-11-01 | Qimonda Ag | Semiconductor device with an interconnect element and method for manufacture |
JP2010010324A (ja) * | 2008-06-26 | 2010-01-14 | Toshiba Corp | 半導体装置及び半導体装置の製造方法 |
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KR20120067525A (ko) * | 2010-12-16 | 2012-06-26 | 삼성전자주식회사 | 반도체 소자 및 이의 제조 방법 |
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2012
- 2012-12-07 WO PCT/JP2012/007841 patent/WO2013160976A1/ja active Application Filing
- 2012-12-07 JP JP2013535173A patent/JP6035520B2/ja active Active
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JPWO2013160976A1 (ja) | 2015-12-21 |
US20130320562A1 (en) | 2013-12-05 |
US9024390B2 (en) | 2015-05-05 |
WO2013160976A1 (ja) | 2013-10-31 |
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