TWI497661B - 半導體基板 - Google Patents

半導體基板 Download PDF

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Publication number
TWI497661B
TWI497661B TW101129625A TW101129625A TWI497661B TW I497661 B TWI497661 B TW I497661B TW 101129625 A TW101129625 A TW 101129625A TW 101129625 A TW101129625 A TW 101129625A TW I497661 B TWI497661 B TW I497661B
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Taiwan
Prior art keywords
conductive
substrate
conductive pad
insulating layer
pad
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TW101129625A
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TW201407729A (zh
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Peng Shu Chen
Min Lin Lee
Shih Hsien Wu
Shur Fen Liu
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Ind Tech Res Inst
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Priority to TW101129625A priority Critical patent/TWI497661B/zh
Priority to CN201210367115.5A priority patent/CN103594440B/zh
Priority to US13/797,366 priority patent/US9029984B2/en
Publication of TW201407729A publication Critical patent/TW201407729A/zh
Priority to US14/570,684 priority patent/US9343393B2/en
Application granted granted Critical
Publication of TWI497661B publication Critical patent/TWI497661B/zh

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Description

半導體基板
實施例係關於一種半導體基板。
為了實現高密度的封裝與改善高速整合電路系統通道頻寬，三維積體電路(3D ICs)技術中矽道通孔為一個關鍵。在三維積體電路的整合電路技術中，直通矽晶穿孔(Through-Silicon Via，TSV)封裝技術是主要核心技術，其可以在晶片與晶片之間的進行垂直式連接且可大幅的縮小連接線的長度。除此之外，在3D ICs外部的連接，矽中介板也是一另一個必要的技術，不只提供二維的連接線層，還提供多個疊堆晶片之間的三維連接線。在3D ICs高速數位裝置應用上，TSV與中介板必需被設計的更寬頻、小尺寸進一步達到高效能與縮小化目標。
TSV與矽基板之間有一層介質層做為電性上的隔離，此用以絕緣的介質層加上半導體晶片本體的導電性會產生不容忽視的電容效應。電容效應與損耗的矽載板會隨著頻率的變化而造成高速數位訊號的失真。為了改善高速訊號通道上的訊號隨著頻率改變而衰減的程度，等化器電路已被實際應用於信號傳輸損耗的改善上。
現有3D IC技術透過TSV於晶片上進行信號傳輸時會面臨TSV的非線性信號傳輸損耗現象，造成高速信號傳輸(例如20Gbps或25Gbps)時的信號失真問題。透過對傳輸線媒介頻率嚮應的等化 設計，可改善上述的信號失真問題。一般而言，被動式等化器電路需要電阻與電容元件，對晶片的設計與製造而言屬額外兩種材料與製程設計，將造成額外晶片電路設計、製程及面積問題。且矽晶片上等化電路的存在將佔據更大的晶片面積，造成成本及設計複雜度的增加。
實施例提出一種半導體基板或基板，以晶片半導體或矽晶半導體或矽晶中介層為基礎來形成電阻元件或電容元件。
根據一實施例所述之一種半導體基板，包括有一基板、一第一導電接墊、一第二導電接墊以及一導電柱。其中基板具有相對之一第一表面與一第二表面；第一導電接墊形成於基板之第一表面之一預定位置；第二導電接墊對應第一導電接墊之位置而形成於基板之第二表面之一預定位置；導電柱係形成於基板中，導電柱與第一導電接墊以及第一導電接墊其中之一接觸。
根據另一實施例所述之一種半導體基板，包括有一基板、一第一導電接墊、一第二導電接墊、一第三導電接墊、第一導電柱、第三絕緣層、第四絕緣層。其中基板具有相對之一第一表面與一第二表面；第一導電接墊形成於該基板之第一表面之一預定位置；第二導電接墊對應第一導電接墊之位置而形成於該基板之一第二表面之一預定位置；第三導電接墊形成於該基板之該第二表面；第一導電柱形成於該基板之中並電性連接該第三導電接墊與該第一導電接墊；第一絕緣層形成於該第一導電柱之周圍；第三 絕緣層形成於該基板之一第一表面之其餘部份；第四絕緣層形成於該基板之一第二表面之其餘部份。
根據另一實施例所述之一種半導體基板，包括有一基板、一第一導電接墊、一第二導電接墊、一第三導電接墊、第一導電柱、第一絕緣層、第三絕緣層、第四絕緣層以及介電層。其中基板具有相對之一第一表面與一第二表面；第一導電接墊形成於該基板之一第一表面之一預定位置；第一導電柱形成於該基板之中並與該第一導電接墊形成電性連接；第二導電接墊對應該第一導電柱之位置而形成於該基板之一第二表面之一預定位置；介電層形成於該第二導電接墊上；第三導電接墊形成於該基板之該第二表面以及該介電層上；第一絕緣層形成於該第一導電柱之周圍；第三絕緣層形成於該基板之一第一表面之其餘部份；第四絕緣層形成於該基板之一第二表面之其餘部份。
以上之關於實施例內容之說明及以下之實施方式之說明係用以示範與解釋實施例之精神與原理，並且提供專利申請範圍更進一步之解釋。
以下在實施方式中詳細敘述實施例之詳細特徵以及優點，其內容足以使任何熟習相關技藝者了解實施例之技術內容並據以實施，且根據本說明書所揭露之內容、申請專利範圍及圖式，任何熟習相關技藝者可輕易地理解實施例相關之目的及優點。以下之實施例係進一步詳細說明實施例之觀點，但非以任何觀點限制實 施例之範疇。
請參考『第1圖』，係為實施例所揭露之半導體基板之實施例示意圖，包括有包括一基板20，在一實施例中，基板20係為一矽基板，在一實施例中係為晶片半導體或矽晶半導體或矽晶中介層(semiconductor interposer)。在基板20的第一表面的一預定位置處形成有一第一導電接墊21，在第二表面相應於第一導電接墊21的位置處形成有一第二導電接墊22，延伸第二導電接墊22處以埋孔的方式形成有一導電柱25。導電柱25與第一導電接墊21的距離大約是5~10μm之間。導電柱25是用金屬的材料形成。
在這個實施例中，第一導電接墊21、第二導電接墊22、導電柱25以及其中夾置的基板20部份共同形成電阻元件10，其中d為基板20的厚度，L為導電柱25的長度，A為導電柱25的截面積。電阻元件10的電阻值R可透過以下的關係式得出：R=ρ[(d-L)/A]，其中ρ為基板20之導電率。透過調整上述關係式中的參數可以獲得不同之電阻值R，例如，在ρ、d、A三個參數均不變的條件下，L越大則R越小，因此，電阻元件10的電阻值R可根據不同的需求進行調整。在後續的實施例中，為了圖式的簡潔，將不在標示公式中的參數，因此當提到類似的參數時，即對應公式中相對應的參數。
雖然圖式繪製導電柱25與第二導電接墊22接觸，當然導電柱25也可形成與第一導電接墊21接觸。
請參考『第2A圖』，係為實施例所揭露之半導體基板之另一 實施例示意圖，此一實施例與『第1圖』之實施例類似。在導電柱25的旁邊距離很近的地方又需要製作一個盲孔或是訊號的走線的通孔時，可以在導電柱25的周圍製作絕緣層23做電性上的隔絕。
請參考『第2B圖』，係為實施例所揭露之半導體基板之另一實施例示意圖，此一實施例與『第2A圖』之實施例類似，亦即在導電柱25的旁邊距離很近的地方製作另一個電阻。其組成方式與『第1圖』的結構相同。在基板20的第一表面的另一預定位置處形成有一第一導電接墊27，在第二表面相應於第一導電接墊27的位置處形成有一第二導電接墊28，延伸第二導電接墊28處以埋孔的方式形成有一導電柱29。
在『第2A圖』與『第2B圖』的實施例中，導電柱25與第一導電接墊21的距離大約是5~10μm之間。
請參考『第3圖』，係為實施例所揭露之半導體基板之另一實施例示意圖，此一實施例的結構基本上與『第1圖』的實施例類似。不同之處在於在第一表面之第一導電接墊21的其他部份形成有第一絕緣層24，第二表面之第二導電接墊22的其他部份形成有第二絕緣層26。第一絕緣層24與第二絕緣層26的主要作用是將基板20與其他的基板或元件進行電性隔離。在此處說明的實施例中第一絕緣層24與第二絕緣層26非必要。
在以上的這些實施例中可以看到導電柱25的寬度，或者說直徑，小於第一導電接墊21或第二導電接墊22的寬度，然而這並 非是限定兩者的寬度關係。以下描述的實施例若有類似的情況，同樣並非限定兩者的寬度關係。
請參考『第4A圖』，係為實施例所揭露之半導體基板之另一實施例示意圖，『第4A圖』的實施例係為『第3圖』的延伸，係透過另一導電柱將與外部元件溝通的兩個電極設置於基板30的同一表面。
此一實施例中包括有一基板30，在一實施例中，基板30係為一矽基板，在一實施例中係為晶片半導體或矽晶半導體或矽晶中介層。在基板30第一表面的一預定位置處形成有一第一導電接墊31，這個第一導電接墊31的大小比前述的實施例都大。延伸第一導電接墊31處以埋孔的方式形成有一第二導電柱33，在第二表面相應於第一導電接墊31的位置處形成有一第二導電接墊32。延伸第一導電接墊31在基板中的另一位置以導通孔的方式形成有一第一導電柱35，在基板30的第二表面上形成第三導電接墊34，第三導電接墊34與第一導電柱35形成電性連接。第三導電接墊34係與第一導電接墊31形成於基板30的同一表面。第二導電柱33與第二導電接墊32的距離大約是5~10μm之間。由於有第二導電柱33與第一導電柱35間隔較近的關係，因此需要設計絕緣層。第二導電柱33的周圍形成有第二絕緣層36，第一導電柱35的周圍有形成有第一絕緣層37。第一絕緣層36也隔離第二導電柱33與第一導電柱35。第一絕緣層36與第二絕緣層37除了使第二導電柱33與第一導電柱35形成電性隔離外，也可使其與基板30形 成的電性隔離。當然基板30表面的其他部份也都形成有第三絕緣層38、第四絕緣層39。
請參考『第4B圖』，係為實施例所揭露之半導體基板之另一實施例示意圖，其係為『第4A圖』的應用實施例，係將『第4A圖』的元件重複配置於基板中。而『第4C圖』，係為實施例所揭露之半導體基板之另一實施例示意圖，其與『第4B圖』的結構相當類似，因此採用相同的標號。不同之處在於圖式右側的部份的第二導電柱33，亦即兩個第二導電柱33其中之一，其周圍沒有形成絕緣層40。請參考『第5圖』，係為實施例所揭露之半導體基板之另一實施例示意圖。其與『第4A圖』之實施例類似，不同之處在於本實施例沒有導電柱。因此當基板30厚度小於10μm時，可以採用『第5圖』的實施例。
在『第4A圖』與『第5圖』的實施例中，差異在於第二導電柱33的高度不同，『第5圖』係說明第二導電柱33高度等於0時的實施例。從這兩個實施例可以得知，依據前述的公式：R=ρ[(d-L)/A]，在ρ、d、A三個參數均不變的條件下，L越大則R越小，因此，所形成的電阻元件的電阻值R可透過調整第二導電柱33的高度來調整。請參考『第6A圖』，係為實施例所揭露之半導體基板之另一實施例示意圖。
此一實施例中包括有一基板50，在一實施例中，基板50係為一矽基板，在一實施例中係為晶片半導體或矽晶半導體或矽晶中介層。在基板50第一表面的一預定位置處形成有一第一導電接墊 51，這個第一導電接墊51的大小比前述的實施例都大。延伸第一導電接墊51處以埋孔的方式形成有一第二導電柱53，在第二表面相應於第一導電接墊51的位置處形成有一第三導電接墊60。延伸第一導電接墊51在基板中的另一位置以導通孔的方式形成有一第一導電柱55，第二導電接墊52則延伸第一導電柱55形成，第二導電接墊52透過第一導電柱55與第二導電柱53形成電性連接。第二導電接墊52係與第三導電接墊60形成於基板50的同一表面。第二導電柱53與第三導電接墊60的距離大約是5~10μm之間。
第二導電接墊52上形成有介電層54，其係覆蓋第二導電接墊52。因此，透過這樣的結構，第二導電接墊52與其上對應的第三導電接墊60的部份，配合介電層54可形成一電容結構。第一導電接墊51、第二導電柱53、第三導電接墊60以及其中夾置的基板50部份共同形成一電阻元件。因為共用第一導電接墊51，因此形成一電阻電容並聯的架構。
由於有第二導電柱53與第一導電柱55間隔較近的關係，因此需要設計絕緣層。第二導電柱53的周圍形成有第二絕緣層56，第一導電柱55的周圍有形成有第一絕緣層57。第二絕緣層56也隔離第二導電柱53與第一導電柱55。第二絕緣層56與第一絕緣層57除了使第二導電柱53與第一導電柱55形成電性隔離外，也可使其與基板50形成的電性隔離。當然基板50表面的其他部份也都形成有第三絕緣層58、第四絕緣層59。
請參考『第6B圖』，係為實施例所揭露之半導體基板之另一實施例示意圖，其係與『第6A圖』類似，不同之處在於第二導電柱53周圍沒有形成絕緣層。
在『第6B圖』與『第6C圖』的實施例中，差異在於第二導電柱53的高度不同，『第6C圖』係說明第二導電柱53高度等於0時的實施例。從這兩個實施例可以得知，依據前述的公式：R=ρ[(d-L)/A]，在ρ、d、A三個參數均不變的條件下，L越大則R越小，因此，所形成的電阻元件的電阻值R可透過調整第二導電柱53的高度來調整。
在前述的實施例中，導電柱的深度(或長度)、基板的厚度或者導電柱與導電接墊之間的間距可控制電阻值的大小。
在以上所述的實施例中，凡提到導電接墊或者導電柱，這些元件的主要功用都是用來傳遞電訊號，因此在材料上當然是選擇金屬，例如一般半導體技術領域常用的金或者銅等等。
而從以上的實施例可以看出來，不論是電阻或者電容元件，均是形成於垂直於基板的方向，而非是水平式的電容或電阻。
半導體基板在各式等化器的設計上大都是實現在晶片電路上，因此除了佔用晶片電路面積之外，在等化電路設計時也無法考慮到未來封裝規格。在前述實施例中，以基板或者搭配導電柱作為電阻元件。在前述實施例之結構中可透過基板的厚度及導電柱與導電接墊間的距離以對電阻進行設計值的調整，因此可獲得穩定的電阻值，降低等化電路的實現難度。
在前述的實施例中，以矽晶體塊材(Silicon Bulk)之基板作為電阻元件的優點無須於晶片上或是矽中介板上以額外元件製作電阻元件，而為了達到等化電路合理的電阻設計值(數Ohm~100Ohm)，矽晶體塊材必須足夠薄，例如小於等於10um，或者5um，或者到達1um。因此前述的實施例即可透過控制晶片或矽中介板的厚度來調整等化電路的電阻值。前述的實施例同時亦提出以埋孔作為調整調整等化電路的電阻值之用，如此在晶片或是矽中介板厚度超過10um時，同樣能透過實施例發揮利用矽晶體塊材作為電阻的優點。當以矽晶體塊材作為電阻元件時，前段或後段的製程便無需顧慮到製成溫度對電阻值的影響，因此結構中電容元件等相關製程的設計及執行自由度都會相當的高。
請參考『第7圖』，係為實施例所揭露之半導體基板之另一實施例示意圖，其係應用『第6A圖』之實施例。這個實施例主要說明應用半導體基板時可使用錫鉛構成的凸塊61(Bump)或錫球來與其他的基板或者電子元件形成電性連接。因此，參考『第8圖』，係為『第7圖』之實施例中，與晶片70電性連接之實施例示意圖。
請參考『第9圖』，係為實施例所揭露之半導體基板之應用實施例示意圖。為了簡化圖式，本實施例省略的大部分的標號。在這個實施例中，可以看到係堆疊了多個晶片71、72、79，每個晶片上都形成有傳遞訊號的導通路徑，此外，晶片71與72中間夾置了一個前述實施例所討論的半導體基板80，其中形成有等化電路81係應用『第6A圖』之實施例，等化電路82係應用『第6B 圖』之實施例，等化電路83係應用『第6C圖』之實施例。『第9圖』之等化電路結構的應用結構，可於高速訊號傳輸路徑上進行訊號傳遞品質的改善。
根據本揭露之實施例，利用基板當作等化電路所需的電阻元件，在其他的實施例中，也可利用埋孔的深度或是晶片的厚度(TSV的高度)來控制電阻值的大小。而在其他的實施例中，在等化電路的導電接墊上直接製作上絕緣材料將電容製作於等化電路上。而在其他的實施例中，係將前述的結構利用RC並聯的方式達到等化器的設計。在本揭露所有的等化器所需的被動元件皆可利用IC Backend或構裝製程來完成電阻及電容元件，使本創作具有低成本的優勢。
此外，本揭露之實施例之實現方式可利用後段製程方式實現，因此未來於實現此創意結構時，可依三維積體電路之晶片封裝規格的不同，例如不同厚度的晶片、不同的晶片堆疊顆數、不同深寬比的TSV而對電容或電阻進行設計值的調整。
雖然實施例以前述之實施例揭露如上，然其並非用以限定實施例。在不脫離實施例之精神和範圍內，所為之更動與潤飾，均屬實施例之專利保護範圍。關於實施例所界定之保護範圍請參考所附之申請專利範圍。
10‧‧‧電阻元件
20‧‧‧基板
21‧‧‧第一導電接墊
22‧‧‧第二導電接墊
23‧‧‧絕緣層
24‧‧‧第一絕緣層
25‧‧‧導電柱
26‧‧‧第二絕緣層
27‧‧‧第一導電接墊
28‧‧‧第二導電接墊
29‧‧‧導電柱
30‧‧‧基板
31‧‧‧第一導電接墊
32‧‧‧第二導電接墊
33‧‧‧第二導電柱
34‧‧‧第三導電接墊
35‧‧‧第一導電柱
36‧‧‧第二絕緣層
37‧‧‧第一絕緣層
38‧‧‧第三絕緣層
39‧‧‧第四絕緣層
40‧‧‧絕緣層
50‧‧‧基板
51‧‧‧第一導電接墊
52‧‧‧第二導電接墊
53‧‧‧第二導電柱
54‧‧‧介電層
55‧‧‧第一導電柱
56‧‧‧第二絕緣層
57‧‧‧第一絕緣層
58‧‧‧第三絕緣層
59‧‧‧第四絕緣層
60‧‧‧第三導電接墊
61‧‧‧凸塊
70‧‧‧晶片
71‧‧‧晶片
72‧‧‧晶片
79‧‧‧晶片
80‧‧‧半導體基板
81‧‧‧等化電路
82‧‧‧等化電路
83‧‧‧等化電路
d‧‧‧基板的厚度
L‧‧‧導電柱的長度
A‧‧‧導電柱的截面積
第1圖係為實施例所揭露之半導體基板之一實施例示意圖。
第2A圖~第2B圖係為實施例所揭露之半導體基板之另一實 施例示意圖。
第3圖係為實施例所揭露之半導體基板之另一實施例示意圖。
第4A圖~第4C圖係為實施例所揭露之半導體基板之另一實施例示意圖。
第5圖係為實施例所揭露之半導體基板之另一實施例示意圖。
第6A圖~第6C圖係為實施例所揭露之半導體基板之另一實施例示意圖。
第7圖係為實施例所揭露之半導體基板之應用實施例示意圖。
第8圖係為實施例所揭露之半導體基板之應用實施例示意圖。
第9圖係為實施例所揭露之半導體基板之應用實施例示意圖。
10‧‧‧電阻元件
20‧‧‧基板
21‧‧‧第一導電接墊
22‧‧‧第二導電接墊
25‧‧‧導電柱
d‧‧‧基板的厚度
L‧‧‧導電柱的長度
A‧‧‧導電柱的截面積

Claims (12)

  1. 一種半導體基板，包括有：一基板，具有相對之一第一表面與一第二表面；一第一導電接墊，形成於該基板之該第一表面之一預定位置；一第二導電接墊，對應該第一導電接墊之位置而形成於該基板之該第二表面之一預定位置；以及一導電柱，係形成於該基板中，該導電柱與該第一導電接墊以及該第二導電接墊其中之一接觸；其中，由該第一導電接墊、該第二導電接墊、該導電柱以及該基板與該第一導電接墊和該導電柱重疊部份共同形成一電阻元件，且該電阻元件的一阻值係隨著該導電柱的一長度增加而降低。
  2. 如請求項1所述之半導體基板，其中更包括有一絕緣層，形成於該導電柱之周圍。
  3. 如請求項1所述之半導體基板，其中更包括有：一第一絕緣層，形成於該基板之該第一表面之其餘部份；以及一第二絕緣層，形成於該基板之該第二表面之其餘部份。
  4. 如請求項1至3之任一項所述之半導體基板，其中該導電柱與該第一導電接墊之距離為5μm~10μm之間。
  5. 一種半導體基板，包括有： 一基板，具有相對之一第一表面與一二表面；一第一導電接墊，形成於該基板之該第一表面之一預定位置；一第二導電接墊，對應該第一導電接墊之位置而形成於該基板之該第二表面之一預定位置；一第三導電接墊，形成於該基板之該第二表面；一第一導電柱，形成於該基板之中並與該第三導電接墊與該第一導電接墊形成電性連接；一第一絕緣層，形成於該第一導電柱之周圍；一第三絕緣層，形成於該基板之該第一表面之其餘部份；一第四絕緣層，形成於該基板之該第二表面之其餘部份；以及一第二導電柱，係形成於該基板中並與該第一導電接墊接觸；其中，由該第一導電接墊、該第二導電柱、該第三導電接墊以及該基板於該第三導電接墊和該第二導電柱之間的一部份形成一電阻元件，且該電阻元件的一阻值係隨著該第二導電柱的一長度增加而降低。
  6. 如請求項5所述之半導體基板，其中該第二導電柱之周圍形成有一第二絕緣層。
  7. 如請求項5所述之半導體基板，其中該第二導電柱與該第二導電接墊之距離為5μm~10μm之間。
  8. 一種半導體基板，包括有：一基板，具有相對之一第一表面與一第二表面；一第一導電接墊，形成於該基板之該第一表面之一預定位置；一第一導電柱，形成於該基板之中並與該第一導電接墊形成電性連接；一第二導電接墊，對應該第一導電柱之位置而形成於該基板之該第二表面之一預定位置；一介電層，形成於該第二導電接墊上；一第三導電接墊，形成於該基板之該第二表面以及該介電電層上；一第一絕緣層，形成於該第一導電柱之周圍；一第三絕緣層，形成於該基板之該第一表面之其餘部份；一第四絕緣層，形成於該基板之該第二表面之其餘部份；以及一第二導電柱，係形成於該基板中並與該第一導電接墊接觸；其中，由該第一導電接墊、該第二導電柱、該第三導電接墊以及該基板於該第三導電接墊和該第二導電柱之間的一部份形成一電阻元件，且該電阻元件的一阻值係隨著該第二導電柱的一長度增加而降低。
  9. 如請求項8所述之半導體基板，其中該第二導電柱與該第三導 電接墊之距離為5μm~10μm之間。
  10. 如請求項8所述之半導體基板，其中該第二導電柱之周圍形成有一第二絕緣層。
  11. 如請求項8所述之半導體基板，其中更包括有一凸塊形成於該第三導電接墊之上。
  12. 如請求項11所述之半導體基板，其中更包括有一晶片，形成於該凸塊之上。
TW101129625A 2012-08-15 2012-08-15 半導體基板 TWI497661B (zh)

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US13/797,366 US9029984B2 (en) 2012-08-15 2013-03-12 Semiconductor substrate assembly
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