CN103681549A - 通孔结构及方法 - Google Patents
通孔结构及方法 Download PDFInfo
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- CN103681549A CN103681549A CN201210539996.4A CN201210539996A CN103681549A CN 103681549 A CN103681549 A CN 103681549A CN 201210539996 A CN201210539996 A CN 201210539996A CN 103681549 A CN103681549 A CN 103681549A
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- electric conducting
- conducting material
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Abstract
一种装置包括形成在衬底中的通孔。通孔耦合在衬底的第一侧和第二侧之间。通孔包括紧邻衬底的第二侧的底部,其中,底部由导电材料形成。通孔进一步包括由导电材料形成的侧壁部和形成在侧壁部之间的中部,其中,中部由介电材料形成。本发明还提供了通孔结构及方法。
Description
技术领域
本发明一般地涉及半导体技术领域,更具体地来说,涉及半导体装置及其形成方法。
背景技术
由于多种电子部件(例如,晶体管、二极管、电阻、电容器等)的集成密度的不断改进,从而,半导体工业经历了快速的增长。在极大程度上,在集成密度上的这种改进来自于最小部件尺寸的不断减小,从而使得更多的部件集成在指定区域中。最近,由于对甚至更小的电子器件的需求的增加,所以对半导体管芯的更小的封装技术和更有创造性的封装技术的需求也在增加。
随着半导体技术的发展,三维集成电路已经成为进一步减小半导体芯片的物理尺寸的一个有效选择。在三维集成电路中,在不同晶圆上制造诸如电路逻辑、存储处理、处理器电路等的有源电路,并且使用拾取-放置技术在封装部件的顶部上堆叠每个晶圆管芯。通过采用三维集成电路可以获得更高的密度。总而言之,三维集成电路可以获得较小的物理尺寸、较小的成本效益、提高的性能以及较低能耗。
为了连接在堆叠半导体管芯中的电路,使用硅通孔提供穿过堆叠管芯主体的垂直连接沟道。可以通过使用合适的技术来形成硅通孔。例如,为了形成硅通孔,可以在半导体衬底的有源侧上形成开口,其中,开口比半导体衬底的有源器件更深地延伸到半导体衬底中。然后,这些开口填充有诸如铜、铝、钨、银、金等的导电材料。在填充开口之后,可以通过诸如化学机械抛光工艺或蚀刻工艺的减薄工艺减薄半导体衬底的背部。对半导体背部实施减薄工艺直到暴露硅通孔的导电材料为止。
发明内容
为了解决现有技术中所存在的缺陷,根据本发明的一方面,提供了一种装置,包括:层间介电层,形成在衬底的第一侧上;第一金属化层,形成在所述层间介电层上方,所述第一金属化层包括形成在第一金属间介电材料中的多条金属线;以及通孔,形成在所述衬底中,所述通孔包括:底部,由导电材料形成,并且所述底部紧邻所述衬底的第二侧;侧壁部,由所述导电材料形成,所述侧壁部的第一端耦合至所述底部且所述侧壁部的第二端耦合至所述第一金属化层的金属线;和中部,形成在所述侧壁部之间,并且所述中部由介电材料形成。
在该装置中,所述通孔包括:衬里层,形成在通孔沟槽的侧壁上;势垒层,形成在所述衬里层上;以及晶种层,形成在所述势垒层上。
在该装置中,所述中部的底面低于所述衬底的顶面。
在该装置中,所述中部由所述第一金属间介电材料形成。
在该装置中,所述第一金属间介电材料是感光聚合物材料。
该装置进一步包括:第一侧互连结构,形成在所述第一金属化层上方;以及第二侧互连结构,形成在所述衬底的所述第二侧上方,其中,所述第二侧互连结构耦合至所述通孔。
在该装置中,所述导电材料是铜。
根据本发明的另一方面,提供了一种方法,包括:在所述衬底的第一侧上方形成层间介电层;在所述衬底中形成开口;用导电材料填充所述开口,其中,所述开口的上部没有所述导电材料;以及在所述衬底上方沉积介电材料,其中,所述介电材料被填充在所述开口的上部中。
该方法进一步包括:在所述开口的侧壁和底部上形成衬里层;在所述衬里层上方形成势垒层;在所述势垒层上方形成晶种层;沉积所述晶种层的光刻胶层;图案化所述光刻胶层;以及对所述晶种层应用喷镀工艺。
该方法进一步包括:使用光刻胶剥离工艺去除所述光刻胶层的剩余部分。
该方法进一步包括:在所述衬底的第一侧上方形成第一侧互连结构;以及对所述衬底的第二侧应用减薄工艺直到从所述衬底的第二侧露出所述开口的所述导电材料为止。
在该方法中,所述导电材料是铜。
在该方法中,所述介电材料是感光材料。
在该方法中,所述上部的底面低于所述衬底的顶面。
根据本发明的又一方面,提供了一种方法,包括:在衬底中自所述衬底的第一侧形成开口;在所述开口的侧壁和底部上沉积衬里层;在所述衬里层上方沉积势垒层;在所述势垒层上方沉积晶种层;在所述晶种层上方形成光刻胶层;图案化所述光刻胶层,从而:去除所述开口中的所述光刻胶层;以及去除所述衬底上的所述光刻胶层的部分,以在所述光刻胶层中形成互连沟槽;使用电化学镀工艺用导电材料填充所述开口,所述开口的上部没有所述导电材料;使用所述电化学镀工艺用所述导电材料将所述互连沟槽填充至第一金属线;以及在所述开口和所述互连沟槽上方沉积介电材料,其中,所述开口的所述上部填充有所述介电材料。
该方法进一步包括:研磨所述衬底的第二侧直到暴露所述开口的所述导电材料为止。
在该方法中,所述导电材料是铜。
在该方法中,控制所述电化学镀工艺,使得所述导电材料沉积在所述开口的侧壁和底部上,并且所述底部的顶面低于所述衬底的顶面。
该方法进一步包括:形成第二侧接触件,所述第二侧接触件耦合至所述开口的所述底部。
该方法进一步包括:沉积第二侧钝化层,所述第二侧接触件内嵌在所述第二侧钝化层中。
附图说明
为了更完整的理解本发明及其优点,现在将结合附图所进行的以下描述作为参考,其中:
图1示出了根据实施例的半导体器件的截面图;
图2示出了根据实施例在衬底中形成多个电路之后的半导体器件;
图3示出了根据实施例在衬底中形成开口之后的图2所示的半导体器件的截面图;
图4示出了根据实施例在开口的侧壁和底部上形成衬里层之后的图3所示的半导体器件的截面图;
图5示出了根据实施例在衬里层上方形成势垒层之后的图4所示的半导体器件的截面图;
图6示出了根据实施例在势垒层上方形成晶种层之后的图5所示的半导体器件的截面图;
图7示出了根据实施例在晶种层上方形成介电层之后的图6所示的半导体器件的截面图;
图8示出了根据实施例在对介电层实施图案化工艺之后的图7所示的半导体器件的截面图;
图9示出了根据实施例在开口中填充导电材料之后的图8所示的半导体器件的截面图;
图10示出了根据实施例在去除剩余的光刻胶层之后的图9所示的半导体器件的截面图;
图11示出了根据实施例在沉积金属间介电层之后的图10所示的半导体器件的截面图;
图12示出了根据实施例在第一金属化层上方形成两个其他金属化层之后的图11所示的半导体器件的截面图;
图13示出了根据实施例在金属间介电层的顶部上形成钝化层之后的图12所示的半导体器件的截面图;
图14示出了根据实施例在钝化层的顶部上形成第一聚合物层之后的图13所示的半导体器件的截面图;
图15示出了根据实施例在对第一聚合物层的表面实施图案化工艺之后的图14所示的半导体器件的截面图;
图16示出了根据实施例在第一聚合物层的顶部上形成晶种层之后的图15所示的半导体器件的截面图;
图17示出了根据实施例在晶种层的顶部上形成再分布线之后的图5所示的半导体器件的截面图;
图18示出了根据实施例在半导体器件上方形成第二聚合物层之后的图17所示的半导体器件的截面图;
图19示出了根据实施例对第二聚合物层的表面实施图案化工艺之后的图18所示的半导体器件的截面图;
图20示出了根据实施例在第二聚合物层的顶部形成UBM晶种层之后的图19所示的半导体器件的截面图;
图21示出了根据实施例在UBM晶种层的顶部形成第二导电层之后的图20所示的半导体器件的截面图;
图22示出了根据实施例在UBM结构上形成互连凸块之后的图21所示的半导体器件的截面图;
图23示出了根据实施例在对衬底的第二侧实施减薄工艺之后的图22所示的半导体器件的截面图;以及
图24示出了根据实施例在衬底的第二侧上形成背部接触件之后的图23所示的半导体器件的截面图。
除非另有说明,否则不同附图中的相应标号和符号通常指的是相应部件。绘制附图以清楚地示出实施例的相关方面而不必按比例绘制。
具体实施方式
下面,详细讨论本实施例的制造和使用。然而,应该理解,本发明提供了许多可以在各种具体环境中实现的可应用的创造性概念。所讨论的具体实施例仅仅示出了制造和使用本发明的实施例的具体方式,而不用于限制本发明的范围。
本发明将参照具体上下文中的实施例来进行描述,即,半导体封装件的通孔结构。然而,本发明的实施例可以应用于半导体工业的各种封装件。下文中,将参照附图详细说明多个实施例。
图1示出了根据实施例的半导体器件的截面图。在衬底102中形成半导体器件100。衬底102具有第一侧101和第二侧103。在衬底102的第一侧101上方形成第一侧互连结构110。在衬底102的第二侧103上方形成第二侧互连结构120。将在下文中参照图2至图24详细描述第一侧互连结构110和第二侧互连结构120。
半导体器件100可以包括多个通孔。为了简便起见,图1中仅示出了一个通孔142。通孔142可以被分成三个部分。底部紧邻衬底102的第二侧103。沿着通孔开口的侧壁形成侧壁部分。更具体地说,如图1所示,通孔142的侧壁部分分别耦合在第一金属化层的底部和金属线184和186之间。
如图1所示,可以具有在衬底102和通孔142的侧壁部分之间所形成的三个薄层122、124和126。根据实施例,薄层122、124和126分别为衬里层、势垒层和晶种层。将在下文中参考图4至图6描述这三个薄层的具体制造工艺。
通孔142可以进一步包括形成在两个侧壁部分之间的中间部分。中间部分可以包括介电材料。更具体地,中间部分的材料可以与第一金属间介电层182的材料相同。下面,将参考图9至图11描述通孔142的具体形成过程。
衬底102可以由硅形成,但是衬底也可以由其他III族、IV族和/或V族元素(诸如,硅、锗、镓、砷以及它们的组合)形成。衬底102也可以是绝缘体上硅(SOI)。SOI衬底可以包括形成在绝缘层(例如,隐埋氧化物等)上方的半导体材料(例如,硅、锗等)层,该绝缘层形成在硅衬底中。此外,可以使用的其他衬底包括多层衬底、梯度衬底、混合定向衬底等。
衬底102可以进一步包括多种电路(未示出)。形成在衬底102上的电路可以是适于特定应用的任何类型的电路。根据实施例,电路可以包括多种n型金属氧化物半导体(NMOS)和/或p型金属氧化物半导体(PMOS)器件,诸如,晶体管、电容器、电阻、二极管、光电二极管、熔丝等。可以互连电路以实施一个或多个功能元件。这些功能可以包括存储结构、处理结构、传感器、放大器、配电器、输入/输出电路等。本领域技术人员将理解的是,上述示例仅用于说明的目的,并不用于将多个实施例限制于任何特定应用中。
层间介电层115形成在衬底102的顶部上。例如,层间介电层115可以由诸如氧化硅的低K介电材料形成。层间介电层115可以通过本领域已知的任何合适的方法形成,诸如,旋涂、化学汽相沉积(CVD)和等离子体增强化学汽相沉积(PEVCD)。也应该注意,本领域技术人员将认识到,虽然图1示出了单个层间介电层,但是层间介电层115可以包括多个介电层。
图1进一步示出了形成在层间介电层115上方的第一金属间介电层182。如图1所示,可以具有形成在第一金属间介电层182中的两条金属线184和186。通孔142耦合至金属线184和186。尤其是,可以在相同的制造步骤中形成通孔142的金属部分和金属线184和186。将在下文中参照图7至图10描述金属线和通孔142的具体形成过程。
应该注意,虽然图1示出了形成在第一金属间介电层182中的金属线184和186,但是本领域技术人员将认识到,可以使用更多的金属间介电层和相关的金属化层以将衬底102中的电路彼此互连为形成功能电路,并且进一步提供外部电连接件。将在下文中参考图2至24描述具有多层金属间介电层和相关的金属化层的半导体器件100的制造工艺。
图2至24示出了根据实施例制造图1所示的通孔的中间步骤。下面描述的制造工艺是基于先通孔制造工艺(via-first fabrication process)。然而,本领域技术人员将认识到,下面描述的先通孔制造工艺仅仅是示例性工艺,并不用于限制各个实施例。也可以可选地使用诸如中间通孔(via-middle)和后通孔(via-last)制造技术的其他通孔制造工艺。总而言之,可以使用任何合适的通孔制造工艺,并且所有这种工艺完全旨在包括在本文所讨论的实施例的范围内。
图2示出根据实施例在衬底中形成多种电路之后的半导体器件。衬底102可以包括多种电路,诸如,金属氧化物半导体(MOS)晶体管(例如,MOS晶体管200)及相关的接触塞(例如,接触塞118)。为了清楚起见,仅示出了单个MOS晶体管和单个接触塞以说明多个实施例的创造性方面。
MOS晶体管200形成在衬底102中。MOS晶体管200包括两个漏极/源极区域106。如图2所示,漏极/源极区域106形成在栅叠层的相对侧上。栅叠层包括形成在衬底102上方的栅极介电层112、形成在栅极介电层112上方的栅电极以及栅极间隔件116。如图2所示,具有形成在MOS晶体管200的相对侧上的两个隔离区104。
隔离区104可以是浅沟槽隔离(STI)区,并且可以通过蚀刻衬底102形成沟槽以及用本领域已知的介电材料来填充沟槽来形成该隔离区104。例如,可以用诸如氧化物材料、高密度等离子体(HDP)氧化物等的介电材料来填充隔离区104。可以对顶面应用诸如CMP工艺的平坦化工艺,从而作为结果可以去除多余的介电材料。
栅极介电层112可以是诸如氧化硅、氮氧化硅、氮化硅、氧化物、含氮氧化物、它们的组合等的介电材料。栅极介电层112可以具有约大于4的相对介电常数值。这种材料的其他实例包括氧化铝、氧化镧、二氧化铪、氧化锆、氮氧化铪、它们的组合等。在栅极介电层112包括氧化物层的实施例中,可以通过使用正硅酸乙酯(TEOS)和氧作为前体的PECVD工艺来形成栅极介电层112。根据实施例,栅极介电层112的厚度可以在约至约的范围内。
栅电极114可以包括导电材料,诸如,金属(例如,钽、钛、钼、钨、铂、铝、铪、钌)、金属硅化物(例如,硅化钛、硅化钴、硅化镍、硅化钽)、金属氮化物(例如,氮化钛、氮化钽)、掺杂多晶硅、其他导电材料、它们的组合等。在栅电极114是多晶硅的实施例中,可以通过低压化学汽相沉积(LPCVD)将掺杂多晶硅或未掺杂多晶硅沉积为厚度在约至约的范围内来形成栅电极114。
可以通过在栅电极114和衬底102上方均匀沉积一层或多层间隔层(未示出)来形成间隔件116。间隔层116可以包括诸如SiN、氮氧化物、SiC、SiON、氧化物等的合适的介电材料。可以通过诸如CVD、PECVD、溅射等通常使用的技术来形成间隔层116。
漏极/源极区域106在衬底102中可以形成在栅极介电层112的相对侧上。在衬底102为n型衬底的实施例中,可以通过注入诸如硼、镓、铟等的合适p型掺杂物来形成源极/漏极区域106。可选地,在衬底102为p型衬底的实施例中,可以通过注入诸如磷、砷等的n型掺杂物来形成源极/漏极区域106。
如图2所示,层间介电层115形成在衬底102上方。在层间介电层115中形成有接触塞118。形成穿过层间介电层115的接触塞118以提供MOS晶体管200和形成在层间介电层115上方的互连结构(未示出,但在图24中示出)之间的电连接件。
可以通过使用光刻技术在层间介电层115上沉积并图案化光刻胶材料来形成接触塞118。根据接触塞118的位置和形状暴露光刻胶的一部分。可以使用诸如各向异性干蚀刻工艺的蚀刻工艺以制造层间介电层115中的开口。
可以在填充接触塞孔之前沉积导电衬里。导电衬里优选为共形的,并且可以包括Ta、TaN、WN、WSi、TiN、Ru层或它们的组合的单层。导电衬里通常可以用作防止诸如铜的导电材料扩散到下面的衬底102中的势垒层。可以通过使用诸如CVD、PVD、原子层沉积(ALD)等的合适沉积工艺来沉积导电衬里。
然后,导电材料被填充到开口中。可以通过使用CVD、PVD或ALD来沉积导电材料。导电材料沉积在导电衬里上方以填充接触塞开口。通过使用诸如CMP的平坦化工艺从层间介电层115的顶面上去除导电材料的多余部分。导电材料可以是铜、钨、铝、银、钛、氮化钛、钽以及它们的组合等。
图3示出了根据实施例在衬底中形成开口之后的图2所示的半导体器件的截面图。通孔开口302可以形成在衬底102的第一侧101中。可以通过涂覆合适的光刻胶层(未示出)并对其进行显影以及去除衬底102暴露期望高度的部分来形成通孔开口302。通孔开口302形成为比形成在衬底102中和/或衬底上的MOS晶体管200更深地延伸到衬底102中。
图4示出根据实施例在在开口的侧壁和底部上形成衬里层之后的图3所示的半导体器件的截面图。一旦在衬底102中形成通孔开口302,通孔开口302的侧壁和底部就可以沉积有衬里层122。可以由诸如TEOS、氮化硅、氧化物、氮氧化硅、低K介电材料、高K介电材料等的合适介电材料形成衬里层122。
可以使用诸如PECVD工艺的合适制造工艺形成衬里层122,但是可选地使用诸如PVD、热处理等的其他合适的工艺。此外,衬里层122可以形成为在约0.1μm至约5μm的范围内的厚度。
图5示出根据实施例在衬里层上方形成势垒层之后的图4所示的半导体器件的截面图。势垒层124可以沉积在衬里层122以及层间介电层115的顶面上。可以由钛、氮化钛、钽、氮化钽、以及它们的组合等形成势垒层124。可以使用诸如ALD、PECVD、等离子体增强物理汽相沉积(PEPVD)等合适的制造技术形成势垒层124。
图6示出根据实施例在势垒层上方形成晶种层之后的图5所示的半导体器件的截面图。可以由铜、镍、金、它们的任何组合等形成晶种层126。可以通过诸如PVD、CVD等合适的沉积技术形成晶种层126。晶种层126的厚度可以在约和约之间。
此外,晶种层126可以与提高晶种层126的粘合性能的材料熔合,从而,其可以用作粘合层。例如,晶种层126可以与诸如锰或铝的材料熔合(alloy),从而诸如锰或铝的材料移动至晶种层126和势垒层124之间的界面并会强化这两层之间的粘合力。可以在形成晶种层126期间引入该合金材料(alloying material)。合金材料可以包括不超过约10%的晶种层。
图7示出根据实施例在晶种层上方形成介电层之后的图6所示的半导体器件的截面图。在晶种层126的顶部上形成介电层702。介电层702可以由光刻胶材料或者非光刻胶材料形成。根据实施例,介电层702可以由常规光刻胶材料形成。可以通过诸如旋涂等合适的制造技术形成介电层702。
图8示出根据实施例在对介电层实施图案化工艺之后的图7所示的半导体器件的截面图。考虑到金属线和通孔的位置,将介电层702的选择区域暴露至光中。因此,去除开口302中的光刻胶材料,并且在晶种层126的顶部上形成多个开口(例如,开口802)。在介电层702中形成诸如开口802的开口包括公知的光刻操作,因此,本文中没有对其进行详细讨论。
图9示出根据实施例在开口中填充导电材料之后的图8所示的半导体器件的截面图。通孔开口以及在晶种层126顶部上的开口(例如,开口802)可以填充有导电材料。导电材料可以包括铜,但是可以可选地使用诸如铝、合金、钨、银、掺杂多晶硅、它们的组合等的其他合适的材料。
如图9所示,通孔开口302部分地填充有导电材料。可以通过电镀工艺将导电材料填充在开口302中。控制电镀工艺,使得通孔的底部的顶面902低于衬底102的顶面904。图9进一步示出在与通孔相同的制造步骤中形成第一金属化层的金属线912、914、和916。
根据实施例,金属线912、914、和916的厚度在约0.5μm至约10μm的范围内。通孔的侧壁的厚度类似于金属线912、914、和916的厚度。通孔的底部的厚度约是金属线912、914、和916的厚度10至50倍。应该注意,可以通过控制电镀工艺来调节通孔底部和金属线之间的厚度比率。
在同一电镀工艺中形成的第一金属化层的金属线和通孔的金属部分的一个有益特征在于,减少了半导体器件的总制造时间。而且,通孔部分地填充有导电材料。这种部分填充结构有助于减少电镀工艺的时间。此外,可以省去传统制造工艺中通常使用的平坦化工艺。因此,改善了半导体器件的成本和制造时间。
上文参照图9描述的制造工艺的另一有益特征在于,部分填充结构有助于解决传统结构的一些共同问题。例如,在先通孔制造工艺中,在互连结构之前形成通孔。在后道工序(BEOL)工艺期间,BEOL工艺的热应力可能导致诸如铜凸出(copper popping)等的可靠性问题。通过采用图9所示的局部填充结构,铜凸出问题不会导致可靠性问题,这是因为通孔并没有完全填充有铜。填充在通孔中的介电材料(未示出)可以用作应力缓冲材料以防止通孔的铜突出。
图10示出根据实施例在去除剩余的光刻胶层之后的图9所示的半导体器件的截面图。可以通过使用诸如化学溶剂清洗、等离子体灰化、干剥离等的合适光刻胶剥离技术来去除图9所示的剩余的光刻胶层。光刻胶剥离技术是众所周知的,因此为了避免重复,本文中没有进行更详细的讨论。
此外,可以通过使用诸如湿蚀刻、干蚀刻等的合适蚀刻工艺来去除在剩余光刻胶层(图9中示出)下面的势垒层和晶种层。干蚀刻工艺或湿蚀刻工艺的具体操作是在本领域众所周知的,因此为了避免重复,本文中没有进行讨论。
图11示出根据实施例在沉积层间介电层之后的图10所示的半导体器件的截面图。金属间介电层182形成在层间介电层115上方。更具体地,通孔的剩余开口(图10所示)通过沉积金属间介电层182而填充有介电材料。金属间介电层182可以由低K介电材料(诸如掺氟硅玻璃(FSG)等)形成。可以通过诸如旋涂等的合适沉积技术形成金属间介电层182。
通孔填充有导电材料和介电材料的组合的一个有益特征在于,中间电介质部分可以用作应力缓冲件。这种应力缓冲件有助于防止通孔在后续的制造步骤期间被热应力和机械应力损坏。
图12示出根据实施例在第一金属化层上方形成两个额外的金属化层之后的图11所示的半导体器件的截面图。如图12所示,两个额外的金属化层形成在第一金属化层上方。虽然图12示出了形成在第一金属化层上方的两个金属化层,但是本领域技术人员会意识到,可以在图12所示的金属化层(例如,层1206和1216)之间形成更多的金属间介电层(未示出)和相关的金属线和插塞(未示出)。具体地,可以通过介电材料(例如,超低k介电材料)和导电材料(例如,铜)的交替层来形成图12所示的金属化层之间的层。
应该注意,通过双镶嵌工艺形成图12所示的金属化层,但是可选地可以使用诸如沉积、单镶嵌的其他合适的技术。双镶嵌工艺是本领域众所周知的,因此,本文中没有进行讨论。
通过双镶嵌工艺形成第二金属线1202和第二插塞1204。第二金属线1202内嵌在类似于第一金属间介电层182的第二金属间介电层1206中。第二插塞1204形成在第一金属间介电层182中。更具体地,第二金属线1202和金属线912通过第二插塞1204彼此耦合。第二金属线1202和插塞1204可以由诸如铜、铜合金、铝、银、金、它们的任意结合等的金属材料形成。第三金属线1212和第三插塞1214分别形成在介电层1216和1208中。第三金属线1212和第三插塞1214类似于第二金属线1202和第二插塞1204,因此,为了避免重复,本文中没有进行讨论。
图13示出根据实施例在金属间介电层的顶部上形成钝化层之后的图12所示的半导体器件的截面图。钝化层154由诸如非掺杂硅玻璃、氮化硅、氧化硅、氮氧化硅、掺硼氧化硅、掺磷氧化硅等的非有机材料形成。可选地,钝化层154可以由诸如掺碳氧化物等的低k介电材料形成。此外,可以使用诸如掺杂多孔碳的二氧化硅的超低k(ELK)电介质形成钝化层154。可以通过诸如CVD的任何合适的技术来形成钝化层154。
如图13所示,在钝化层154中形成开口。开口用于容纳金属焊盘156。如图13所示,金属焊盘156内嵌在钝化层154中。尤其是,金属焊盘156提供金属线(例如,金属线1212)和钝化后互连结构(未示出,但在图24中示出)之间的导电通道。金属焊盘156可以由诸如,铜、铜合金、铝、银、金以及它们的组合的金属材料和/或它们的多层制成。可以通过诸如CVD的适当技术形成金属焊盘156。可选地,金属焊盘156可以通过溅射、电镀等形成。
图14示出根据实施例在钝化层的顶部上形成第一聚合物层之后的图13所示的半导体器件的截面图。第一聚合物层158形成在钝化层154的顶部上。第一聚合物层158可以由诸如环氧树脂、聚酰亚胺、聚苯并恶唑(PBO)、硅树脂、苯并环丁烯(BCB)、模塑料等制成。根据实施例,第一聚合物层158可以由PBO形成。第一聚合物层158可以由诸如旋涂的本领域公知的合适沉积方法制成。
图15示出根据实施例在对第一聚合物层的表面实施图案化工艺之后的图14所示的半导体器件的截面图。可以通过使用诸如蚀刻工艺、激光烧蚀工艺等的合适图案化技术来实施图案化工艺。根据再分布线的形状和位置,可以将蚀刻工艺或激光束(未示出)应用于第一聚合物层158的顶面。因此,去除第一聚合物层158的一部分以形成开口1502。
图16示出根据实施例在第一聚合物层的顶面上形成晶种层之后的图15所示的半导体器件的截面图。晶种层164形成在第一聚合物层158上方。晶种层164可以包括两部分,即,底部晶种层(未示出)和上部晶种层(未示出)。底部晶种层可以是钛层、氮化钛层、钽层、氮化钽层等。上部晶种层可以由铜、铜合金等形成。根据实施例,可以使用诸如CVD、PVD等的任何合适技术形成晶种层164。
图17示出根据实施例在晶种层的顶部上形成再分布线之后的图16所示的半导体器件的截面图。如图17所示,可以在开口(例如图15所示的开口1502)中填充导电材料以形成再分布线166。导电材料可以是铜,但是也可以是诸如铜合金、铝、钨、银、它们的任何组合等的任何合适的导电材料。可以通过诸如非电镀工艺、CVD、电镀等的合适的技术形成再分布线166。
如图17所示,再分布线166连接金属焊盘156。更具体地,半导体器件的再分布线166在金属线(例如,金属线1212)和输入/输出端(例如,图24所示的凸块176)之间提供导电通路。再分布线的操作原理是本领域众所周知的,因此本文中没有详细讨论。
图18示出根据实施例在半导体器件上方形成第二聚合物层之后的图17所示的半导体器件的截面图。第二聚合物层162形成在第一聚合物层158的顶部上。第二聚合物层162由诸如环氧树脂、聚酰亚胺、聚苯并恶唑(PBO)、硅树脂、苯并环丁烯(BCB)、模塑料等的聚合物材料制成。可以使用诸如旋涂的合适的沉积技术在第一聚合物层158上沉积第二聚合物层162。第二聚合物层162的厚度可以在约4μm至约10μm的范围内。
图19示出根据实施例的将图案化工艺应用于第二聚合物层的顶面之后的图18所示的半导体器件的截面图。可以通过使用光刻工艺和蚀刻工艺来实施图案化工艺。可选地,可以通过使用激光烧蚀工艺实施图案化工艺。根据凸块底部金属化(UBM)结构(未示出,但在图24中示出)的形状和位置,蚀刻工艺或激光束可以应用于第二聚合物层162的顶面以形成开口1902。
图20示出根据实施例的在第二聚合物层的顶部上形成UBM晶种层之后的图19所示的半导体器件的截面图。UBM晶种层172沉积在第二聚合物层162上。UBM晶种层172可以包括诸如铜等的导电材料。可以通过使用诸如溅射、CVD等的合适的制造技术来实施UBM晶种层172。
图21示出根据实施例在UBM晶种层的顶部上形成第二导电层之后的图20所示的半导体器件的截面图。如图21所示,为了获得可靠的UBM结构,可以在UBM晶种层172的顶部上以共形方式沉积额外的导电材料,以形成额外的导电层174。导电材料可以是铜,但是也可以是诸如铜合金、铝、钨、银、它们的组合等的任何导电材料。可以通过诸如非电镀工艺的合适技术形成导电层174。
图22示出根据实施例在UBM结构上形成互连凸块之后的图21所示的半导体器件的截面图。互连凸块176提供连接半导体器件与外部电路(未示出)的有效路径。根据实施例,互连凸块176可以是焊球。焊球176可以由任何合适的材料制成。根据实施例,焊球176可以包括SAC 405。SAC405包括95%的Sn、4.0%的Ag和0.5%的Cu。
根据另一个实施例,互连凸块176可以是铜凸块。铜凸块的高度可以是大约45μm。可以通过使用诸如溅射、电镀等的多种半导体封装技术来形成铜凸块。
图23示出根据实施例在减薄工艺应用于衬底的第二侧之后的图22所示的半导体器件的截面图。根据通孔的制造工艺,减薄衬底102的第二侧(也叫背部)变薄直到暴露通孔的导电材料为止。
可以通过诸如研磨、抛光和/或化学蚀刻、蚀刻和研磨技术的结合等的合适的技术来实施减薄工艺。根据实施例,可以使用CMP工艺实施减薄工艺。在CMP工艺中,将蚀刻材料和研磨材料的混合物与衬底的背部接触,研磨垫(未示出)用于研磨掉衬底102的背部直到暴露通孔的导电材料为止。
图24示出根据实施例在衬底的第二侧上形成背部接触件之后的图23所示的半导体器件的截面图。可以采用清洗工艺去除任何剩余残渣,诸如,衬底102的背部上的氧化铜,可以在衬底102的第二侧上形成与位于通孔中的导电材料电接触的背部接触件2402。
背部接触件2402可以包括导电层(未示出)和非电镀镍/浸金(electro-less nickel immersion gold,ENIG)层(未示出)。导电层可以包括铝并可以通过溅射沉积工艺形成。然而,可以可选地使用诸如镍、铜等的其他材料。此外,可以可选地采用诸如电镀或非电镀的其他形成工艺形成导电层。形成的导电层的厚度可以介于约0.5μm和约3μm之间。
形成导电层之后实施ENIG工艺以形成ENIG层。ENIG工艺可以包括清洗导电层、将衬底102浸入锌酸盐活化液(zincate activation solution)中、在导电层之上非电镀镍以及在镍之上非电镀金。
可选地,导电层形成之后实施类似于ENIG层的其他导电层。例如,导电层可以是非电镀镍非电镀钯浸金(electro-less nickel electro-lesspalladium immersion gold,ENEPIG)层,从而包括镍层、镍层上的钯层以及钯层上的金层。而且,ENIG或ENEPIG层可以由其他相似的导电层代替,诸如,非电镀镍非电镀钯(ENEP)层、直接浸金(DIG)层等。
背部钝化层2404可以部分地形成在背部接触件2402上方,从而密封并保护背部接触件2402。背部钝化层2404可以包括诸如氧化物或氮化硅的介电材料,但是可以可选地使用诸如高k电介质的其他合适的电介质。
可以使用PECVD工艺来形成背部钝化层2404,但是可以可选地使用任何其他合适的工艺。一旦背部钝化层2404沉积在衬底的第二侧上,为了至少暴露背部接触件2402的一部分,可以将图案化工艺应用于背部钝化层2404。将合适的蚀刻技术应用于背部钝化层2404,从而暴露背部接触件2402。因此,外部器件(未示出)可以连接到背部接触件2402。
尽管已经详细地描述了本发明及其优势,但应该理解,可以在不背离所附权利要求限定的本发明主旨和范围的情况下,做各种不同的改变、替换和更改。
而且,本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解,通过本发明,现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造,材料组分、装置、方法或步骤根据本发明可以被使用。因此,所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。
Claims (10)
1.一种装置,包括:
层间介电层,形成在衬底的第一侧上;
第一金属化层,形成在所述层间介电层上方,所述第一金属化层包括形成在第一金属间介电材料中的多条金属线;以及
通孔,形成在所述衬底中,所述通孔包括:
底部,由导电材料形成,并且所述底部紧邻所述衬底的第二侧;
侧壁部,由所述导电材料形成,所述侧壁部的第一端耦合至所述底部且所述侧壁部的第二端耦合至所述第一金属化层的金属线;和
中部,形成在所述侧壁部之间,并且所述中部由介电材料形成。
2.根据权利要求1所述的装置,其中,所述通孔包括:
衬里层,形成在通孔沟槽的侧壁上;
势垒层,形成在所述衬里层上;以及
晶种层,形成在所述势垒层上。
3.根据权利要求1所述的装置,其中,所述中部的底面低于所述衬底的顶面。
4.根据权利要求1所述的装置,其中,所述中部由所述第一金属间介电材料形成。
5.根据权利要求4所述的装置,其中,所述第一金属间介电材料是感光聚合物材料。
6.根据权利要求1所述的装置,进一步包括:
第一侧互连结构,形成在所述第一金属化层上方;以及
第二侧互连结构,形成在所述衬底的所述第二侧上方,其中,所述第二侧互连结构耦合至所述通孔。
7.根据权利要求1所述的装置,其中,所述导电材料是铜。
8.一种方法,包括:
在所述衬底的第一侧上方形成层间介电层;
在所述衬底中形成开口;
用导电材料填充所述开口,其中,所述开口的上部没有所述导电材料;以及
在所述衬底上方沉积介电材料,其中,所述介电材料被填充在所述开口的上部中。
9.根据权利要求8所述的方法,进一步包括:
在所述开口的侧壁和底部上形成衬里层;
在所述衬里层上方形成势垒层;
在所述势垒层上方形成晶种层;
沉积所述晶种层的光刻胶层;
图案化所述光刻胶层;以及
对所述晶种层应用喷镀工艺。
10.一种方法,包括:
在衬底中自所述衬底的第一侧形成开口;
在所述开口的侧壁和底部上沉积衬里层;
在所述衬里层上方沉积势垒层;
在所述势垒层上方沉积晶种层;
在所述晶种层上方形成光刻胶层;
图案化所述光刻胶层,从而:
去除所述开口中的所述光刻胶层;以及
去除所述衬底上的所述光刻胶层的部分,以在所述光刻胶层中形成互连沟槽;
使用电化学镀工艺用导电材料填充所述开口,所述开口的上部没有所述导电材料;
使用所述电化学镀工艺用所述导电材料将所述互连沟槽填充至第一金属线;以及
在所述开口和所述互连沟槽上方沉积介电材料,其中,所述开口的所述上部填充有所述介电材料。
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US6645851B1 (en) * | 2002-09-17 | 2003-11-11 | Taiwan Semiconductor Manufacturing Company | Method of forming planarized coatings on contact hole patterns of various duty ratios |
JP4093186B2 (ja) * | 2004-01-27 | 2008-06-04 | カシオ計算機株式会社 | 半導体装置の製造方法 |
US7833895B2 (en) * | 2008-05-12 | 2010-11-16 | Texas Instruments Incorporated | TSVS having chemically exposed TSV tips for integrated circuit devices |
US9112007B2 (en) | 2012-09-14 | 2015-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through via structure and method |
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US20070228576A1 (en) * | 2005-06-14 | 2007-10-04 | John Trezza | Isolating chip-to-chip contact |
US20110200937A1 (en) * | 2008-10-20 | 2011-08-18 | Sumitomo Bakelite Co., Ltd. | Positive photosensitive resin composition for spray coating and method for producing through electrode using the same |
CN102299136A (zh) * | 2010-06-28 | 2011-12-28 | 三星电子株式会社 | 半导体器件及其制造方法 |
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CN106601624A (zh) * | 2016-12-02 | 2017-04-26 | 厦门市三安集成电路有限公司 | 一种化合物半导体的金属连线方法及结构 |
CN106601624B (zh) * | 2016-12-02 | 2019-04-09 | 厦门市三安集成电路有限公司 | 一种化合物半导体的金属连线方法及结构 |
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US9112007B2 (en) | 2015-08-18 |
US11756883B2 (en) | 2023-09-12 |
US20200343176A1 (en) | 2020-10-29 |
US20180145022A1 (en) | 2018-05-24 |
US20140077374A1 (en) | 2014-03-20 |
DE102013103206A1 (de) | 2014-03-20 |
US10714423B2 (en) | 2020-07-14 |
DE102013103206B4 (de) | 2020-06-18 |
US9831177B2 (en) | 2017-11-28 |
US20150357263A1 (en) | 2015-12-10 |
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