CN102820257B - 硅通孔结构和方法 - Google Patents

硅通孔结构和方法 Download PDF

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Publication number
CN102820257B
CN102820257B CN201110446671.7A CN201110446671A CN102820257B CN 102820257 B CN102820257 B CN 102820257B CN 201110446671 A CN201110446671 A CN 201110446671A CN 102820257 B CN102820257 B CN 102820257B
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Prior art keywords
passivation layer
lining
electric conducting
conducting material
silicon
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CN102820257A (zh
Inventor
余振华
郑心圃
邱文智
蔡方文
蔡承佑
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明涉及硅通孔结构和方法，公开了用于制造硅通孔的系统和方法。一个实施例包括：形成具有从衬底突出的衬里的硅通孔。钝化层形成在衬底和硅通孔的上方，并且钝化层和衬里从硅通孔的侧壁开始凹陷。然后，导电材料可以形成为与硅通孔的侧壁和顶面接触。

Description

硅通孔结构和方法
技术领域
本发明涉及半导体领域，具体地，涉及硅通孔结构和方法。
背景技术
通常，可以在半导体衬底中形成硅通孔来为半导体衬底的背侧提供电连接。通过提供这种电连接，在如前一代半导体工艺中仅位于半导体衬底单侧的电连接之外，可以扩展连接半导体衬底的可能性。此外，这种扩展允许半导体管芯的三维堆叠，其通过硅通孔进行连接并贯穿三维堆叠提供电源、地和信号线。
为了形成硅通孔，可以在半导体衬底的有源侧形成开口，其中，开口与位于半导体衬底中或上的有源器件相比更加深得延伸到半导体衬底中。然后，这些开口可以填充到导电材料。在开口被填充之后，通过例如化学机械抛光(CMP)或蚀刻工艺，可以将半导体衬底的背侧减薄，以露出导电材料，从而在导电材料与周围材料之间留下平面。然后，可以在平面的上方形成导电粘合层，以在硅通孔与将被形成的接触之间提供接口。
然而，硅通孔与接触相比相对较小的尺寸会引起非均匀电流分布，已知为在硅通孔与粘合层之间的接口处发生电流拥挤。除本身的问题之外，该电流拥挤还会引发电磁故障并引起结构内突出物和孔洞的形成。
发明内容
为解决上述问题，本发明提供了一种方法，包括：在衬底中形成硅通孔，硅通孔具有被衬里覆盖的侧壁；在衬底和衬里的上方共形地形成钝化层；使钝化层和衬里凹陷，以露出硅通孔的侧壁；以及与硅通孔的侧壁接触地形成导电材料。
其中，在相同的步骤中执行钝化层和衬里的凹陷。
其中，使钝化层和衬里凹陷还包括：使钝化层凹陷；以及使衬里凹陷，其中，在与使钝化层凹陷的步骤独立的步骤中执行衬里的凹陷。
其中，形成导电材料还包括：形成再分布层。
其中，衬里包括第一材料，以及钝化层包括第一材料。
其中，第一材料为氮化硅。
其中，形成导电材料还包括：形成胶粘层。
其中，胶粘层为钛。
其中，钝化层包括氮化硅、碳化硅、氮氧化硅、氧化硅或聚合物中的一种。
此外，本发明提供了一种方法，包括：在半导体衬底的第一侧的开口中形成衬里；使用第一导电材料填充开口；减薄半导体衬底的第二侧以露出衬里；使半导体衬底凹陷以便第一导电材料从半导体衬底的第二侧突出；在第一导电材料和半导体衬底的第二侧的上方形成钝化层，钝化层具有与第二侧相邻并接触的第一部分以及位于第一部分的上方并沿着第一导电材料的侧壁延伸的第二部分；使钝化层的第一部分和衬里凹陷，以露出第一导电材料的侧壁；以及与第一导电材料的顶面和侧壁物理接触地形成第二导电材料。
其中，形成第二导电材料还包括：形成胶粘层；形成晶种层；以及形成再分布层。
其中，形成第二导电材料还包括：形成接触焊盘。
其中，钝化层包括第一材料，并且衬里包括第一材料。
其中，形成第二导电材料还包括：在钝化层、衬里和第一导电材料的上方形成钛层。
此外，本发明提供了一种半导体器件，包括：硅通孔，从衬底突出，硅通孔具有侧壁；衬里，沿着远离衬里的侧壁延伸，衬里在到达硅通孔的顶面之前终止；钝化层，包括远离衬底第一距离的第一上表面和远离衬底第二距离的第二上表面，第二距离大于第一距离，并且第二上表面与衬里相邻；以及导电材料，位于硅通孔的侧壁和顶面的上方并与硅通孔的侧壁和顶面物理接触。
其中，导电材料还包括：胶粘层；以及再分布层。
其中，导电材料包括钛。
其中，钝化层和衬里均包括第一材料。
其中，第一材料包括氮化硅。
其中，钝化层包括组合层。
附图说明
为了更加完整地理解本发明的实施例及其优点，现在结合附图进行以下描述，其中：
图1示出了根据实施例的具有附接至载体的导电开口的半导体衬底；
图2示出了根据实施例的半导体衬底的第二侧的减薄；
图3示出了根据实施例的在硅通孔的上方形成钝化层；
图4示出了根据实施例的钝化层的平面化；
图5示出了根据实施例的钝化层和衬里的开槽；
图6示出了根据实施例的粘合层的形成；
图7示出了根据实施例的晶种层、接触焊盘和再分布层的形成；
图8示出了根据实施例的硅通孔与粘合层之间的接口的全貌图；以及
图9示出了根据实施例的半导体管芯与第一外部器件和第二外部器件的结合。
除非另有指定，不同附图中对应的标号和符合通常是指对应的部件。附图清楚示出了实施例的相对方面，并且并不需要按比例绘制。
具体实施方式
以下详细讨论本发明实施例的制造和用法。然而，应该理解，本公开提供了许多可以在各种特定环境下具体化的可应用新概念。所讨论的具体实施例仅仅示出了制造和使用所公开概念的特定方式，而不用于限制。
在特定环境，即，硅通孔中描述了实施例。然而，这些实施例还可以应用于其他导电接触。
现在，参照图1，示出了具有半导体衬底101的半导体管芯100，其中，半导体衬底101具有第一侧102和第二侧104。半导体衬底101的第一侧102可以具有形成在其中的TSV开口111和有源器件103、金属层105以及形成在其中和其上的第一导电凸起107。半导体衬底101可包括体硅(bulksilicon)、或者绝缘体上硅(SOI)衬底的掺杂或未掺杂的有源层。通常，SOI衬底包括半导体材料层，诸如硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)或者它们的组合。可使用的其他衬底包括多层衬底、梯度衬底或混合取向衬底。
硅通孔(TSV)开口111可形成在半导体衬底101的第一侧102中。可通过涂覆和显影适当的光刻胶(未示出)并去除暴露为期望深度的半导体衬底101来形成TSV开口111。TSV开口111可形成为延伸到半导体衬底101中，至少比形成在半导体衬底101中和/或上的有源器件103深，并且可以延伸到大于半导体衬底101的最终预期高度的深度。因此，虽然深度依赖于半导体管芯100的总体设计，但深度可以在从半导体衬底101的有源器件103开始的大约20μm和大约200μm之间，诸如从半导体衬底101的有源器件103开始的大约100μm的深度。
一旦TSV开口111形成在半导体衬底101内，TSV开口111就可以加衬有衬里113。例如，衬里113可以为由正硅酸乙酯(TEOS)形成的氧化物或氮化硅，尽管可选地可以使用任何适当的电介质材料。可以使用等离子体增强化学气相沉积(PECVD)工艺来形成衬里113，尽管可以可选地使用诸如物理气相沉积或热工艺的其他适当工艺。此外，衬里113可以形成为大约0.1μm和大约5之间的厚度，诸如大约1μm。
一旦沿着TSV开口111的侧壁和底部形成衬里113，就可以形成阻挡层(未示出)并且可以用第一导电材料115填充TSV开口111的剩余部分。第一导电材料115可包括铜，尽管可以可选地使用其他适当材料，诸如铝、合金、掺杂多晶硅、它们的组合等。可以通过将铜电镀到晶种层(未示出)上、填充并溢出TSV开口111来形成第一导电材料115。一旦填充了TSV开口111，就可以通过诸如化学机械抛光(CMP)的平面化工艺来去除TSV开口111外部的过量衬底113、阻挡层、晶种层和第一导电材料115，尽管还可以使用任何适当的去除工艺。
有源器件103在图1中被示为单个晶体管。然而，本领域的技术人员应该意识到，可以使用各种有源器件(诸如电容器、电阻器、电感器等)来生成用于半导体管芯100的设计的期望结构和功能要求。有源器件103可以使用任何适当的方法来形成在半导体衬底101的第一侧102内或其上。
金属层105形成在半导体衬底101的第一侧102和有源器件103的上方，并且被设计为连接各种有源器件103来形成功能电路。虽然在图1中示为单层的电介质和互连，但金属层105可以由电介质和导电材料的交替层来形成，并且可以通过任何适当的工艺(诸如沉积、镶嵌、双重镶嵌等)来形成。在一个实施例中，其可以为通过至少一个层间电介质层(ILD)与半导体衬底101隔离的四层金属层，但是金属层105的精确数目依赖于半导体管芯100的设计。
图1还示出了半导体衬底101的第一层102上的第一导电凸起107的形成。第一导电凸起107可包括诸如锡的材料或者诸如银或铜的其他适当材料。在第一导电凸起107为锡焊料凸起的实施例中，可初始地通过诸如蒸镀、电镀、印刷、移焊、焊球放置等的这些通用方法将锡层形成为例如大约10μm至大约100μm的厚度来形成第一导电凸起107。一旦锡层形成在结构上，就可以执行回流以将材料成形为期望的凸起形状。
一旦对半导体衬底101的第一侧102执行的工艺达到在半导体衬底101的第二侧104上发生的用于处理的适当点，载体117就可以利用粘合剂119附接至半导体管芯100。例如，载体117可包括玻璃、氧化硅、氧化铝等。在一个实施例中，粘合剂119可用于将载体117粘附至半导体管芯100。粘合剂119可以为任何适当的粘合剂，诸如紫外线(UV)胶，其中暴露给UV光时失去它的粘性。载体可具有大于约12密尔的厚度。
可选地，载体117可包括适当的载体带。如果利用载体带，载体带可以为通常已知的蓝膜。载体带可以使用位于载体带上的第二粘合剂(未示出)附接至半导体管芯100。
图2示出了半导体衬底101的第二侧104的减薄以露出TSV开口111(参见上面讨论的图1)并利用延伸穿过半导体衬底101的第一导电材料115形成TSV 201。在一个实施例中，半导体衬底101的第二侧104的减薄可以留下由衬里113加衬的TSV 201。可通过CMP和蚀刻的组合来执行半导体衬底101的第二侧104的减薄。例如，可以执行CMP工艺以去除块状的半导体衬底101。一旦去除了块状的半导体衬底101的第二侧104，然后就可以采用蚀刻工艺来使半导体衬底101的第二侧104凹陷并使得TSV201从半导体衬底101的第二侧104突出。在一个实施例中，TSV 201可以从半导体衬底101的第二侧104突出大约0.5μm与大约10μm之间的距离，诸如大约5μm。
本领域的技术人员应该意识到，用于形成TSV 201的上述工艺仅仅是形成TSV 201的一种方法，其他方法也可以完全包括在实施例的范围内。例如，还可以使用形成TSV开口111、用电介质材料填充TSV开口111、减薄半导体衬底101的第二侧104以露出电介质材料、去除电介质材料以及在使半导体衬底101的第二侧104凹陷之前利用导体填充TSV开口111。用于将TSV 201形成在半导体衬底101的第一侧102中的该方法以及所有其他适当方法均旨在完全包含在实施例的范围内。
可选地，TSV 201可以被形成为延伸通过金属层105。例如，可以在形成金属层105之后或者甚至部分地与金属层105同时形成TSV 201。例如，TSV开口111可以在单个工艺步骤中形成为穿过金属层105和半导体衬底101。可选地，在形成金属层105之前，可以在半导体衬底101内形成并填充一部分TSV开口111，并且随着分别形成每个金属层105来形成并填充TSV开口111的后续层。任何这些工艺以及可用于形成TSV 201的任何其他适当工艺都完全包括在实施例的范围内。
图3示出了半导体衬底101的第二侧104之上以及从半导体衬底101的第二侧104突出的TSV 201和衬里113之上的第一钝化层301的形成。第一钝化层301可以为类似于衬里113的电介质材料(诸如氮化硅)，但是可选地可以为诸如碳化硅、氮氧化硅、氧化硅、聚合材料、它们的组合等的不同材料。此外，第一钝化层301可以为材料的单层或者可以为具有不同材料的多个子层的组合层。可以使用PECVD工艺形成第一钝化层301，尽管还可以可选地使用任何其他适当的工艺。
第一钝化层301可以共形地(comformally)形成在半导体衬底101的第二侧104和TSV 201的上方，并且可以形成为具有大约0.1μm与大约5μm之间的厚度，诸如大约1μm。通过相似地形成第一钝化层301，第一钝化层301可以具有两个上表面，顶部上表面303位于TSV 201的顶部上方，以及底部上表面305位于TSV 201的顶部下方。
图4示出了一旦形成了第一钝化层301就对第一钝化层301、衬里113和第一导电材料115进行平面化以露出TSV 201内的第一导电材料115。例如，可通过CMP工艺或其他适当的平面化工艺来执行平面化，并且至少可以在通过第一钝化层301以及衬里113露出TSV 201的第一导电材料115之后继续。此外，可以停止平面化工艺以维持第一钝化层301的顶部上表面303和底部上表面305的分离。如此，第一钝化层301沿着TSV 201和衬里113的侧壁保持第一钝化层301的一部分。
图5示出了第一钝化层301和衬里113从TSV 201的侧壁开始的凹陷。在第一钝化层301和衬里113为诸如氮化硅的类似材料的实施例中，第一钝化层301和衬里113可以通过例如使用蚀刻剂(诸如CxFy或HF，其对氮化硅具有选择性并且将不会从TSV 201中显著去除第一导电材料115)湿式或干式蚀刻来同时去除。
第一钝化层301和衬里113的凹陷可以继续，直到TSV 201的侧壁从第一钝化层301突出大约0.1μm与大约5μm之间(诸如大约1μm)。然而，可以在从TSV 201的侧壁完全去除第一钝化层301和衬里113之前停止凹陷。如此，会在第一钝化层301的底部上表面305、顶部上表面303和衬里113以及TSV 201的顶面之间形成楼梯台阶图样。
在第一钝化层301和衬里113为类似材料(诸如具有类似蚀刻选择性的材料)的实施例中，第一钝化层301和衬里113可以在单个工艺步骤中凹陷。可选地，如果第一钝化层301和衬里113为不同材料，或者甚至期望独立的工艺步骤，则可以在一个工艺步骤中使第一钝化层301凹陷，以及在与其独立的工艺步骤中使衬里113凹陷。如此，第一钝化层301可以比衬里113凹陷的多或少，例如，TSV 201可以从衬里113突出大约0.1μm至大约5μm的距离(诸如大约2μm)，以及可以从第一钝化层301突出大约0.1μm至大约5μm的距离(诸如大约2μm)。可以可选地使用用于使第一钝化层301和衬里113凹陷的工艺步骤任何适当的组合，并且所有这些组合都完全包括在实施例内。
图6示出了粘合层601在第一钝化层301、衬里113和TSV 201之上的形成。粘合层601帮助将第一钝化层301、衬里113和TSV 201粘附至随后形成的材料(诸如晶种层，其在图6中未示出但是以下参照图7示出并进行讨论)。粘合层601可以为钛、氮化钛、钽、氮化钽、它们的组合等，并且可以通过诸如CVD的工艺来形成，尽管还可以任选地使用任何适当的工艺。此外，粘合层601可以被形成为大约和大约之间的厚度，诸如大约
图7示出了晶种层701、接触焊盘703和再分布层705的形成。晶种层701可用作用于进一步沉积材料以形成接触焊盘703和再分布层705的引发剂(initiator)。晶种层701可通过PVD、CVD、溅射等来沉积，并且可以由铜、镍、金、钛、铜合金、它们的组合等来形成，尽管可以可选地根据预期来使用其他方法和材料。此外，晶种层701可具有大约和大约之间的厚度。
一旦形成了晶种层701，就可以形成光刻胶(未示出)来覆盖晶种层701，并且可以对光刻胶进行图样化以露出晶种层701中位于预期接触焊盘703和再分布层705的那些部分。例如，光刻胶可以被图样化以在一个TSV201的上方形成接触焊盘703的形状，同时光刻胶还可以在其他两个TSV201的上方被图样化以提供再分布层705来连接两个TSV 201。
在光刻胶被图样化之后，可以在晶种层701上镀上第二导电材料707以形成接触焊盘703和再分布层705。第二导电材料707可包括铜，尽管可以可选地利用诸如铝、合金、掺杂多晶硅、它们的组合等的其他适当材料。第二导电材料707可以形成为大约1μm和大约10μm之间的厚度(诸如大约3μm)，并且可以通过将铜电镀到图样化的晶种层701上来形成，尽管还可以可选地利用用于形成第二导电材料707的任何适当的可选工艺。
一旦形成了第二导电材料707，就可以通过诸如灰化的适当去除工艺来去除光刻胶。此外，在去除光刻胶之后，例如可以通过将第二导电材料707用作掩模的适当蚀刻工艺来去除晶种层701被光刻胶覆盖的那些部分。
图8示出了图7中的区域801的特写，并部分示出了一个TSV 201与再分布层705之间的接口区域的特写。从图中可以看出，通过部分地使衬里113和第一钝化层301从TSV 201的侧壁开始凹陷，在除了只有TSV 201的顶面之外，增加了TSV 201与粘合层601之间的接口的表面积。通过增加接口的表面积，可以减小TSV 201与再分布层705(和其他接触)之间的电流拥挤问题，从而在减少形成孔洞和突出物的同时提供更加有效的系统。
图9示出了半导体管芯100内的TSV 201以例如堆叠结构与第一外部器件901和第二外部器件902接触的放置。在一个实施例中，第二钝化层911可以形成在第一钝化层301的上方以及形成在接触焊盘703和再分布层705的上方。第二钝化层911可以与第一钝化层301类似，诸如为通过PECVD工艺形成的氮化硅层。然而，第二钝化层911可以可选地为其他材料(诸如碳化硅、氮氧化硅、氧化硅、聚合材料、它们的组合等)以及可以通过任何适当的工艺来形成。此外，第二钝化层911可以被形成为大约0.1μm和大约5μm之间的厚度，诸如大约1μm。
一旦被形成，第二钝化层911就可以被图样化以露出接触焊盘703和再分布层705。可以使用光刻掩模和蚀刻工艺来执行第二钝化层911的图样化，从而在第二钝化层911的上方形成光刻胶(未示出)并露出为期望图样。在曝光之后，光刻胶被显影以去除第二钝化层911的预期部分，并露出接触焊盘703和再分布层705的下部。
一旦露出了接触焊盘703和再分布层705的预期部分，就可以形成第二导电凸起913以建立与接触焊盘703和再分布层705的电连接。可以以与第一导电凸起107(上面参照图1进行讨论)类似的方法和类似的材料来形成第二导电凸起913。然而，第二导电凸起913可以可选地利用与第一导电凸起107不同的工艺或材料来形成。
例如，第一外部器件901可以为印刷电路板、半导体封装衬底或者如图9所示为具有第二衬底903、第二有源器件905、第二金属层907和第三导电凸起909的第二半导体管芯。然而，第一外部器件901并不限于任何本文所列的器件，而是可以可选地为适合于与半导体管芯100接触的任何器件。
类似于第一外部器件901，例如，第二外部器件902也可以为第三半导体管芯、半导体封装衬底或者如图9所示为印刷电路板。然而，第二外部器件902并不限于任何本文所列的器件，而是可以可选地为适合于与半导体管芯100接触的任何器件。
在图9所示的实施例中，半导体管芯100可以例如以堆叠的倒装芯片结构连接至第一外部器件901和第二外部器件902。在该实施例中，半导体管芯100被定位为使得第二导电凸起913与第三导电区域909物理接触，并且被定位为使得第一导电凸起107与第二外部器件902物理接触。一旦被定位，第一导电凸起107、第二导电凸起913和第三导电凸起909就被加热并且施加压力以液化第一导电凸起107、第二导电凸起913和第三导电凸起909，并将第三导电凸起909结合至第二导电凸起913以及将第一导电凸起107结合至第二外部器件902。这种回流帮助建立半导体管芯100的第二导电凸起913与第一外部器件901的第三导电凸起909之间的电接触以及建立第一导电凸起107与第二外部器件902之间的另一电接触。
根据一个实施例，提供了一种方法，包括：在衬底中形成硅通孔，硅通孔具有被衬里覆盖的侧壁。在衬底上方和衬里上方相似地形成钝化层，并且使钝化层和衬里凹陷以露出硅通孔的侧壁。与硅通孔的侧壁接触地形成导电材料。
根据另一个实施例，提供了一种方法，包括：在半导体衬底的第一侧的开口中形成衬里；以及利用第一导电材料填充开口。半导体衬底的第二侧被减薄以露出衬里，并且半导体衬底凹陷使得第一导电材料从半导体衬底的第二侧突出。在半导体衬底的第二侧和第一导电材料的上方形成钝化层，钝化层具有与第二侧相邻并接触的第一部分和在第一部分之上并沿着第一导电材料的侧壁延伸的第二部分。使钝化层的第一部分和衬里凹陷以露出第一导电材料的侧壁，并且第二导电材料被形成为与第一导电材料的侧壁和顶面物理接触。
根据又一实施例，提供了一种半导体器件，包括从衬底突出的硅通孔，硅通孔具有侧壁。衬里沿着远离衬底的侧壁延伸，衬里在到达硅通孔的顶面之前终止。钝化层包括远离衬底第一距离的第一上表面和远离衬底第二距离的第二上表面，第二距离大于第一距离，第二上表面与衬里相邻。导电材料在硅通孔的侧壁和顶面的上方并与硅通孔的侧壁和顶面物理接触。
尽管详细描述了实施例及其优点，但应该理解，在不背离实施例的精神和范围的情况下可以进行各种改变、替换和变化。例如，可以改变用于形成硅通孔的精确方法和材料，而仍然在实施例的范围之内。此外，组合层可用于钝化层或衬里，也仍然在实施例的范围之内。
此外，本申请的范围不限于说明书中描述的处理、机器、制造、物质组成、装置、方法和步骤的特定实施例。如本领域的技术人员可以从本发明实施例的公开所容易理解的，可以根据本公开利用现有或稍后开发的执行与本文所描述对应实施例基本相同的功能并实现基本相同结果的处理、机器、制造、物质组成、装置、方法或步骤。因此，所附权利要求用于在它们的范围内包括这些处理、机器、制造、物质组成、装置、方法或步骤。

Claims (20)

1.一种制造半导体器件的方法，包括：
在衬底中形成硅通孔，所述硅通孔具有被衬里覆盖的侧壁；
在所述衬底和所述衬里的上方共形地形成钝化层；
使所述钝化层和所述衬里凹陷，以露出所述硅通孔的侧壁，所述钝化层在凹陷所述钝化层和所述衬里之后具有两个不同的厚度；以及
与所述硅通孔的侧壁接触地形成导电材料。
2.根据权利要求1所述的方法，其中，在相同的步骤中执行所述钝化层和所述衬里的凹陷。
3.根据权利要求1所述的方法，其中，使所述钝化层和所述衬里凹陷还包括：
使所述钝化层凹陷；以及
使所述衬里凹陷，其中，在与使所述钝化层凹陷的步骤独立的步骤中执行所述衬里的凹陷。
4.根据权利要求1所述的方法，其中，形成导电材料还包括：形成再分布层。
5.根据权利要求1所述的方法，其中，所述衬里包括第一材料，以及所述钝化层包括所述第一材料。
6.根据权利要求5所述的方法，其中，所述第一材料为氮化硅。
7.根据权利要求1所述的方法，其中，形成所述导电材料还包括：形成胶粘层。
8.根据权利要求7所述的方法，其中，所述胶粘层为钛。
9.根据权利要求1所述的方法，其中，所述钝化层包括氮化硅、碳化硅、氮氧化硅、氧化硅或聚合物中的一种。
10.一种制造半导体器件的方法，包括：
在半导体衬底的第一侧的开口中形成衬里；
使用第一导电材料填充所述开口；
减薄所述半导体衬底的第二侧以露出所述衬里；
使所述半导体衬底凹陷以便所述第一导电材料从所述半导体衬底的所述第二侧突出；
在所述第一导电材料和所述半导体衬底的所述第二侧的上方形成钝化层，所述钝化层具有与所述第二侧相邻并接触的第一部分以及位于所述第一部分的上方并沿着所述第一导电材料的侧壁延伸的第二部分；
使所述钝化层的所述第一部分和所述衬里凹陷，以露出所述第一导电材料的侧壁，所述钝化层在凹陷所述钝化层和所述衬里之后具有两个不同的厚度；以及
与所述第一导电材料的顶面和侧壁物理接触地形成第二导电材料。
11.根据权利要求10所述的方法，其中，形成所述第二导电材料还包括：
形成胶粘层；
形成晶种层；以及
形成再分布层。
12.根据权利要求10所述的方法，其中，形成所述第二导电材料还包括：形成接触焊盘。
13.根据权利要求10所述的方法，其中，所述钝化层包括第一材料，并且所述衬里包括所述第一材料。
14.根据权利要求10所述的方法，其中，形成所述第二导电材料还包括：在所述钝化层、所述衬里和所述第一导电材料的上方形成钛层。
15.一种半导体器件，包括：
硅通孔，从衬底突出，所述硅通孔具有侧壁；
衬里，沿着远离所述衬底的侧壁延伸，所述衬里在到达所述硅通孔的顶面之前终止；
钝化层，包括远离所述衬底第一距离的第一上表面和远离所述衬底第二距离的第二上表面，所述第二距离大于所述第一距离，并且所述第二上表面与所述衬里相邻，所述第二上表面比所述硅通孔的顶面更接近所述衬底；以及
导电材料，位于所述硅通孔的所述侧壁和所述顶面的上方并与所述硅通孔的所述侧壁和所述顶面物理接触。
16.根据权利要求15所述的半导体器件，其中，所述导电材料还包括：
胶粘层；以及
再分布层。
17.根据权利要求15所述的半导体器件，其中，所述导电材料包括钛。
18.根据权利要求15所述的半导体器件，其中，所述钝化层和所述衬里均包括第一材料。
19.根据权利要求18所述的半导体器件，其中，所述第一材料包括氮化硅。
20.根据权利要求15所述的半导体器件，其中，所述钝化层包括组合层。
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