TWI450376B - 具有對準標記的結構及堆疊裝置的製造方法 - Google Patents

具有對準標記的結構及堆疊裝置的製造方法 Download PDF

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TWI450376B
TWI450376B TW099140503A TW99140503A TWI450376B TW I450376 B TWI450376 B TW I450376B TW 099140503 A TW099140503 A TW 099140503A TW 99140503 A TW99140503 A TW 99140503A TW I450376 B TWI450376 B TW I450376B
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substrate
layer
recess
isolation layer
isolation
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Chen Yu Tsai
Shih Hui Wang
Chien Ming Chiu
Chia Ho Chen
Fang Wen Tsai
Weng Jin Wu
Jing Cheng Lin
Wen Chih Chiou
Shin Puu Jeng
Chen Hua Yu
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Taiwan Semiconductor Mfg
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Description

具有對準標記的結構及堆疊裝置的製造方法
本發明係有關於一種半導體製程及其所形成的結構，特別是有關於一種對準標記(alignment mark)製造方法及其所形成的結構。
在半導體製程中，結構及裝置的製造通常包括依序將一層材料或材料組成形成於另一層上方。這些膜層通常利用微影技術進行蝕刻或摻雜，以控制這些被蝕刻或摻雜的區域。舉例來說，電晶體的源極/汲極的製做可包括在半導體基底上形成一光阻層，其中形成了源極/汲極區。對光阻層進行曝光，使得位於源極/汲極區上方的光阻層被除去。利用光阻層對半導體層進行摻雜，以防止未曝光區受到摻雜。再者，源極/汲極區的接觸窗(contact)可包括：在半導體基底上沉積絕緣層；在絕緣層上形成光阻層；對光阻層進行曝光，以去除位於源極/汲極區上方的光阻層；利用光阻層作為罩幕，以蝕刻絕緣層；以及沉積金屬。
整合利用微影技術形成的裝置係取決於從一層到另一層中特徵部件(features)可適當的對準，在上述範例中，接觸窗必須對準於源極/汲極區。膜層之間的誤對準(misalignment)會阻礙裝置的操作。
半導體製程領域中已發展出對準標記，使膜層之間微影製程的對準具有更高的精確性。對準標記容許晶圓進行製程時的定位測量。依據該測量，步進機(stepper)可移動或修正晶圓位置，以協助微影製程獲得更佳的對準。
在本發明一實施例中，一種具有對準標記的結構，包括：一基底，具有一第一區及一第二區；一基底通孔電極，位於基底內且穿過基底的第一區；一隔離層，位於基底的第二區，隔離層具有一凹口；以及一導電材料，位於隔離層上並順應凹口內的隔離層，隔離層設置於導電材料與基底之間。
在本發明另一實施例中，一種具有對準標記的結構，包括：一基底，包括一基底通孔電極，基底通孔電極自基底的一前表面延伸至基底的一背表面；一隔離層，位於基底的背表面，隔離層具有一凹穴；以及一導體，位於凹穴內並順應凹穴內的隔離層，隔離層設置於導體與基底之間。
在本發明又一實施例中，一種堆疊裝置的製造方法，包括：提供一基底，其具有一基底通孔電極突出於基底的一背側；於基底的背側上形成一隔離層，隔離層具有一凹口；以及於凹口內順應形成一導電層，隔離層設置於導電層與基底之間。
以下說明本發明實施例之製作與使用。然而，可輕易了解本發明實施例提供許多合適的發明概念而可實施於廣泛的各種特定背景。所揭示的特定實施例僅僅用於說明以特定方法製作及使用本發明，並非用以侷限本發明的範圍。
以下說明本發明實施例之一特定背景，即在堆疊裝置的晶片進行製程處理期間所形成的對準標記。然而，上述實施例也可應用於轉接板(interposer)或是在製程期間使用對準標記的另一結構。
第1A至1H圖係繪示出根據本發明實施例之用於堆疊裝置的對準標記製造方法。第2圖係繪示出由第1A至1H圖的方法所形成的結構。該方法中所述的任何順序僅為了清晰的說明，而方法的步驟可在任何邏輯進展中進行。
第1A圖係繪示出製程中間階段(例如，進行前側製程之後)中的一基底100，例如一堆疊裝置的晶片(die)。特別的是此時的製程中，基底100內已形成了基底通孔電極(TSV)102、一或多個具有內連結構106的金屬化層104已形成於基底100上，且形成了導電凸塊(bump)108而電性耦接至內連結構106。基底100可為任何適當的材料，例如矽。基底通孔電極102可包括一襯層(liner layer)、一擴散阻障層、一黏著層、一隔離層等等並且填有一導電材料。舉例來說，襯層可為，氮化矽、氧化矽、高分子材料及/或其組合等等。擴散阻障層可包括一或多層的TaN、Ta、TiN、Ti、CoW等等，而導電材料可包括由電化學電鍍製程所形成的銅、鎢、鋁、銀及/或其組合等等。金屬化層104、內連結構106及導電凸塊108可為任何可接受的材料且由適當的製程所形成，例如熟習的後段(back end of the line,BEOL)製程。
再者，基底100前側經由黏著層110而貼附於一承載板112以進行背側製程。一般而言，承載板112在後續製程期間提供暫時性的機械及結構上的支撐。在上述方式中，可降低或防止基底100受損。舉例來說，承載板112可包括玻璃、氧化矽、氧化鋁等等。黏著層110可為任何適當的黏著劑，例如紫外光固化膠(UV膠)，其暴露於紫外光時會失去黏性。需注意的是標號104至112並未明確地標示於第1B至1H圖及第2圖中。然而，對應於這些標號的特徵部件係繪示於這些圖中。未標示這些標號僅是為了讓圖式更為清晰。
請參照第1B圖，其繪示出第1A圖的結構在基底100進行薄化(thinned)及向下凹陷(recessed)之後露出於基底100背側的基底通孔電極102。薄化及向下凹陷可使基底100形成一薄基底，其厚度近似20微米至200微米。可利用平坦化製程、蝕刻製程及/或其組合來進行薄化及向下凹陷製程。舉例來說，初始可進行平坦化製程，例如化學機械研磨(chemical mechanical polishing,CMP)，以初步露出基底通孔電極102的上表面。之後，可進行一或多道的蝕刻製程，其對於基底通孔電極102的材料與基底100之間具有高蝕刻選擇比，以留下突出於基底100背側的基底通孔電極102。
第1C圖係繪示出在基底100背側上形成光阻層114。光阻層114的厚度可大於基底通孔電極102突出部位的高度。光阻層114內具有開口116。開口116可利用微影技術而形成，例如利用微影罩幕，對欲形成開口116處的光阻層114進行曝光。在形成開口116之後，進行蝕刻製程，例如異向性(anisotropic)蝕刻，以形成凹入基底100背側表面下方的開口118，如第1D圖所示。第1E圖係繪示出對第1D圖的結構進行灰化(ash/flash)製程之後，而去除了光阻層114。
第1F圖係繪示出在第1E圖的結構上形成第一隔離層120及第二隔離層122。第一及第二隔離層120及122可包括氮化矽、氧化矽、碳化矽、氮氧化矽、氧化物、高分子材料及/或其組合等等。第一及第二隔離層120及122可為單一層或是實質上由相同或不同材料所組成的多層結構。在第1F圖的範例中，第一隔離層120為氮化矽，而第二隔離層122為氧化矽。第一及第二隔離層120及122可使用適當的沉積技術而形成，例如化學氣相沉積(chemical vapor deposition,CVD)或是低溫CVD製程。如第1F圖所示，第一及第二隔離層120及122兩者形成於開口118內露出的基底100上表面上且順應於這些露出的表面。
第1G圖係繪示出在第二隔離層122上方形成一光阻層124。可對光阻層124進行圖案化，例如對光阻層124進行曝光，以容許進行蝕刻製程時，去除塗覆於基底通孔電極102突出部位的第一及第二隔離層120及122。接著，對第一及第二隔離層120及122進行蝕刻，例如乾蝕刻，以容許基底通孔電極102自第一及第二隔離層120及122下方露出，如第1H圖所示。蝕刻製程所使用的蝕刻劑對於基底通孔電極102與第一及第二隔離層120及122之間具有高蝕刻選擇比，第1H圖更進一步繪示出進行灰化製程之後，去除了光阻層124的結構。
第2圖係繪示出經由第1A至1H圖的方法所形成具有對準標記130的結構。如第2圖所示，第1H圖的結構更包括了第一金屬層126及第二金屬層128。第一金屬層126可為鈦(Ti)、氮化鈦(TiN)、鈦鎢(TiW)、氮化矽鈦(TiSiN)、鉭(Ta)、氮化鉭(TaN)、氮化矽鉭(TaSiN)、鎢(W)、氮化鎢(W2 N)、氮化矽鎢(WSiN)及/或其組合等等。而第二金屬層128可為銅等。第一及第二金屬層126及128可藉由適當的沉積技術而形成，例如物理氣相沉積(physical vapor deposition,PVD)、CVD或原子層沉積(atomic layer deposition,ALD)。形成於開口118內的第一及第二金屬層126及128連同設置於第一金屬層126與基底100之間的第一及第二隔離層120及122，構成了位於基底100背側的對準標記130。任何所屬技術領域中具有通常知識者可輕易理解在後續製程步驟中(例如，在基底通孔電極102上形成銅柱體之後)可去除部分的第一及第二金屬層126及128，例如位於基底通孔電極102之間的部分，以避免基底通孔電極102發生短路。
第3A至3H圖係繪示出根據本發明另一實施例之用於堆疊裝置的基底上的對準標記製造方法，而第4A至4F圖係繪示出根據本發明又另一實施例之用於堆疊裝置的對準標記製造方法。第5圖係繪示出由上述方法所形成的結構。方法中所述的任何順序僅為了清晰的說明，而方法的步驟可在任何邏輯進展中進行。
首先說明第3A至3H圖所示的方法。請參照第3A圖，製程中間階段(例如，進行前側製程之後)中的一基底200。特別的是此時的製程中，基底200內已形成了基底通孔電極(TSV)202、一或多個具有內連結構206的金屬化層204已形成於基底200上，且形成了導電凸塊208而電性耦接至內連結構206。基底200可為任何適當的材料，例如矽。基底通孔電極202可包括一襯層、一擴散阻障層、一黏著層等等並且填有一導電材料。舉例來說，襯層可為，氮化矽、氧化矽、高分子材料及/或其組合等等。擴散阻障層可包括一或多層的TaN、Ta、TiN、Ti、CoW等等，而導電材料可包括由電化學電鍍製程所形成的銅、鎢、鋁、銀及/或其組合等等。金屬化層204、內連結構206及導電凸塊208可為任何可接受的材料且由適當的製程所形成，例如熟習的後段(BEOL)製程。
再者，基底200前側經由黏著層210而貼附於一承載板212以進行背側製程。一般而言，承載板212在後續製程期間提供暫時性的機械及結構上的支撐。在上述方式中，可降低或防止基底200受損。舉例來說，承載板212可包括玻璃、氧化矽、氧化鋁等等。黏著層210可為任何適當的黏著劑，例如紫外光固化膠(UV膠)，其暴露於紫外光時會失去黏性。需注意的是標號204至212並未明確地標示於第3B至3H圖及第5圖中。然而，對應於這些標號的特徵部件係繪示於這些圖中。未標示這些標號僅是為了讓圖式更為清晰。
請參照第3B圖，其繪示出第3A圖的結構在基底100進行薄化及向下凹陷之後露出於基底200背側的基底通孔電極202。薄化及向下凹陷可使基底200形成一薄基底，其厚度近似20微米至200微米。可利用平坦化製程、蝕刻製程及/或其組合來進行薄化及向下凹陷製程。舉例來說，初始可進行平坦化製程，例如化學機械研磨(CMP)，以初步露出基底通孔電極202的上表面。之後，可進行一或多道的蝕刻製程，其對於基底通孔電極202的材料與基底200之間具有高蝕刻選擇比，以留下突出於基底200背側的基底通孔電極202。
第3C圖係繪示出在第3B圖的結構上形成第一隔離層214及第二隔離層216。第一隔離層214形成於基底200背側上，而第二隔離層216形成於第一隔離層214上。第一及第二隔離層214及216可包括氮化矽、氧化矽、碳化矽、氮氧化矽、氧化物、高分子材料及/或其組合等等。第一及第二隔離層214及216可為單一層或是實質上由相同或不同材料所組成的多層結構。在第3C圖的範例中，第一隔離層214為氮化矽，而第二隔離層216為氧化矽。第一及第二隔離層214及216可使用適當的沉積技術而形成，例如化學氣相沉積(CVD)或是低溫CVD製程。
第3D圖係繪示出在第二隔離層216上形成光阻層218。可對光阻層218進行圖案化，例如對光阻層218進行曝光，以容許進行蝕刻製程時，去除塗覆於基底通孔電極202突出部位的第一及第二隔離層214及216。接著，對第一及第二隔離層214及216進行蝕刻，例如乾蝕刻，以容許基底通孔電極202自第一及第二隔離層214及216下方露出，如第3E圖所示。蝕刻製程所使用的蝕刻劑對於基底通孔電極202與第一及第二隔離層214及216之間具有高蝕刻選擇比，第3E圖更進一步繪示出進行灰化製程之後，去除了光阻層218的結構。
第3F圖係繪示出在第二隔離層216上形成光阻層220。光阻層220內具有開口222。開口222可利用微影技術而形成，例如利用微影罩幕，對欲形成開口222處的光阻層220進行曝光。在形成開口222之後，進行異向性蝕刻製程，以形成凹入第二隔離層216的開口224，如第3G圖所示。開口224可進一步凹入第一隔離層214內，但未及於或低於基底200背側表面。第3H圖係繪示出對第3G圖的結構進行灰化製程之後，而去除了光阻層220。
現在說明第4A至4F圖所示之方法。第4A至4C圖所進行的方法相同於前述對應於第3A至3C圖所進行的方法。因此，為了簡化說明，在此不再贅述這些步驟。再者，第4A至4C圖中相同或相似於第3A至3C圖的部件係使用相同的標號。
第4D圖係繪示出在第二隔離層216上形成光阻層230。光阻層230內具有開口232。開口232可利用微影技術而形成，例如利用微影罩幕，對欲形成開口222處的光阻層230進行曝光。接著蝕刻第二隔離層216，例如進行異向性蝕刻製程，以形成凹入第二隔離層216的開口234，如第4E圖所示。蝕刻製程所使用的蝕刻劑對於第二隔離層216與第一隔離層214所使用的材料之間具有高蝕刻選擇比。之後，可利用平坦化製程，例如CMP，去除基底通孔電極202上方的第一及第二隔離層214及216，以容許基底通孔電極202露出上表面，如第4F圖所示。第4F圖係進一步繪示出進行灰化製程之後，去除光阻層230的結構。
第5圖係繪示出經由第3A至3H圖或第4A至4F圖的方法所形成具有對準標記240的結構。如第5圖所示，第3H或4F圖的結構更包括了第一金屬層236及第二金屬層238。第一金屬層236可為Ti、TiN、TiW、TiSiN、Ta、TaN、TaSiN、W、W2 N、WSiN及/或其組合等等。而第二金屬層238可為銅等。第一及第二金屬層236及238可藉由適當的沉積技術而形成，例如PVD、CVD或ALD。形成於開口234內的第一及第二金屬層236及238連同設置於第一金屬層236與基底200之間的第二隔離層216，構成了位於基底200背側的對準標記240。任何所屬技術領域中具有通常知識者可輕易理解在後續製程步驟中(例如，在基底通孔電極202上形成銅柱體之後)可去除部分的第一及第二金屬層236及238，例如位於基底通孔電極202之間的部分，以避免基底通孔電極202發生短路。
上述實施例可防止對準標記內金屬的擴散。隔離層可形成一阻障層，以防止金屬，例如銅，擴散進入上述實施例的基底內。透過預防擴散，形成於基底內的裝置及結構很少會發生由於對準標記內金屬擴散所造成的短路或其他問題而導致無法操作的情形。
同樣地，上述實施例的方法及結構可增加製程的產能。再者，由於製程的改善(例如使用低溫製程)，因此可緩和薄化基底內的應力及應變。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種更動、替代與潤飾。再者，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此，本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。
100、200．．．基底
102、202．．．基底通孔電極
104、204．．．金屬化層
106、206．．．內連結構
108、208．．．導電凸塊
110、210．．．黏著層
112、212．．．承載板
114、124、218、220、230．．．光阻層
116、118、222、224、232、234．．．開口
120、214．．．第一隔離層
122、216．．．第二隔離層
126、236．．．第一金屬層
128、238．．．第二金屬層
130、240．．．對準標記
第1A至1H圖係繪示出根據本發明實施例之用於堆疊裝置的對準標記製造方法。
第2圖係繪示出經由第1A至1H圖的方法所形成具有對準標記的結構。
第3A至3H圖係繪示出根據本發明另一實施例之用於堆疊裝置的基底上的對準標記製造方法。
第4A至4F圖係繪示出根據本發明又另一實施例之對準標記製造方法。
第5圖係繪示出經由第3A至3H圖或第4A至4F圖的方法所形成具有對準標記的結構。
100．．．基底
102．．．基底通孔電極
120．．．第一隔離層
122．．．第二隔離層
126．．．第一金屬層
128．．．第二金屬層
130．．．對準標記

Claims (10)

  1. 一種具有對準標記的結構，包括：一基底，具有一第一區及一第二區；一基底通孔電極，位於該基底內且穿過該基底的該第一區；一隔離層，位於該基底的該第二區，該隔離層具有一凹口；以及一導電材料，位於該隔離層上並順應該凹口內的該隔離層，該隔離層設置於該導電材料與該基底之間。
  2. 如申請專利範圍第1項所述之具有對準標記的結構，其中該凹口延伸進入該基底內或未延伸進入該基底內。
  3. 如申請專利範圍第1項所述之具有對準標記的結構，其中該隔離層包括一第一次層及位於其上的一第二次層，該第一次層的組成不同於該第二次層，且其中該凹口僅延伸穿過該第二次層。
  4. 一種具有對準標記的結構，包括：一基底，包括一基底通孔電極，該基底通孔電極自該基底的一前表面延伸至該基底的一背表面；一隔離層，位於該基底的該背表面，該隔離層具有一凹穴；以及一導體，位於該凹穴內並順應該凹穴內的該隔離層，該隔離層設置於該導體與該基底之間。
  5. 如申請專利範圍第4項所述之具有對準標記的結構，該隔離層包括一第一次層及位於其上的一第二次層，而該凹穴為位於該第二次層內的一開口，且該第一次層設置於該導體與該基底之間。
  6. 如申請專利範圍第4項所述之具有對準標記的結構，其中該凹穴包括延伸進入該基底而位於該基底的該背表面內的一凹口，該隔離層順應該凹口。
  7. 一種堆疊裝置的製造方法，包括：提供一基底，其具有一基底通孔電極突出於該基底的一背側；於該基底的該背側上形成一隔離層，該隔離層具有一凹口；以及於該凹口內順應形成一導電層，該隔離層設置於該導電層與該基底之間。
  8. 如申請專利範圍第7項所述之堆疊裝置的製造方法，其中形成該隔離層包括在該基底的該背側內形成一開口以及形成順應該開口的該隔離層，以構成該凹口。
  9. 如申請專利範圍第7項所述之堆疊裝置的製造方法，其中形成該隔離層包括在該隔離層內形成一開口，已構成該凹口，該開口未到達該基底的該背側。
  10. 如申請專利範圍第7項所述之堆疊裝置的製造方法，其中形成該隔離層包括形成一第一次層及位於其上的一第二次層，而該第一及該第二次層具有不同的材料。
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Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8513119B2 (en) 2008-12-10 2013-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bump structure having tapered sidewalls for stacked dies
US20100171197A1 (en) 2009-01-05 2010-07-08 Hung-Pin Chang Isolation Structure for Stacked Dies
US8466059B2 (en) 2010-03-30 2013-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-layer interconnect structure for stacked dies
US8466553B2 (en) * 2010-10-12 2013-06-18 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package having the same
JP6053256B2 (ja) 2011-03-25 2016-12-27 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体チップ及びその製造方法、並びに半導体装置
US8900994B2 (en) 2011-06-09 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for producing a protective structure
US8525168B2 (en) * 2011-07-11 2013-09-03 International Business Machines Corporation Integrated circuit (IC) test probe
KR101840846B1 (ko) * 2012-02-15 2018-03-21 삼성전자주식회사 관통전극을 갖는 반도체 소자 및 그 제조방법
US8940637B2 (en) * 2012-07-05 2015-01-27 Globalfoundries Singapore Pte. Ltd. Method for forming through silicon via with wafer backside protection
KR102018885B1 (ko) 2012-12-20 2019-09-05 삼성전자주식회사 관통전극을 갖는 반도체 소자 및 그 제조방법
US8860228B2 (en) * 2012-12-26 2014-10-14 Stmicroelectronics Pte. Ltd. Electronic device including electrically conductive vias having different cross-sectional areas and related methods
TWI517328B (zh) * 2013-03-07 2016-01-11 矽品精密工業股份有限公司 半導體裝置
US8884427B2 (en) * 2013-03-14 2014-11-11 Invensas Corporation Low CTE interposer without TSV structure
US20140264848A1 (en) * 2013-03-14 2014-09-18 SK Hynix Inc. Semiconductor package and method for fabricating the same
JP2014187185A (ja) 2013-03-22 2014-10-02 Renesas Electronics Corp 半導体装置の製造方法
US9059111B2 (en) * 2013-04-11 2015-06-16 International Business Machines Corporation Reliable back-side-metal structure
CN104465492B (zh) * 2013-09-23 2018-03-16 中芯国际集成电路制造(上海)有限公司 穿透硅通孔结构的形成方法以及集成电路制造方法
KR20150048388A (ko) * 2013-10-28 2015-05-07 삼성전자주식회사 반도체 장치 및 이의 제조 방법
CN104733371B (zh) * 2013-12-18 2018-08-10 中芯国际集成电路制造(上海)有限公司 硅通孔形成方法及半导体器件的对准结构
US9478509B2 (en) * 2014-03-06 2016-10-25 GlobalFoundries, Inc. Mechanically anchored backside C4 pad
US9318452B2 (en) 2014-03-21 2016-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US9735129B2 (en) * 2014-03-21 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
KR102165266B1 (ko) * 2014-04-03 2020-10-13 삼성전자 주식회사 반도체 소자 및 반도체 패키지
KR20170037705A (ko) 2015-09-25 2017-04-05 삼성전자주식회사 입력 신호들을 랭크별로 제어하는 메모리 버퍼를 갖는 메모리 모듈
US10229877B2 (en) 2016-06-22 2019-03-12 Nanya Technology Corporation Semiconductor chip and multi-chip package using thereof
KR20180014362A (ko) 2016-07-29 2018-02-08 삼성전자주식회사 회로 기판 및 반도체 패키지
US10627720B2 (en) * 2017-08-18 2020-04-21 Globalfoundries Inc. Overlay mark structures
US20190392879A1 (en) * 2018-06-26 2019-12-26 Spin Memory, Inc. MAGNETIC MEMORY ELEMENT HAVING MgO ISOLATION LAYER
US11694968B2 (en) * 2020-11-13 2023-07-04 Samsung Electronics Co., Ltd Three dimensional integrated semiconductor architecture having alignment marks provided in a carrier substrate
US11798888B2 (en) * 2020-12-11 2023-10-24 Sj Semiconductor (Jiangyin) Corporation Chip packaging structure and method for preparing same
US11908836B2 (en) * 2021-01-13 2024-02-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method of manufacturing semiconductor package

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040169255A1 (en) * 2003-02-28 2004-09-02 Masahiro Kiyotoshi Semiconductor device and method of manufacturing same
US20040188822A1 (en) * 2003-01-15 2004-09-30 Kazumi Hara Semiconductor chip, semiconductor wafer, semiconductor device and method of manufacturing the same, circuit board, and electronic instrument
US20060141737A1 (en) * 2003-06-24 2006-06-29 Gaidis Michael C Planar magnetic tunnel junction substrate having recessed alignment marks
US20090166811A1 (en) * 2007-12-27 2009-07-02 Shinko Electric Industries Co., Ltd Semiconductor device and manufacturing method thereof

Family Cites Families (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05211239A (ja) 1991-09-12 1993-08-20 Texas Instr Inc <Ti> 集積回路相互接続構造とそれを形成する方法
DE4314907C1 (de) 1993-05-05 1994-08-25 Siemens Ag Verfahren zur Herstellung von vertikal miteinander elektrisch leitend kontaktierten Halbleiterbauelementen
US5391917A (en) 1993-05-10 1995-02-21 International Business Machines Corporation Multiprocessor module packaging
JP2595885B2 (ja) 1993-11-18 1997-04-02 日本電気株式会社 半導体装置およびその製造方法
US6882030B2 (en) 1996-10-29 2005-04-19 Tru-Si Technologies, Inc. Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate
EP0948808A4 (en) 1996-10-29 2000-05-10 Trusi Technologies Llc INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF
US6809421B1 (en) * 1996-12-02 2004-10-26 Kabushiki Kaisha Toshiba Multichip semiconductor device, chip therefor and method of formation thereof
US5783490A (en) 1997-04-21 1998-07-21 Vanguard International Semiconductor Corporation Photolithography alignment mark and manufacturing method
US5972793A (en) 1997-06-09 1999-10-26 Vanguard International Semiconductor Corporation Photolithography alignment mark manufacturing process in tungsten CMP metallization
US6337522B1 (en) * 1997-07-10 2002-01-08 International Business Machines Corporation Structure employing electrically conductive adhesives
US5966613A (en) 1997-09-08 1999-10-12 Lsi Corporation Consistent alignment mark profiles on semiconductor wafers using metal organic chemical vapor deposition titanium nitride protective
US6037822A (en) 1997-09-30 2000-03-14 Intel Corporation Method and apparatus for distributing a clock on the silicon backside of an integrated circuit
US5998292A (en) 1997-11-12 1999-12-07 International Business Machines Corporation Method for making three dimensional circuit integration
JP3532788B2 (ja) 1999-04-13 2004-05-31 唯知 須賀 半導体装置及びその製造方法
JP4037561B2 (ja) 1999-06-28 2008-01-23 株式会社東芝 半導体装置の製造方法
US6322903B1 (en) 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
US6444576B1 (en) 2000-06-16 2002-09-03 Chartered Semiconductor Manufacturing, Ltd. Three dimensional IC package module
US6780775B2 (en) 2001-01-24 2004-08-24 Infineon Technologies Ag Design of lithography alignment and overlay measurement marks on CMP finished damascene surface
US6383888B1 (en) 2001-04-18 2002-05-07 Advanced Micro Devices, Inc. Method and apparatus for selecting wafer alignment marks based on film thickness variation
US6878615B2 (en) * 2001-05-24 2005-04-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method to solve via poisoning for porous low-k dielectric
JP4680424B2 (ja) 2001-06-01 2011-05-11 Ｏｋｉセミコンダクタ株式会社 重ね合わせ位置検出マークの製造方法
US6599778B2 (en) 2001-12-19 2003-07-29 International Business Machines Corporation Chip and wafer integration process using vertical connections
WO2003063242A1 (en) 2002-01-16 2003-07-31 Alfred E. Mann Foundation For Scientific Research Space-saving packaging of electronic circuits
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
JP2003257970A (ja) * 2002-02-27 2003-09-12 Nec Electronics Corp 半導体装置及びその配線構造
TWI265550B (en) 2002-05-14 2006-11-01 Toshiba Corp Fabrication method, manufacturing method for semiconductor device, and fabrication device
US6800930B2 (en) 2002-07-31 2004-10-05 Micron Technology, Inc. Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies
US7030481B2 (en) 2002-12-09 2006-04-18 Internation Business Machines Corporation High density chip carrier with integrated passive devices
US6621119B1 (en) * 2003-02-04 2003-09-16 Ching-Yuan Wu Isolated stack-gate flash cell structure and its contactless flash memory arrays
US6803291B1 (en) 2003-03-20 2004-10-12 Taiwan Semiconductor Manufacturing Co., Ltd Method to preserve alignment mark optical integrity
US6841883B1 (en) 2003-03-31 2005-01-11 Micron Technology, Inc. Multi-dice chip scale semiconductor components and wafer level methods of fabrication
US6924551B2 (en) 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package
US7111149B2 (en) 2003-07-07 2006-09-19 Intel Corporation Method and apparatus for generating a device ID for stacked devices
TWI251313B (en) 2003-09-26 2006-03-11 Seiko Epson Corp Intermediate chip module, semiconductor device, circuit board, and electronic device
US7335972B2 (en) 2003-11-13 2008-02-26 Sandia Corporation Heterogeneously integrated microsystem-on-a-chip
US7049170B2 (en) 2003-12-17 2006-05-23 Tru-Si Technologies, Inc. Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
US7060601B2 (en) 2003-12-17 2006-06-13 Tru-Si Technologies, Inc. Packaging substrates for integrated circuits and soldering methods
JP4467318B2 (ja) 2004-01-28 2010-05-26 Ｎｅｃエレクトロニクス株式会社 半導体装置、マルチチップ半導体装置用チップのアライメント方法およびマルチチップ半導体装置用チップの製造方法
JP4074862B2 (ja) * 2004-03-24 2008-04-16 ローム株式会社 半導体装置の製造方法、半導体装置、および半導体チップ
JP4966487B2 (ja) * 2004-09-29 2012-07-04 オンセミコンダクター・トレーディング・リミテッド 半導体装置及びその製造方法
US7262495B2 (en) 2004-10-07 2007-08-28 Hewlett-Packard Development Company, L.P. 3D interconnect with protruding contacts
US20060264021A1 (en) * 2005-05-17 2006-11-23 Intel Corporation Offset solder bump method and apparatus
US7297574B2 (en) 2005-06-17 2007-11-20 Infineon Technologies Ag Multi-chip device and method for producing a multi-chip device
US7902643B2 (en) * 2006-08-31 2011-03-08 Micron Technology, Inc. Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods
US8476769B2 (en) * 2007-10-17 2013-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon vias and methods for forming the same
US8084854B2 (en) * 2007-12-28 2011-12-27 Micron Technology, Inc. Pass-through 3D interconnect for microelectronic dies and associated systems and methods
US8039314B2 (en) * 2008-08-04 2011-10-18 International Business Machines Corporation Metal adhesion by induced surface roughness
KR20100021856A (ko) 2008-08-18 2010-02-26 삼성전자주식회사 관통 전극을 갖는 반도체장치의 형성방법 및 관련된 장치
US7956442B2 (en) * 2008-10-09 2011-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Backside connection to TSVs having redistribution lines
US8227295B2 (en) * 2008-10-16 2012-07-24 Texas Instruments Incorporated IC die having TSV and wafer level underfill and stacked IC devices comprising a workpiece solder connected to the TSV
WO2010049852A1 (en) * 2008-10-30 2010-05-06 Nxp B.V. Through-substrate via and redistribution layer with metal paste
US8513119B2 (en) * 2008-12-10 2013-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bump structure having tapered sidewalls for stacked dies
US7839163B2 (en) * 2009-01-22 2010-11-23 International Business Machines Corporation Programmable through silicon via
US8587121B2 (en) * 2010-03-24 2013-11-19 International Business Machines Corporation Backside dummy plugs for 3D integration

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040188822A1 (en) * 2003-01-15 2004-09-30 Kazumi Hara Semiconductor chip, semiconductor wafer, semiconductor device and method of manufacturing the same, circuit board, and electronic instrument
US20040169255A1 (en) * 2003-02-28 2004-09-02 Masahiro Kiyotoshi Semiconductor device and method of manufacturing same
US20060141737A1 (en) * 2003-06-24 2006-06-29 Gaidis Michael C Planar magnetic tunnel junction substrate having recessed alignment marks
US20090166811A1 (en) * 2007-12-27 2009-07-02 Shinko Electric Industries Co., Ltd Semiconductor device and manufacturing method thereof

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