TWI515826B - 貫穿矽介層及其製造方法 - Google Patents

貫穿矽介層及其製造方法 Download PDF

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TWI515826B
TWI515826B TW098125343A TW98125343A TWI515826B TW I515826 B TWI515826 B TW I515826B TW 098125343 A TW098125343 A TW 098125343A TW 98125343 A TW98125343 A TW 98125343A TW I515826 B TWI515826 B TW I515826B
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trench
layer
top surface
substrate
forming
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TW201013841A (en
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保羅 史蒂芬 安卓
艾慕德 喬瑞斯 史普洛吉斯
柯尼利亞 康依 曾
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烏翠泰克股份有限公司
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Description

貫穿矽介層及其製造方法
本發明有關積體電路的領域，尤其有關積體電路晶片中使用的貫穿矽介層及製造貫穿矽介層的方法。
為增加使用積體電路晶片之裝置的密度，需要在積體電路晶片頂面及底面上製作互連線。這需要形成從積體電路晶片頂面至底面並相容於互補金屬氧化矽(CMOS)技術的貫穿矽介層。許多現有的貫穿介層方案不是難以和CMOS製程整合，就是導致積體電路晶片正面與底面間令人無法接受的信號傳播降級。因此，本技術中需要克服上述缺點及限制。
本發明之第一方面為一種方法，包含：(a)形成一溝渠於一矽基板中，該溝渠開啟至基板之一頂面；(b)形成一二氧化矽層於溝渠的側壁上，且二氧化矽層未填充溝渠；(c)用多晶矽填充溝渠中的其餘空間；(d)在(c)之後，製造CMOS裝置的至少一部分於基板中；(e)自溝渠移除多晶矽，介電層繼續保留在溝渠的側壁上；(f)用一導電核心再填充溝渠；及(g)在(f)之後，形成一或多個配線層於基板的頂面之上，一或多個配線層級之一配線層級的一線路接近接觸導電核心之一頂面的基板。
本發明之第二方面為一種方法，包含：(a)形成一氧化障 壁層於一矽基板的一頂面上及形成一開口於障壁層中，基板之頂面的一區域在開口的一底部中暴露；(b)形成一溝渠於基板未受障壁層保護的矽基板中，溝渠開啟至基板的一頂面；(c)形成一二氧化矽層於溝渠的側壁上，二氧化矽層未填充溝渠；(d)移除氧化障壁層；(e)形成一硬遮罩層於基板的頂面及二氧化矽層的所有暴露表面上；(f)用多晶矽填充溝渠中的其餘空間，其後多晶矽的一頂面與硬遮罩層的一頂面共面；在(f)之後，(g)形成一場效電晶體之一源極、一汲極及一通道區域於基板中，一閘極介電質於通道區域上及一閘極電極於閘極介電質上；(h)形成一保護層於硬遮罩層及場效電晶體之上；(i)形成穿過保護層到達場效電晶體之相應的源極、汲極及閘極電極的金屬接點，金屬接點的頂面與保護層的一頂面共面；(j)形成一開口於溝渠之上的保護層中及自溝渠移除多晶矽，介電層及硬遮罩層繼續留在溝渠的側壁上；(k)用一導電核心再填充溝渠，介電層及硬遮罩層繼續留在溝渠的側壁上，核心的一頂面與保護層的頂面共面；及在(k)之後，(l)形成一或多個配線層於保護層上，一或多個配線層級之一配線層級的一線路接近接觸導電核心之頂面的基板。
本發明之第三方面為一種結構，包含：在一矽基板中的一溝渠；在溝渠之側壁上的一二氧化矽層，二氧化矽層未填充溝渠，二氧化矽層在溝渠的側壁上的二氧化矽層之最薄及最厚區域之間具有一厚度變化小於約10%；填充溝渠中其餘空間的一導電核心，至少一部分在基板中的一CMOS裝置；及一或多個在基板之頂面上的配線層，一或多個配線層級之一配線層級的一線路接近接觸導電核心之一頂面的基板。
本發明之第四方面為一種結構，包含：在一矽基板中的一溝渠；在溝渠側壁上的二氧化矽層，二氧化矽層未填充溝渠；在基板之頂面上及在二氧化矽層上的一介電層，介電層未填充溝渠；一導電核心，其填充溝渠中其餘空間，基板中一場效電晶體的一源極、汲極及通道區域、通道區域上的一閘極介電質、及閘極介電質上的一閘極電極；在介電層及場效電晶體之上的一保護層；核心延伸穿過保護層，核心之一頂面與保護層之頂面共面；穿過保護層到達場效電晶體之相應的源極、汲極及閘極電極的金屬接點，金屬接點的頂面與保護層的一頂面共面；及一或多個在保護層上的配線層，一或多個配線層級之一配線層級的一線路接近接觸導電核心之頂面的基板。
圖1A至1M根據本發明具體實施例，為圖解貫穿矽介層之初始製造步驟的橫截面圖。在圖1A中，單晶矽基板100具有頂面105。在一範例中，基板100具有相對於頂面105的<100>晶向。在一範例中，基板100為摻雜P型。障壁層110形成於基板100的頂面105上。在一範例中，障壁層110包含二或多個單獨層。在一範例中及如圖1A所示，障壁層110由基板100上的第一層115及第一層上的第二層120組成。在一範例中，第一層115為二氧化矽且厚度介於約5nm及約20nm，第二層120為氮化矽且厚度介於約10nm及約30nm。在一範例中，障壁層110包含二氧化矽層、氮化矽層、及碳化矽層中的一或多個。障壁層110的一個用途是在後續處理步驟中，當作矽的氧化障壁(即，氧(如 O、O2或O3)、氫/氧化合物(如，H2O)、及其他含氧化合物(如，NO、N2O)的擴散障壁)。因此，障壁層110的至少一層由氧化障壁的材料組成。障壁層110還需要有足夠的厚度，致使如果其表面氧化，還保留有足夠的材料厚度仍能當作氧(或水)的擴散障壁。為了解說之故，將在下文說明的後續圖式中圖解第一層115及第二層120。
在圖1B中，在障壁層110上形成光阻層125，及利用微影在光阻層中形成開口130，以暴露在開口底部中的襯墊介電質。
微影製程係製程如下：在表面上塗上光阻層，透過圖案化光罩使光阻層曝光於光化輻射，然後使曝光的光阻層顯影以形成圖案化光阻層。當光阻層包含正光阻時，顯影劑溶解曝光於光化輻射的光阻區域，而不會溶解圖案化光罩擋住(或大幅減弱輻射強度)光照射在光阻層上的區域。當光阻層包含負光阻時，顯影劑不會溶解曝光於光化輻射的光阻區域，而會溶解圖案化光罩擋住(或大幅減弱輻射強度)光照射在光阻層上的區域。在進一步處理(如，蝕刻或離子植入)之後，移除圖案化光阻。可視需要在以下一或多個情形中烘烤光阻層：在曝光於光化輻射之前、在曝光於光化輻射及顯影之間、在顯影之後。
在圖1C中，蝕刻開口135穿過障壁層110，其中障壁層在光阻層125的開口130中暴露。基板100的頂面105在 開口135的底部暴露。在一範例中，利用反應性離子蝕刻(RIE)製程形成開口135。
在圖1D中，在障壁層110的開口135中，將溝渠140蝕刻至基板100中。在一範例中，使用RIE製程蝕刻溝渠140。蝕刻溝渠140之合適RIE製程的一個範例在業界中稱為「波希法(Bosch process)」(又稱為「脈衝或時間多工電漿蝕刻製程」)。
在圖1E中，移除光阻層125(見圖1D)。這可利用以下方式來完成：乾式剝離清洗(如，在氧電漿中蝕刻光阻層)、在酸性溶液中進行濕式剝離、或乾式及濕式剝離二者的組合。溝渠140從頂面105延伸距離D至基板100中，且具有實質上一致、按相對於基板100之頂面105的所量角度A實質上平直的側壁141(即，在約W1的正負10%內)。在一範例中，A介於約85°及約95°。在一範例中，A介於約88°及約92°。如圖1E所示，A等於約90°。有利的是，A儘可能接近90°。在一範例中，D介於約20微米及約200微米及W1介於約1微米及約5微米。將寬度定義為在與基板頂面平行的平面中所測量、在溝渠之兩個最接近且相對側壁之間的距離。例如，在兩側平直的矩形溝渠中，在長邊之間且與長邊垂直處測量寬度，然後得到單一寬度值。例如，在兩側逐漸變窄的矩形溝渠中，在長邊之間且與長邊垂直處測量寬度，但寬度值將隨著在與基板頂面平行處測量(但仍在最接近的對置側壁之間測量)寬度的平面而有所變化。
圖1F圖解第一替代形狀的溝渠。在圖1F中，溝渠140A在溝渠頂部具有寬度W1及在溝渠底部具有寬度W2。W1大於W2。在圖1F中，側壁142以角度A均勻地向內逐漸變窄。如圖1F所示，A大於90°。
圖1G圖解第二替代形狀的溝渠。在圖1G中，溝渠140B在溝渠頂部具有寬度W1及在溝渠底部具有寬度W3。W3大於W1。在圖1G中，溝渠140B具有向外逐漸變窄的側壁143及較寬底部144。如圖1G所示，A小於90°。為了解說之故，將在下文說明的後續圖式中圖解圖1E的溝渠140。
在圖1H中，已在溝渠140兩側及底部上形成二氧化矽層145。利用氧化製程形成二氧化矽層145。因為二氧化矽在緊鄰溝渠140之頂面105的兩個方向中生長，因而在障壁層110中在溝渠140周圍附近形成尖端150。在一範例中，在正常壓力(即，一個大氣壓力(atm))及介於約1000℃及約1200℃的溫度下，使用H2O以濕式氧化形成二氧化矽層145。在一範例中，在正常壓力及介於約1000℃及約1200℃的溫度下，使用O2以乾式氧化形成二氧化矽層145。在一範例中，在高壓(即，大於一個atm)中，在介於約500℃及約800℃的溫度下，使用O2或H2O形成二氧化矽層145。二氧化矽層145具有厚度T1。由於二氧化矽層145利用氧化形成，因此二氧化矽層約一半的厚度係藉由消耗矽而形成，其中約一半的氧化物生長是從溝渠140之原始(圖1E)側壁進入基板中，及約一半的氧化物生長是從溝渠原始側壁 進入溝渠中。在溝渠140的側壁及底部上已消耗掉厚度約(T1)/2的矽層。溝渠140現在寬度減少為W4，因此W1(見圖1E)約等於W4+T1。在一範例中，T1介於0.1微米及約1微米及W4介於約0.8微米及約4.8微米。在一範例中，T1至少約0.5微米。
本發明具體實施例之一特色是在溝渠側壁上，形成二氧化矽層145在二氧化矽層的最薄及最厚(在與溝渠側壁垂直的方向中測量)區域之間的厚度變化小於約10%，這以目前的CMOS相容溝渠技術是做不到的。本發明具體實施例之一特色是形成厚度約0.5微米或以上之二氧化矽層145的能力，這以目前的CMOS相容溝渠技術是做不到的。本發明具體實施例之一特色是在溝渠側壁上，形成二氧化矽層145在氧化物的最薄及最厚(在與溝渠側壁垂直的方向中測量)區域之間的厚度變化小於約10%及形成厚度約0.5微米或以上的二氧化矽層145，這以目前的CMOS相容溝渠技術是做不到的。
在圖1I中，視需要移除障壁層110(見圖1H)及沈積硬遮罩層155於基板100的頂面105及二氧化矽層145的所有暴露表面之上。硬遮罩層155可包含上文針對氧化障壁110所說明的任何相同材料及材料組合(見圖1A)。為了解說之故，硬遮罩層155將在下文說明的後續圖式中圖解。
在圖1J中，填料層160係沈積於硬遮罩層155上(若有 的話，否則沈積於障壁層110上，見圖1H)。在一範例中，填料層160包含多晶矽。填料層160填充溝渠140中所有其餘空間。如果在溝渠140之側壁上的任何層間之最大距離是B且填料層160的厚度是C，則C可為約1.5乘B，以確保用填料層160填充溝渠140的頂部。
在圖1K中，執行化學機械拋光(CMP)，使溝渠140中填料層160的頂面165與硬遮罩層155的頂面170共面。因此，硬遮罩層155亦當作拋光停止層。
在圖1L中，執行填料層凹陷蝕刻，以使填料層160的頂面175在基板100的頂面105下凹陷距離R。在一範例中，填料凹陷蝕刻是反應性離子蝕刻(RIE)。在一範例中，R介於約50nm及約500nm。如果執行選擇性填料凹陷蝕刻，則在圖1M中，在溝渠140中形成選擇性介電帽蓋180，以填充在圖1L中形成的凹陷。帽蓋180的頂面185與硬遮罩層155的頂面170共面。在一範例中，利用二氧化矽的化學汽相沈積(CVD)，繼而利用CMP，形成帽蓋180。為了解說之故，帽蓋層180將在下文說明的後續圖式中圖解。
在圖1M中的結構可視為前導貫穿矽介層190。貫穿矽介層按照圖2A至2G中圖解的步驟完成，且在下文結合CMOS裝置的製造及與CMOS技術相容的裝置加以說明。
圖2A至2H根據本發明具體實施例，為圖解貫穿矽介 層之製造步驟整合CMOS積體電路裝置之製造及線路的橫截面圖。在圖2A中，一般使用具有一或多個前導貫穿矽介層190的基板100開始製造積體電路。在圖2A中，已製造了場效電晶體(FET)200。FET 200包括在井210中形成並在閘極電極220下為通道區域215所分開的源極/汲極205。閘極電極220與通道區域為閘極介電質225所分開。在閘極電極220的側壁上已形成介電側壁間隔物230。源極/汲極205及井210形成於基板100中。介電溝渠隔離235鄰接井210的周圍並鄰接源極/汲極205。閘極介電質225形成於基板100的頂面105上，及閘極電極220及間隔物230形成於頂面105上方。金屬矽化物接點(未顯示)形成於源極/汲極205及閘極電極220的暴露表面上。FET 200是可在製程此時加以製造的CMOS裝置範例。其他類型的CMOS裝置或相容CMOS(即，可使用CMOS製程技術加以製造)包括：雙極電晶體(包括SiGe電晶體)、二極體、電容器、溝渠電容器、及電阻器(包括多晶矽及金屬電阻器)。在製造FET 200(及/或多個FET及其他裝置)之後，在硬遮罩層155、溝渠隔離235及FET 200的暴露部分上沈積介電保護層240。在一範例中，介電層240係為二氧化矽。在一範例中，利用CVD，使用四乙氧基矽烷(TEOS)，形成保護層240(即，形成TEOS氧化物)。在一範例中，利用氧化物的高壓(大於1atm)電漿沈積，使用矽烷及/或矽烷衍生物，形成保護層240(即，形成HDP氧化物)。
在圖2B中，形成穿過保護層240到達源極/汲極205及閘極電極220的金屬接點245。在一範例中，接點245包含鎢。金屬接點245係使用鑲嵌製程形成。
鑲嵌程序如下：其中在介電層中形成線路溝渠或介層開口，在介電質的頂面上沈積填充溝渠之足夠厚度的導電體，及執行化學機械拋光(CMP)程序以移除多餘導體，及使導體表面與介電層表面共面以形成鑲嵌線路(或鑲嵌介層)。僅形成一溝渠及一線路(或一介層開口及介層)時，將此程序稱為「單鑲嵌」。用語「線路」包括用語「接點」。
在圖2C中，使用微影/RIE製程在前導貫穿矽介層190之上形成穿過保護層240及硬遮罩層155的開口250。注意，在此製程期間移除介電帽蓋180(見圖2B)，且硬遮罩層155及二氧化矽層145的上方區域在開口250中暴露。
在圖2D中，自溝渠140中移除填料層160(見圖2C)。在第一範例中，使用對硬遮罩層155及二氧化矽層145的材料有選擇性的多晶矽波希(Bosch)蝕刻法移除填料層160(見圖2C)。在第二範例中，對160(見圖2C)使用濕式蝕刻，其使用水性TMAH或水性氫氧化銨。在第三範例中，使用對硬遮罩層155及二氧化矽層145的材料有選擇性的多晶矽波希蝕刻法移除填料層160(見圖2C)，繼而利用水性氫氧化四甲銨(TMAH)或水性氫氧化銨的濕式清除蝕刻。
在圖2E中，導電核心255完全填充溝渠140及開口250中的空間。核心255的頂面與保護層240的頂面共面。核心255已使用鑲嵌製程形成。在一範例中，核心255包含 金屬。在一範例中，核心255包含耐火金屬。耐火金屬是一種特別耐熱、耐磨且耐腐蝕的金屬類。五種耐火金屬是：鎢(W)、鉬(Mo)、鈮(Nb)、鉭(Ta)、及錸(Re)。在一範例中，核心255包含鎢、鉭或其組合。在一範例中，核心255包含銅或銅及鉭的組合。在一範例中，核心255包含摻雜多晶矽。透過所謂前段製程(FEOL)或簡稱FEOL的作業，完成積體電路的製造。核心255包括在保護層240中的整體接點區域257。
在圖2F中，在所謂後段製程(BEOL)或簡稱BEOL的作業期間，藉由添加一或多個配線層級，完成積體電路的製造。在圖2F中，添加兩個配線層級。第一配線層級259包括在層間介電(ILD)層265中形成的雙鑲嵌線路260。
雙鑲嵌程序如下：其中形成穿過介電層整個厚度的介層開口，接著形成部分穿過任何給定橫截面圖中介電層的溝渠。所有介層開口均與上方的整合線路溝渠及下方的線路溝渠相交，但並非所有溝渠必須與介層開口相交。在介電質的頂面上沈積填充溝渠及介層開口之足夠厚度的導電體，然後執行CMP程序，以使溝渠中的導體表面與介電層表面共面，以形成雙鑲嵌線路及具有整合雙鑲嵌介層的雙鑲嵌線路。在一些雙鑲嵌製程中，首先形成溝渠，繼而再形成介層開口。
或者，可使用介層的單鑲嵌製程及線路的單鑲嵌製程形 成線路260(但ILD 259包含兩個介電層)。第二配線層級270包括在ILD層280中形成的雙鑲嵌線路275。此完成積體電路的BEOL製造。
在BEOL後，執行其他作業。在圖2G中，已執行背面研磨及/或CMP，以使基板100變薄並暴露核心255的底面290，然後完成貫穿矽介層285的製造。核心255的底面290與基板100的底面295共面。
現在可對線路275及貫穿矽介層285製作各種互連結構，諸如對核心290及線路275形成焊料凸塊連接。此類互連結構範例如圖2H中所圖解。
在圖2H中，在基板100的底面295上形成介電底部保護層300。導電底部襯墊305穿過底部保護層300的開口在貫穿矽介層285之上接觸核心255。底部焊料凸塊310在底部襯墊305上形成。導電頂部襯墊325穿過頂部保護層315的開口在線路275之上接觸線路275。頂部焊料凸塊330在頂部襯墊325上形成。儘管將單一貫穿介層285連接至襯墊305，但可將二或多個貫穿矽介層連接至襯墊305並因此共用單一底部互連線。
因此，根據本發明具體實施例之貫穿晶圓介層的製造包含以下步驟：(1)在FEOL前形成貫穿矽介層前導結構，(2)在FEOL期間藉由添加核心導體而改變貫穿矽介層前導結 構，及(3)在BEOL之後完成貫穿矽介層。
因此，本發明具體實施例提供貫穿矽介層及製造貫穿矽介層的方法，其相容於CMOS技術，且具有從積體電路晶片頂面至積體電路底面的絕緣體厚度比目前業界所得更為優異。
上述本發明具體實施例的說明是為了瞭解本發明。應明白，本發明不限於本文所述的特定具體實施例，而是在不脫離本發明範疇下，能夠進行各種修改、重新配置及替換，正如本技術人士所明白的。因此，以下申請專利範圍是用來涵蓋此種在本發明精神及範疇之內的修改及變更。
100‧‧‧基板
105、165、170、175、185‧‧‧頂面
110‧‧‧障壁層
115‧‧‧第一層
120‧‧‧第二層
125‧‧‧光阻層
130、135、250‧‧‧開口
140、140A、140B‧‧‧溝渠
141、142、143‧‧‧側壁
144‧‧‧底部
145‧‧‧二氧化矽層
150‧‧‧尖端
155‧‧‧硬遮罩層
160‧‧‧填料層
180‧‧‧介電帽蓋
190‧‧‧前導貫穿矽介層
200‧‧‧場效電晶體(FET)
205‧‧‧源極/汲極
210‧‧‧井
215‧‧‧通道區域
220‧‧‧閘極電極
225‧‧‧閘極介電質
230‧‧‧間隔物
235‧‧‧介電溝渠隔離
240‧‧‧介電保護層
245‧‧‧金屬接點
255‧‧‧導電核心
255A‧‧‧第一配線層級
257‧‧‧接點區域
260、275‧‧‧雙鑲嵌線路
265、280‧‧‧層間介電(ILD)層
270‧‧‧第二配線層級
290、295‧‧‧底面
300‧‧‧底部保護層
305‧‧‧導電底部襯墊
310‧‧‧底部焊料凸塊
315‧‧‧頂部保護層
325‧‧‧導電頂部襯墊
330‧‧‧頂部焊料凸塊
本發明的特色如隨附的申請專利範圍所述。然而，要完全瞭解本發明本身，請在連同附圖一起閱讀時，參考解說性實施例的詳細說明，圖式中：圖1A至1M根據本發明具體實施例，為圖解貫穿矽介層之初始製造步驟的橫截面圖；及圖2A至2H根據本發明具體實施例，為圖解貫穿矽介層之製造步驟整合CMOS積體電路裝置及線路之製造的橫截面圖。
100‧‧‧基板
105‧‧‧頂面
140‧‧‧溝渠
145‧‧‧二氧化矽層
155‧‧‧硬遮罩層
160‧‧‧填料層
170、175、185‧‧‧頂面
180‧‧‧介電帽蓋
190‧‧‧前導貫穿矽介層

Claims (18)

  1. 一種製造貫穿矽介層的方法，包含：(a)形成一溝渠於一矽基板中，該溝渠開啟至該基板之一頂面；(b)形成一二氧化矽層於該溝渠的側壁上，該二氧化矽層未填充該溝渠；(c)形成一硬遮罩層於該基板之頂面及該二氧化矽層之暴露表面上；(d)用多晶矽填充該溝渠中的其餘空間；(e)移除該溝渠中的上端區域之多晶矽並且形成一介電帽蓋於該溝渠中的其餘多晶矽上方；在(e)之後，(f)製造一互補金屬氧化矽(CMOS)裝置之至少一部份於該基板中；(g)自該溝渠完全移除該多晶矽，該二氧化矽層繼續留在該溝渠的該側壁上；(h)用一導電核心再填充該溝渠，該導電核心延伸至該基板之頂面上方；及在(h)之後，(i)形成自一第一配線層級至一最後配線層級的一堆疊之兩個或多個鑲嵌線路層於該基板的該頂面上，該第一配線層級之一線路接觸該導電核心之一頂面。
  2. 如申請專利範圍第1項所述之方法，另外包括：(j)從一底面薄化該基板以形成一薄化基板，在該薄化之後，該核心之一底面與該薄化基板之一底面共面。
  3. 如申請專利範圍第2項所述之方法，另外包括： 形成至該核心之該底面的一互連結構。
  4. 如申請專利範圍第3項所述之方法，其中該形成該互連結構包括：形成一介電層於該薄化基板的該底面上；形成一開口於該介電層中，該核心在該開口的一底部中暴露；形成一金屬襯墊於該介電層上；該襯墊的一周圍與該開口的一周圍重疊，該襯墊接觸該核心的該底面；及形成一焊料凸塊於該金屬襯墊上。
  5. 如申請專利範圍第1項所述之方法，其中(a)包括：形成一氧化障壁於該基板的該頂面上；形成一開口於該氧化障壁中，該基板之該頂面的一區域在該開口中暴露；及電漿蝕刻在該開口中暴露的該基板。
  6. 如申請專利範圍第1項所述之方法，其中(a)包括：形成一氧化障壁層於該基板的一頂面上；形成一圖案化光阻層於該障壁層的一頂面上；蝕刻該障壁層以暴露該基板中該障壁層未受該圖案化光阻層保護的該頂面；在蝕刻該障壁層之後，蝕刻該基板以形成該溝渠；及在蝕刻該溝渠之後及在(b)之前，移除該光阻層。
  7. 如申請專利範圍第1項所述之方法，其中該CMOS裝置係為一場 效電晶體且該(f)包括：在形成該場效電晶體之後，形成一保護層於該基板的該頂面上；形成金屬接點，其穿通該保護層而連接至該場效電晶體的一源極、一汲極及一閘極；及形成一開口於該保護層中該溝渠上方。
  8. 如申請專利範圍第7項所述之方法，其中在執行(h)之後，該核心之一上端區域係充填該保護層中之該開口。
  9. 如申請專利範圍第1項所述之方法，其中該溝渠具有與該晶圓之該頂面垂直的平直側壁及實質上一致的一寬度。
  10. 如申請專利範圍第1項所述之方法，其中該溝渠具有朝向彼此逐漸變窄的平直側壁，致使該溝渠在該溝渠之該頂面的一第一寬度大於該溝渠在該溝渠之一底部的一第二寬度。
  11. 如申請專利範圍第1項所述之方法，其中該溝渠具有遠離彼此逐漸變寬的平直側壁，致使該溝渠在該溝渠之該頂面的一第一寬度小於該溝渠在該溝渠之一底部的一第二寬度。
  12. 一種製造貫穿矽介層的方法，包含：(a)形成一氧化障壁層於一矽基板的一頂面上及形成一開口於該障壁層中，該基板之該頂面的一區域在該開口的一底部中暴露；(b)形成一溝渠於該基板未受該障壁層保護的該矽基板中，該 溝渠開啟至該基板的一頂面；(c)形成一二氧化矽層於該溝渠的側壁上，該二氧化矽層未填充該溝渠；(d)移除該氧化障壁層；(e)形成一硬遮罩層於該基板的該頂面及該二氧化矽層的所有暴露表面上；(f)用多晶矽填充該溝渠中的其餘空間，其後該多晶矽的一頂面與該硬遮罩層的一頂面共面；(g)移除該溝渠中的上端區域之多晶矽並且形成一介電帽蓋於該溝渠中的其餘多晶矽上方；在(g)之後，(h)形成一場效電晶體的一源極、一汲極及一通道區域於該基板中，一閘極介電質於該通道區域上，及一閘極電極於該閘極介電質上；(i)形成一保護層於該硬遮罩層及該場效電晶體之上；(j)形成穿過該保護層到達該場效電晶體之相應的該源極、該汲極及該閘極電極的金屬接點，該金屬接點的頂面與該保護層的一頂面共面；(k)形成一開口於該溝渠之上的該保護層中及自該溝渠完全移除該介電帽蓋及該多晶矽，該二氧化矽層及該硬遮罩層繼續留在該溝渠的該側壁上；(l)用一導電核心再填充該溝渠，該二氧化矽層及該硬遮罩層繼續留在該溝渠的該側壁上，該核心的一頂面與該保護層的該頂面共面；及在(l)之後，(m)形成自一第一配線層級至一最後配線層級的一堆疊之兩個或多個鑲嵌線路層於該保護層上，該第一配線層級中之一線路接觸該導電核心之該頂面。
  13. 如申請專利範圍第12項所述之方法，另外包括：(n)從一底面薄化該基板以形成一薄化基板，在該薄化之後，該核心之一底面與該薄化基板之一底面共面。
  14. 如申請專利範圍第13項所述之方法，另外包括：形成一介電層於該薄化基板的該底面上；形成一開口於該底部保護層中，該核心在該開口的一底部中暴露；形成一金屬襯墊於該介電層上；該襯墊的一周圍與該開口的一周圍重疊，該襯墊接觸該核心的該底面；及形成一焊料凸塊於該底部金屬襯墊上。
  15. 如申請專利範圍第12項所述之方法，其中：(a)包括形成一圖案化光阻層在該障壁層的一頂面上及蝕刻該障壁層以在該障壁層中該障壁層未受該圖案化光阻層保護處形成該開口；及(b)包括藉由電漿蝕刻在該開口中暴露的該基板而形成該溝渠，及在蝕刻該溝渠之後及在(c)之前，移除該光阻層。
  16. 如申請專利範圍第12項所述之方法，其中該溝渠具有與該晶圓之該頂面垂直的平直側壁及實質上一致的一寬度。
  17. 如申請專利範圍第12項所述之方法，其中該溝渠具有朝向彼此逐漸變窄的平直側壁，致使該溝渠在該溝渠之該頂面的一第一寬度大於該溝渠在該溝渠之一底部的一第二寬度。
  18. 如申請專利範圍第12項所述之方法，其中該溝渠具有遠離彼此逐漸變寬的平直側壁，致使該溝渠在該溝渠之該頂面的一第一寬度小於該溝渠在該溝渠之一底部的一第二寬度。
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US8637937B2 (en) 2014-01-28
US20140094007A1 (en) 2014-04-03
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US8138036B2 (en) 2012-03-20
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