US20120080802A1 - Through silicon via in n+ epitaxy wafers with reduced parasitic capacitance - Google Patents

Through silicon via in n+ epitaxy wafers with reduced parasitic capacitance Download PDF

Info

Publication number
US20120080802A1
US20120080802A1 US12/894,218 US89421810A US2012080802A1 US 20120080802 A1 US20120080802 A1 US 20120080802A1 US 89421810 A US89421810 A US 89421810A US 2012080802 A1 US2012080802 A1 US 2012080802A1
Authority
US
United States
Prior art keywords
formed
silicon via
epitaxy layer
trench
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/894,218
Inventor
Kangguo Cheng
Subramanian Iyer
Ali Khakifirooz
Pranita Kulkarni
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US12/894,218 priority Critical patent/US20120080802A1/en
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: IYER, SUBRAMANIAN, CHENG, KANGGUO, KHAKIFIROOZ, ALI, KULKARNI, PRANITA
Publication of US20120080802A1 publication Critical patent/US20120080802A1/en
Application status is Abandoned legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486Via connections through the substrate with or without pins
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/268Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device includes an epitaxy layer formed on semiconductor substrate, a device layer formed on the epitaxy layer, a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor, and a deep trench isolation structure formed within the substrate and surrounding the through-silicon via conductor. A region of the epitaxy layer formed between the through-silicon via conductor and the deep trench isolation structure is electrically isolated from any signals applied to the semiconductor device, thereby decreasing parasitic capacitance.

Description

    BACKGROUND
  • The present invention relates to integrated circuits, and more specifically, to through-silicon vias (TSVs) formed through an n+ epitaxy layer which reduces parasitic capacitance.
  • In integrated circuit technology, TSVs are used to create a vertical electrical connection (e.g., a via) passing completely through a silicon wafer or die, and can be used to connect integrated circuits together. FIG. 1 is an example of a TSV in a semiconductor device in the conventional art. As shown in FIG. 1, a semiconductor device 10 includes a semiconductor substrate 12 formed of a low dopant concentration (e.g., a p− layer) and having a device layer 14 formed on a top surface thereof. A trench 16 is etched through the substrate 12 to form a TSV and a dielectric layer 18 is deposited within the trench 16 to form a liner along sidewalls surfaces of the trench 16 for isolation purposes. The trench 16 is then filled with a conductive layer to form a TSV conductor 19.
  • FIG. 2 is another example of a TSV in a semiconductor device in the conventional art. As shown in FIG. 2, the semiconductor device 20 includes a semiconductor substrate 22 having an n+ epitaxy layer 23 formed thereon and a device layer 24 formed on the n+ epitaxy layer 23. A trench 26 is etched through the substrate 22 and a dielectric layer 18 is deposited within the trench 26 to form a liner along sidewall surfaces of the trench 26. The trench 26 is then filled with a conductive layer to form a TSV conductor 29.
  • In both examples shown in FIGS. 1 and 2, a MOS (metal oxide semiconductor) capacitor is formed. There may be several problems associated with the MOS capacitors when a n+ epitaxy layer is included as shown in FIG. 2. One of the problems includes capacitance issues. FIG. 3 is a diagram illustrating capacitance vs. gate voltage regarding the TSVs shown in FIGS. 1 and 2. As shown in FIG. 3, for voltages placed on the TSV conductor 19 (as represented by line 32) such as zero or a positive voltage, the capacitance per unit area is very low for example, approximately 1×10-8 F/cm2. On the other hand, when voltage is placed on the TSV conductor 29 (as represented by line 34), there is a significant increase in the capacitance with the inversion (as represented by arrow 36). Furthermore, when the TSV capacitor operates in the inversion mode, it introduces significant voltage and frequency dependence that thus complicates the TSV modeling.
  • In eDRAM (i.e., embedded capacitor-based dynamic random access memory) technology, it is necessary to have the n+ epitaxy layer but when combined with the TSV, capacitance significantly increases as shown in FIG. 3.
  • SUMMARY
  • According to one embodiment of the present invention, a semiconductor device is provided. The semiconductor device includes an epitaxy layer formed on semiconductor substrate, a device layer is formed on the epitaxy layer, a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor, and a deep trench isolation structure formed within the substrate and surrounding the through-silicon via conductor. A region of the epitaxy layer formed between the through-silicon via conductor and the deep trench isolation structure is electrically isolated from any signals applied to the semiconductor device, thereby decreasing parasitic capacitance.
  • According to another embodiment of the present invention, a semiconductor device is provided. The semiconductor device includes an epitaxy layer formed on a semiconductor substrate, a device layer is formed on the epitaxy layer, a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor, and a grounded through-silicon via formed within the substrate and surrounding the through-silicon via conductor. A region of the epitaxy layer formed between the through-silicon via conductor and the grounded through-silicon via is electrically isolated from any signals applied to the semiconductor device.
  • According to another embodiment of the present invention, a semiconductor device is provided. The semiconductor device includes a p-doped layer formed on a semiconductor substrate and comprising a higher dopant concentration than that of the semiconductor substrate, an epitaxy layer formed on the p-doped layer, a device layer formed on the epitaxy layer, and a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor.
  • According to another embodiment of the present invention, a semiconductor device is provided. The semiconductor device includes an epitaxy layer formed on a semiconductor substrate, a device layer 44 is formed on the epitaxy layer, a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor, and a p-doped region implanted beneath the epitaxy layer and adjacent to the through-silicon via conductor and the semiconductor substrate and comprising a higher dopant concentration than that of the semiconductor substrate.
  • According to another embodiment of the present invention, a method is provided. The method includes forming an epitaxy layer on a semiconductor substrate, forming a trench having a dielectric liner and conductive core within the trench to form a through-silicon via conductor, and implanting a p-doped region beneath the epitaxy layer and adjacent to the through-silicon via conductor.
  • Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the advantages and the features, refer to the description and to the drawings.
  • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
  • The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
  • FIG. 1 is a diagram illustrating an example of a through-silicon via for a semiconductor device in the conventional art.
  • FIG. 2 is a diagram illustrating another example of a through-silicon via for a semiconductor device including an n+ epitaxy layer in the conventional art.
  • FIG. 3 is a graph illustrating capacitance vs. gate voltage regarding the through-silicon vias shown in FIGS. 1 and 2.
  • FIG. 4 is a diagram illustrating a through-silicon via and a deep trench isolation structure for a semiconductor device that can be implemented within embodiments of the present invention.
  • FIG. 5 is a diagram illustrating a through-silicon via and a grounded through-silicon via for a semiconductor device that can be implemented within alternative embodiments of the present invention.
  • FIG. 6 is a diagram illustrating a through-silicon via and a grounded through-silicon via for a semiconductor device that can be implemented within alternative embodiments of the present invention.
  • FIG. 7 is a diagram illustrating a through-silicon via and a p-doped layer formed beneath the n+ epitaxy layer in a semiconductor device that can be implemented within alternative embodiments of the present invention.
  • FIG. 8 is a diagram illustrating a through-silicon via and an implanted p-doped region beneath the n+ epitaxy layer and adjacent to the through-silicon via in a semiconductor device that can be implemented within alternative embodiments of the present invention.
  • FIG. 9 is a diagram illustrating a method of implanting the p-doped region beneath the n+ epitaxy layer and adjacent to the through-silicon via as shown in FIG. 8 that can be implemented within embodiments of the present invention.
  • FIG. 10 is a diagram illustrating a method of implanting the p-doped region beneath the n+ epitaxy layer and adjacent to the through-silicon via as shown in FIG. 8 that can be implemented within alternative embodiments of the present invention.
  • FIG. 11 is a graph illustrating capacitance vs. gate voltage regarding the through-silicon vias implemented within embodiments of the present invention.
  • DETAILED DESCRIPTION
  • It is desirable to have an n+ epitaxy layer within an eDRAM, without the increased parasitic capacitance for the through-silicon-via (TSV) structures. Embodiments of the present invention provide semiconductor devices including n+ epitaxy layers and alternative ways for reducing the TSV capacitance. FIG. 4 is a diagram illustrating a through-silicon via and a deep trench isolation structure for a semiconductor device that can be implemented within embodiments of the present invention. As shown in FIG. 4, a semiconductor device 40 is provided. A semiconductor substrate 42 is formed. The semiconductor substrate 42 is formed of a low dopant concentration (e.g., a p− layer). The semiconductor substrate 42 may be formed of silicon (Si), but is not limited hereto and may be formed of any semiconductor material. An epitaxy layer 43 (e.g., an n+ epitaxy layer) is formed on the semiconductor substrate 42 and a device layer 44 is formed on the epitaxy layer 43. According to an embodiment of the present invention, the n+ epitaxy layer 43 is formed of a predetermined thickness usually ranging from approximately 1 micrometer to approximately 10 micrometers. Further, the n+ epitaxy layer 43 has a doping level above approximately 1×1019 atoms/cm3.
  • A through-silicon via (TSV) is also formed within the semiconductor substrate 42. As shown in FIG. 4, a trench 45 is etched through the substrate 42 using a reactive ion etch (RIE) process, for example. According to an embodiment of the present invention, the trench 45 is between approximately 2 micrometers and approximately 10 micrometers in diameter and a depth in the range of approximately 20 micrometer to 50 micrometers.
  • The trench 45 is then lined with a dielectric layer 46 for isolation purposes. According to an embodiment of the present invention, the dielectric layer 46 may be formed of silicon dioxide (SiO2) or silicon nitride (SiN), for example, and may have a thickness of between approximately 50 nanometers (nm) to approximately 100 nanometers (nm). The trench 45 is then filled with an electrically conductive material such as copper or tungsten, for example, to thereby form a TSV conductor 47. Depending on the requirements of the process flow, the formation and filling of the trench can be performed before or after other devices are formed as known in the art. According to this embodiment of the present invention, a deep trench isolation structure 48 surrounds the TSV conductor 47. That is, the deep trench isolation structure 48 is formed as a ring around the TSV conductor 47. As shown in FIG. 4, region 43 a of the n+ epitaxy layer between the deep trench isolation structure 48 and the TSV conductor 47 is electrically isolated from any signals applied to the semiconductor device 40, therefore the TSV capacitance cannot go to inversion mode since there is no source to supply minority carriers (i.e., electrons). Hence, at high frequencies e.g., above approximately 10 kHz and thus for any practical purpose the TSV capacitance operates in the depletion mode and not inversion mode. Further, the region 43 a of the epitaxy layer 43 is formed of a predetermined thickness ranging from approximately 1 micrometer to approximately 10 micrometers. The present invention is not limited to the use of a deep trench isolation structure as shown in FIG. 4 to reduce parasitic capacitance. Other embodiments of the present invention will now be described below with reference to FIGS. 5 through 8.
  • FIG. 5 is a diagram illustrating a through-silicon via and an isolating through-silicon via for a semiconductor device 50 that can be implemented within alternative embodiments of the present invention. As shown in FIG. 5, a semiconductor substrate 52 is formed. An n+ epitaxy layer 53 is formed on the semiconductor substrate 52. A device layer 54 is then formed on the n+ epitaxy layer 53. A plurality of trenches 55 and 56 are etched within the semiconductor substrate 52 using an etching process. These trenches 55 and 56 are then lined with a dielectric layer 57. The trench 55 is filled with an electrically conductive material to form a signal TSV 58. The trench 56 is also filled with the conductive material and used to form an isolating TSV 59 surrounding the TSV conductor 58. Therefore, similar to FIG. 4, a region 53 a of the n+ epitaxy layer 53 between the isolating TSV 59 and the signal TSV 58 is electrically isolated to prevent the TSV capacitance from going to inversion mode. According to an embodiment of the present invention, the region 53 a of the n+ epitaxy layer 53 is formed of a predetermined thickness ranging from approximately 1 micrometer to approximately 10 micrometers. The isolating TSV 59 is preferably grounded to reduce the noise coupling between different devices and signal TSV 58. However, it can be kept floating if desired. As shown in FIG. 5, according to an embodiment of the present invention, the isolating TSV 59 is of a length and width comparable to that the signal TSV 58. However, the present invention is not limited to the isolating TSV 59 being of a particular length or width. An alternative embodiment of the isolating TSV 59 will now be discussed with reference to FIG. 6.
  • FIG. 6 is a diagram illustrating a through-silicon via and an isolating through-silicon via for a semiconductor device 60 that can be implemented within alternative embodiments of the present invention. As shown in FIG. 6, a semiconductor substrate 62 is provided. An n+ epitaxy layer 63 is formed on the semiconductor substrate 62. A device layer 64 is then formed on the n+ epitaxy layer 63. A plurality of trenches 65 and 66 are etched through the semiconductor substrate 62 using an etching process. According to an embodiment of the present invention, the trench 66 is etched narrower than that of the trench 65 and is thus has less depth due to loading effect in the etch process. A dielectric liner 67 is then formed within each trench 65 and 66. An electrically conductive material is then deposited within the trench 65 to form a signal TSV 68. An isolating TSV 69 is formed within the trench 66. The isolating TSV 69 has the same effect as that shown in FIG. 5. That is, a region 63 a of the n+ epitaxy layer 63 is electrically isolated to prevent an increase in parasitic capacitance when voltage is applied to the signal TSV 68. Since the isolating 69 (in FIG. 6) is made narrower than the isolating TSV 59 (in FIG. 7) it adds less area penalty. Yet, it has similar effect in preventing the TSV capacitance from operating in the inversion mode and thus reduces the parasitic capacitance.
  • FIG. 7 is a diagram illustrating a through-silicon via and a p-doped layer formed beneath the n+ epitaxy layer in a semiconductor device 70 that can be implemented within alternative embodiments of the present invention. As shown in FIG. 7, a semiconductor substrate 71 formed of a low dopant concentration (e.g., a p− layer) is provided. A p-doped layer 72 formed on the semiconductor substrate 71. An n+ epitaxy layer 73 is formed on the p-doped layer 72 and a device layer 74 is formed on the n+ epitaxy layer 73. A through-silicon via is formed within the semiconductor substrate 71. The through-silicon via is formed by etching a trench 75 through the semiconductor substrate 71 and depositing a dielectric layer 76 to form a liner on the sidewalls within the trench 75. The trench 75 is then filled with an electrically conductive material to form a through-silicon via conductor 77. According to an embodiment of the present invention, the p-doped layer 72 is formed without been deactivated by the n+ diffusion. Further, the p-doped layer 72 is formed of a higher dopant concentration than the semiconductor substrate 71, thereby increasing a threshold voltage of the semiconductor device and decreasing the parasitic capacitance (as depicted in FIG. 11 (line 95)). According to an embodiment of the present invention, the p-doped layer 72 is of a predetermined width ranging from approximately 200 nanometer to approximately 2 micrometer and includes a doping concentration of 1×1018 atoms/cm3 or greater. According to an embodiment of the present invention, it is not necessary for the p-doped layer to be formed over the entire surface of the semiconductor substrate in order to increase the threshold voltage. An alternative embodiment will now be discussed below with reference to FIG. 8.
  • FIG. 8 is a diagram illustrating a through-silicon via and an implanted p-doped region beneath the n+ layer and adjacent to the through-silicon via in a semiconductor device 80 that can be implemented within alternative embodiments of the present invention. As shown in FIG. 8, a semiconductor substrate 81 is provided. The semiconductor substrate is formed of a low dopant concentration. An n+ epitaxy layer 82 is formed on the semiconductor substrate 81 and a device layer 83 is formed on the n+ epitaxy layer. A through-silicon via is then formed by etching a trench 85 through the semiconductor substrate 81 and depositing a dielectric layer 86 to form a liner on sidewalls surfaces within the trench 85. The trench 85 is then filled with an electrically conductive material to form a through-silicon via conductor 87. A p-doped region 90 implanted beneath the n+ epitaxy layer and adjacent to the through-silicon via conductor 87 and formed of a higher dopant concentration than that of the semiconductor substrate 81, to increase threshold voltage of the semiconductor device and in turn lower the parasitic capacitance. According to an embodiment of the present invention, p-doped region 90 is of a predetermined width ranging from approximately 200 nanometer to approximately 2 micrometer and includes a doping concentration of 1×1018 atoms/cm3 or greater. Methods for implanting the p-doped region 90 will be discussed below with reference to FIGS. 9 and 10.
  • As shown in FIGS. 9 and 10, the p-doped region 90 is formed by forming a photo resist layer 84 on the device layer and performing angled implantation of p-dopants after the trench 85 is formed. The implantation is performed from various angles, at least four different angles (the so-called “quad” implant), for example, 0°, 90°, 180°, and 270°. Other “quad” implant direction, such as 45°, 135°, 225°, 315° can be also used. The implantation of the p dopants is formed at a predetermined implantation depth ‘A’ just beneath the n+ epitaxy layer 82 by proper tilting of the implant. According to an embodiment of the present invention, the p dopants may comprise boron (B) or indium (In), for example. In FIG. 9, the implantation of p-dopants is performed prior to depositing the dielectric layer 86 within the trench 85. In FIG. 10, the implantation of p-dopants is performed after depositing the dielectric layer 86 within the trench 85. In both cases a “diffusion-less” process is used to activate the p doping without causing significant diffusion of the n+ doping from the n+ epitaxy layer 82 into the p-doped region. This can be done by annealing at low temperatures so that the n+ dopants do not diffuse or by a laser annealing, for example.
  • FIG. 11 is a graph 100 illustrating capacitance vs. gate voltage regarding the through-silicon vias implemented within embodiments of the present invention. As shown in FIG. 11, and discussed above with reference to FIG. 2, the semiconductor device having an n+ epitaxy layer shows increased parasitic capacitance (as indicated by line 90). The use of an n+ epitaxy and a p doped layer or region adjacent to the through-silicon via and having a dopant concentration higher than that of the semiconductor substrate increasing the threshold voltage while decreasing the parasitic capacitance.
  • Thus, embodiments of the present invention provide a way to use n+ epitaxy layer within eDRAM technology, for example, while reducing parasitic capacitance. By preventing the TSV capacitance from operating in the inversion mode, these embodiments also remove the voltage and frequency dependency of the TSV capacitance and simplify the device modeling.
  • The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, element components, and/or groups thereof.
  • The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
  • The flow diagrams depicted herein are just one example. There may be many variations to this diagram or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention.
  • While the preferred embodiment to the invention had been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.

Claims (20)

1. A semiconductor device comprising:
an epitaxy layer formed on a semiconductor substrate;
a device layer formed on the epitaxy layer;
a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor; and
a deep trench isolation structure formed within the substrate and surrounding the through-silicon via conductor wherein a region of the epitaxy layer formed between the through-silicon via conductor and the deep trench isolation structure is electrically isolated from any signals applied to the semiconductor device.
2. The semiconductor device of claim 1, wherein the region of the epitaxy layer is formed of a predetermined thickness ranging from approximately 1 micrometer to approximately 10 micrometers.
3. The semiconductor device of claim 1, wherein the epitaxy layer is an n+ epitaxy layer.
4. The semiconductor device of claim 3, wherein the epitaxy layer has a doping level of about 1×1019 atoms/cm3 or greater.
5. A semiconductor device comprising:
an epitaxy layer formed on a semiconductor substrate;
a device layer formed on the epitaxy layer;
a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor; and
an isolating through-silicon via formed within the substrate and surrounding the through-silicon via conductor wherein a region of the epitaxy layer formed between the through-silicon via conductor and the grounded through-silicon via is electrically isolated from any signals applied to the semiconductor device.
6. The semiconductor device of claim 5, wherein the through-silicon via conductor and the isolating through-silicon via are of a same length and width.
7. The semiconductor device of claim 5, wherein the through-silicon via conductor is of a larger length and width than that of the isolating through-silicon via.
8. The semiconductor device of claim 5, wherein the region of the epitaxy layer is formed of a predetermined thickness ranging from approximately 1 micrometer to approximately 10 micrometers.
9. The semiconductor device of claim 5, wherein the epitaxy layer is an n+ epitaxy layer.
10. The semiconductor device of claim 9, wherein the epitaxy layer has a doping level above approximately of about 1×1019 atoms/cm3 or greater.
11. A semiconductor device comprising:
a p-doped layer formed on a semiconductor substrate and comprising a higher dopant concentration than that of the semiconductor substrate;
an epitaxy layer formed on the p-doped layer;
a device layer formed on the epitaxy layer; and
a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor.
12. The semiconductor device of claim 11, wherein the p-doped layer is of a predetermined width ranging from approximately 200 nanometer to approximately 2 micrometer and includes a doping concentration of 1×1018 atoms/cm3 or greater.
13. A semiconductor device comprising:
an epitaxy layer formed on a semiconductor substrate;
a device layer formed on the epitaxy layer;
a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor; and
a p-doped region implanted beneath the epitaxy layer and adjacent to the through-silicon via conductor and the semiconductor substrate and comprising a higher dopant concentration than that of the semiconductor substrate.
14. The semiconductor device of claim 13, wherein the p-doped region is of a predetermined width ranging from approximately 200 nanometer to approximately 2 micrometers and includes a doping concentration of 1×1018 atoms/cm3 or greater.
15. A method comprising:
forming an epitaxy layer on a semiconductor substrate;
forming a trench having a dielectric liner and conductive core within the trench to form a through-silicon via conductor; and
implanting a p-doped region beneath the epitaxy layer and adjacent to the through-silicon via conductor.
16. The method of claim 15, wherein, the p-doped region is formed by performing angled implantation p dopants.
17. The method of claim 16, wherein the p dopants comprise boron (B) or Indium (In).
18. The method of claim 16, wherein the angled implantation is performed after the trench is formed and prior to forming the dielectric liner within the trench.
19. The method of claim 16, wherein the angled implantation is performed after the trench and the dielectric liner are formed.
20. The method of claim 16, wherein the angled implantation is performed from at least four different angles.
US12/894,218 2010-09-30 2010-09-30 Through silicon via in n+ epitaxy wafers with reduced parasitic capacitance Abandoned US20120080802A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/894,218 US20120080802A1 (en) 2010-09-30 2010-09-30 Through silicon via in n+ epitaxy wafers with reduced parasitic capacitance

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/894,218 US20120080802A1 (en) 2010-09-30 2010-09-30 Through silicon via in n+ epitaxy wafers with reduced parasitic capacitance
US13/743,882 US9029988B2 (en) 2010-09-30 2013-01-17 Through silicon via in n+ epitaxy wafers with reduced parasitic capacitance
US14/632,531 US9748114B2 (en) 2010-09-30 2015-02-26 Method for forming through silicon via in N+ epitaxy wafers with reduced parasitic capacitance

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US13/743,882 Division US9029988B2 (en) 2010-09-30 2013-01-17 Through silicon via in n+ epitaxy wafers with reduced parasitic capacitance

Publications (1)

Publication Number Publication Date
US20120080802A1 true US20120080802A1 (en) 2012-04-05

Family

ID=45889098

Family Applications (3)

Application Number Title Priority Date Filing Date
US12/894,218 Abandoned US20120080802A1 (en) 2010-09-30 2010-09-30 Through silicon via in n+ epitaxy wafers with reduced parasitic capacitance
US13/743,882 Active 2030-12-20 US9029988B2 (en) 2010-09-30 2013-01-17 Through silicon via in n+ epitaxy wafers with reduced parasitic capacitance
US14/632,531 Active US9748114B2 (en) 2010-09-30 2015-02-26 Method for forming through silicon via in N+ epitaxy wafers with reduced parasitic capacitance

Family Applications After (2)

Application Number Title Priority Date Filing Date
US13/743,882 Active 2030-12-20 US9029988B2 (en) 2010-09-30 2013-01-17 Through silicon via in n+ epitaxy wafers with reduced parasitic capacitance
US14/632,531 Active US9748114B2 (en) 2010-09-30 2015-02-26 Method for forming through silicon via in N+ epitaxy wafers with reduced parasitic capacitance

Country Status (1)

Country Link
US (3) US20120080802A1 (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8492272B2 (en) * 2011-07-29 2013-07-23 International Business Machines Corporation Passivated through wafer vias in low-doped semiconductor substrates
CN103456683A (en) * 2012-05-30 2013-12-18 三星电子株式会社 Methods of forming a through via structure, image sensor and integrated circuit
US20140054743A1 (en) * 2012-08-24 2014-02-27 Newport Fab, Llc Dba Jazz Semiconductor Isolated Through Silicon Vias in RF Technologies
US20140118059A1 (en) * 2012-11-01 2014-05-01 International Business Machines Corporation Through-substrate via shielding
US20140284690A1 (en) * 2013-03-22 2014-09-25 Kabushiki Kaisha Toshiba Semiconductor device
US8878369B2 (en) 2011-08-15 2014-11-04 Taiwan Semiconductor Manufacturing Co., Ltd. Low power/high speed TSV interface design
US20150061083A1 (en) * 2013-09-03 2015-03-05 Realtek Semiconductor Corp. Metal trench de-noise structure and method for forming the same
US20150200152A1 (en) * 2014-01-16 2015-07-16 Samsung Electronics Co., Ltd. Semiconductor device and method for fabricating the same
US9257322B2 (en) * 2012-07-04 2016-02-09 Industrial Technology Research Institute Method for manufacturing through substrate via (TSV), structure and control method of TSV capacitance
US9613864B2 (en) 2014-10-15 2017-04-04 Micron Technology, Inc. Low capacitance interconnect structures and associated systems and methods
US20170207169A1 (en) * 2013-09-09 2017-07-20 Taiwan Semiconductor Manufacturing Company, Ltd. Backside Contacts for Integrated Circuit Devices
US9847290B1 (en) * 2016-12-12 2017-12-19 Globalfoundries Inc. Through-silicon via with improved substrate contact for reduced through-silicon via (TSV) capacitance variability
USRE47709E1 (en) * 2011-07-07 2019-11-05 Taiwan Semiconductor Manufacturing Company, Ltd. Forming grounded through-silicon vias in a semiconductor substrate

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170017122A (en) 2015-08-05 2017-02-15 삼성전자주식회사 Semiconductor device
US9966318B1 (en) * 2017-01-31 2018-05-08 Stmicroelectronics S.R.L. System for electrical testing of through silicon vias (TSVs)
CN109300877A (en) * 2018-08-27 2019-02-01 北京大学 Through-hole structure and its manufacturing method in a kind of semiconductor substrate

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050199980A1 (en) * 2004-03-09 2005-09-15 Hirokazu Fujimaki Semiconductor device and method of manufacturing same
US20100224965A1 (en) * 2009-03-09 2010-09-09 Chien-Li Kuo Through-silicon via structure and method for making the same
US7871925B2 (en) * 2006-09-30 2011-01-18 Hynix Semiconductor Inc. Stack package and method for manufacturing the same
US8110900B2 (en) * 2008-01-29 2012-02-07 Renesas Electronics Corporation Manufacturing process of semiconductor device and semiconductor device

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5858845A (en) 1994-09-27 1999-01-12 Micron Technology, Inc. Electrically conductive substrate interconnect continuity region and method of forming same with an angled implant
US6551857B2 (en) 1997-04-04 2003-04-22 Elm Technology Corporation Three dimensional structure integrated circuits
US5915167A (en) 1997-04-04 1999-06-22 Elm Technology Corporation Three dimensional structure memory
US6509240B2 (en) 2000-05-15 2003-01-21 International Rectifier Corporation Angle implant process for cellular deep trench sidewall doping
US7253477B2 (en) 2005-02-15 2007-08-07 Semiconductor Components Industries, L.L.C. Semiconductor device edge termination structure
US7679146B2 (en) 2006-05-30 2010-03-16 Semiconductor Components Industries, Llc Semiconductor device having sub-surface trench charge compensation regions
US7701057B1 (en) * 2007-04-25 2010-04-20 Xilinx, Inc. Semiconductor device having structures for reducing substrate noise coupled from through die vias
US7843064B2 (en) 2007-12-21 2010-11-30 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and process for the formation of TSVs
US7833895B2 (en) 2008-05-12 2010-11-16 Texas Instruments Incorporated TSVS having chemically exposed TSV tips for integrated circuit devices
US8334170B2 (en) 2008-06-27 2012-12-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method for stacking devices
US8138036B2 (en) 2008-08-08 2012-03-20 International Business Machines Corporation Through silicon via and method of fabricating same
US8502338B2 (en) * 2010-09-09 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate via waveguides

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050199980A1 (en) * 2004-03-09 2005-09-15 Hirokazu Fujimaki Semiconductor device and method of manufacturing same
US7871925B2 (en) * 2006-09-30 2011-01-18 Hynix Semiconductor Inc. Stack package and method for manufacturing the same
US8110900B2 (en) * 2008-01-29 2012-02-07 Renesas Electronics Corporation Manufacturing process of semiconductor device and semiconductor device
US20100224965A1 (en) * 2009-03-09 2010-09-09 Chien-Li Kuo Through-silicon via structure and method for making the same

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE47709E1 (en) * 2011-07-07 2019-11-05 Taiwan Semiconductor Manufacturing Company, Ltd. Forming grounded through-silicon vias in a semiconductor substrate
US8492272B2 (en) * 2011-07-29 2013-07-23 International Business Machines Corporation Passivated through wafer vias in low-doped semiconductor substrates
US8878369B2 (en) 2011-08-15 2014-11-04 Taiwan Semiconductor Manufacturing Co., Ltd. Low power/high speed TSV interface design
CN103456683A (en) * 2012-05-30 2013-12-18 三星电子株式会社 Methods of forming a through via structure, image sensor and integrated circuit
US9257322B2 (en) * 2012-07-04 2016-02-09 Industrial Technology Research Institute Method for manufacturing through substrate via (TSV), structure and control method of TSV capacitance
US9577035B2 (en) * 2012-08-24 2017-02-21 Newport Fab, Llc Isolated through silicon vias in RF technologies
US20140054743A1 (en) * 2012-08-24 2014-02-27 Newport Fab, Llc Dba Jazz Semiconductor Isolated Through Silicon Vias in RF Technologies
US20140118059A1 (en) * 2012-11-01 2014-05-01 International Business Machines Corporation Through-substrate via shielding
US20150035589A1 (en) * 2012-11-01 2015-02-05 International Business Machines Corporation Through-substrate via shielding
US9070698B2 (en) * 2012-11-01 2015-06-30 International Business Machines Corporation Through-substrate via shielding
US9177923B2 (en) * 2012-11-01 2015-11-03 International Business Machines Corporation Through-substrate via shielding
CN103811440A (en) * 2012-11-01 2014-05-21 国际商业机器公司 Semiconductor apparatus and formation method thereof, and a semiconductor circuit and application method thereof
JP2014187183A (en) * 2013-03-22 2014-10-02 Toshiba Corp Semiconductor device
US9705009B2 (en) * 2013-03-22 2017-07-11 Kabushiki Kaisha Toshiba Semiconductor device
US20140284690A1 (en) * 2013-03-22 2014-09-25 Kabushiki Kaisha Toshiba Semiconductor device
US9978638B2 (en) * 2013-09-03 2018-05-22 Realtek Semiconductor Corp. Metal trench de-noise structure and method for forming the same
US20150061083A1 (en) * 2013-09-03 2015-03-05 Realtek Semiconductor Corp. Metal trench de-noise structure and method for forming the same
US20170207169A1 (en) * 2013-09-09 2017-07-20 Taiwan Semiconductor Manufacturing Company, Ltd. Backside Contacts for Integrated Circuit Devices
US10083910B2 (en) * 2013-09-09 2018-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Backside contacts for integrated circuit devices
US20150200152A1 (en) * 2014-01-16 2015-07-16 Samsung Electronics Co., Ltd. Semiconductor device and method for fabricating the same
US9418915B2 (en) * 2014-01-16 2016-08-16 Samsung Electronics Co., Ltd. Semiconductor device and method for fabricating the same
US9911653B2 (en) 2014-10-15 2018-03-06 Micron Technology, Inc. Low capacitance interconnect structures and associated systems and methods
US9613864B2 (en) 2014-10-15 2017-04-04 Micron Technology, Inc. Low capacitance interconnect structures and associated systems and methods
US9847290B1 (en) * 2016-12-12 2017-12-19 Globalfoundries Inc. Through-silicon via with improved substrate contact for reduced through-silicon via (TSV) capacitance variability
TWI645531B (en) * 2016-12-12 2018-12-21 格羅方德半導體公司 Through-silicon via with improved substrate contact for reduced through-silicon via (tsv) capacitance variability
US10446484B2 (en) * 2016-12-12 2019-10-15 Globalfoundries Inc. Through-silicon via with improved substrate contact for reduced through-silicon via (TSV) capacitance variability

Also Published As

Publication number Publication date
US20130127067A1 (en) 2013-05-23
US20150179548A1 (en) 2015-06-25
US9748114B2 (en) 2017-08-29
US9029988B2 (en) 2015-05-12

Similar Documents

Publication Publication Date Title
US5410176A (en) Integrated circuit with planarized shallow trench isolation
US6429477B1 (en) Shared body and diffusion contact structure and method for fabricating same
US6350653B1 (en) Embedded DRAM on silicon-on-insulator substrate
KR100372872B1 (en) Patterned SOI Regions On Semiconductor Chips
US5894152A (en) SOI/bulk hybrid substrate and method of forming the same
US6239472B1 (en) MOSFET structure having improved source/drain junction performance
US6593612B2 (en) Structure and method for forming a body contact for vertical transistor cells
EP1213757B1 (en) Integrated circuits having adjacent p-type doped regions having shallow trench isolation structures without liner layers therebetween and methods of forming same
US20100102420A1 (en) Semiconductor device and method for manufacturing the same
US20090236662A1 (en) Guard ring structures for high voltage cmos/low voltage cmos technology using ldmos (lateral double-diffused metal oxide semiconductor) device fabrication
US7750429B2 (en) Self-aligned and extended inter-well isolation structure
DE60036410T2 (en) Methods for generating a field effect transistor structure with partially isolated source / drain transitions
US20010044193A1 (en) Isolation structure and process therefor
US20030040154A1 (en) Novel DRAM access transistor
US20060244093A1 (en) Sti formation in semiconductor device including soi and bulk silicon regions
US8264038B2 (en) Buried floating layer structure for improved breakdown
JP3431734B2 (en) Soi field effect transistor and manufacturing method thereof
US20090236691A1 (en) Deep trench (dt) metal-insulator-metal (mim) capacitor
US6172390B1 (en) Semiconductor device with vertical transistor and buried word line
US5466630A (en) Silicon-on-insulator technique with buried gap
US6297088B1 (en) Method for forming a deep trench capacitor of a dram cell
US5759907A (en) Method of making large value capacitor for SOI
CN100466263C (en) Low-cost deep trench decoupling capacitor device and the manufacturing method thereof
TWI276156B (en) Formation of active area using semiconductor growth process without STI integration
US9018078B2 (en) Method of making a 3D integrated circuit

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHENG, KANGGUO;IYER, SUBRAMANIAN;KHAKIFIROOZ, ALI;AND OTHERS;SIGNING DATES FROM 20100914 TO 20100923;REEL/FRAME:025119/0850

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION