CN102655136B - 半导体芯片及其制造方法 - Google Patents

半导体芯片及其制造方法 Download PDF

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Publication number
CN102655136B
CN102655136B CN201210142303.8A CN201210142303A CN102655136B CN 102655136 B CN102655136 B CN 102655136B CN 201210142303 A CN201210142303 A CN 201210142303A CN 102655136 B CN102655136 B CN 102655136B
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insulation layer
semi
substrate
conductive pole
pole body
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CN102655136A (zh
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孙皓荣
吴卓根
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SK Hynix Inc
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Hynix Semiconductor Inc
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Abstract

本发明提供一种半导体芯片及其制造方法，该半导体芯片包括：衬底，具有前表面和与前表面相对的后表面；导电柱体部，从前表面到后表面穿过衬底；空腔，通过去除导电柱体部的端部周围的部分后表面形成，使得导电柱体部的端部从空腔突出；第一绝缘层，形成在空腔中，使得导电柱体部的端部的一部分暴露；以及后电极，电连接至导电柱体部的暴露端部。

Description

半导体芯片及其制造方法
技术领域
本发明的示例性实施例涉及一种半导体芯片及其制造方法，并且尤其涉及一种能够用于电子产品中的半导体芯片以及包括形成硅通路(TSV)的制造方法，所述电子产品具有重量轻、结构纤薄以及尺寸紧凑的特征。
背景技术
随着更高性能的电子产品以小尺寸制作以及便携式移动产品的需求增加，对于具有高容量的超微型半导体存储器的需求日益增加。一般而言，为了增加半导体存储器的存储容量，可以采用通过增加半导体芯片的集成度来增加半导体存储器的存储容量的方法以及在一个半导体封装体内安装和组合多个半导体芯片的方法。在前者情况下，需要大量的努力、成本和时间。然而，在后者情况下，可以仅通过改变封装方法来增加半导体存储器的存储容量。而且，与前者情况相比，由于后者情况在需要的成本和研发努力以及时间方面具有优势，因此半导体存储器制造公司努力通过多芯片封装来增加半导体存储器的存储容量，在所述多芯片封装中将多个半导体芯片安装在一个半导体封装体内。
在一个半导体封装体内安装多个半导体芯片的方法可分为水平安装半导体芯片的方法和垂直安装半导体芯片的方法。但是，为了保持电子产品的微型化趋势，大多数半导体存储器制造公司采用将半导体芯片垂直堆叠的堆叠式多芯片封装体。
典型地，在堆叠封装体中采用硅通路(TSV)的封装结构。采用硅通路(TSV)的封装体具有这样的结构，其中在晶片级的每个芯片中形成硅通路，并且通过硅通路进行芯片之间的物理和电气连接。为了应对多功能和高性能的移动设备等，已经积极地进行了关于采用电极的封装体的研究。
图1是现有技术的硅通路的剖面图。参考图1，硅晶片10的硅通路12包括前电极14、后电极16以及绝缘层18，绝缘层18用于实质上防止硅和后电极16之间的漏电流。由于硅通路12的直径随着半导体部件变小而减小，因此绝缘层18的开口18a也需要变小。如果绝缘层18的开口18a不变小，则会出现硅漏电部分10a，从而导致漏电流。为了实质上防止漏电流，可能需要采用短波长的光刻工艺和表面平坦化。但是，这种设备很昂贵，从而导致产品成本增加。
发明内容
本发明的实施例总体涉及半导体，并且尤其涉及半导体芯片及其制造方法，其即使在硅通路的直径减少时也能够有效地防止漏电流，而无关于包括昂贵的光刻设备的设备进步。
在本发明的一个实施例中，衬底包括前表面和与前表面相对的后表面。导电柱体部从前表面到后表面穿过衬底，并且通过去除导电柱体部的端部周围的一部分后表面可形成空腔，使得导电柱体部的端部从空腔中突出。第一绝缘层形成在空腔中，使得导电柱体部的端部的一部分暴露，并且后电极电连接至导电柱体部的暴露端部。
本发明的另一个实施例可包括一种在衬底中形成导电柱体部的方法，该衬底具有前表面和与前表面相反的后表面，并且该导电柱从前表面到后表面穿过衬底。通过去除导电柱体部的端部周围的一部分衬底可形成空腔，并且通过填充空腔的至少一部分形成第一绝缘层。然后，可形成后电极以电连接至导电柱体部的端部。
附图说明
根据以下结合附图的详细描述，可更清楚地理解以上及其它方面、特征和其它优点，在附图中：
图1是根据现有技术的硅通路的剖面图；
图2a至图2e是示出根据本发明的一个实施例的用于制造半导体芯片的示例性方法的剖面图；
图3a至图3e是示出根据本发明的另一个实施例的用于制造半导体芯片的示例性方法的剖面图；
图4a至图4c是示出根据本发明的另一个实施例的用于制造半导体芯片的示例性方法的剖面图；
图5a至图5c是示出根据本发明的另一个实施例的用于制造半导体芯片的示例性方法的剖面图；
图6a至图6d是示出根据本发明的另一个实施例的用于制造示例性半导体芯片的方法的剖面图；以及
图7是示出根据本发明的一个实施例的示例性堆叠封装体的剖面图。
具体实施方式
本发明的实施例将通过参考附图进行说明。然而，所述实施例仅用于示范性的目的，而不会限制本发明的范围。
在根据本发明的一个实施例的半导体芯片中，衬底形成有硅通路，并且硅通路可包括柱体部、后电极和后电极下的绝缘层。所述绝缘层可包括一个或更多个绝缘层(第一绝缘层、第二绝缘层等)，并且可填充整个或者一部分的空腔，所述空腔通过去除柱体部的一侧端部周围的衬底而获得。
第一绝缘层可涂覆空腔的下表面并且同时涂覆衬底的后表面，可形成为填充整个空腔，或者可形成为填充一部分的空腔。第一绝缘层和/或第二绝缘层可由有机绝缘材料或者无机绝缘材料形成，所述有机绝缘材料例如包括光致抗蚀剂、热固化树脂以及光固化树脂等。第一绝缘层和/或第二绝缘层可由实质上彼此相同的材料或不同的材料形成。此外，柱体部可包括多个柱体。
本发明的不同实施例将通过参考附图进行说明。图2a至图2f是示出根据本发明的一个实施例的用于制造半导体芯片的方法的剖面图。
参考图2a，通过在衬底100中制作孔并且再用导电材料填充孔，在衬底100中形成柱体部104。衬底100包括前表面100a以及与前表面100a相对的后表面100b。如图所示，第一前绝缘膜102和前电极106等可位于前表面100a上。
衬底100将封装体中的半导体芯片电连接至外部印刷电路板(PCB)，并且可包括用于支撑半导体芯片的封装衬底、印刷电路板自身或者形成半导体芯片的晶片。就材料而言，衬底100可以是例如陶瓷衬底，包括环氧芯和电互连等的塑料衬底，或者将互连等形成在背衬材料(backingmaterial)上的晶片，所述背衬材料例如由硅(Si)、砷化镓(GaAs)、钽酸锂(LiTaO3)、铌酸锂(LiNbO3)以及蓝宝石等制成。方便起见，衬底100将描述为硅晶片。
举例而言，柱体部104中的导电材料可包括一种或更多种金属以及导电有机材料等，例如，金(Au)、银(Ag)、铜(Cu)、铝(Al)、镍(Ni)、钨(W)、钛(Ti)、铂(Pt)、钯(Pd)、锡(Sn)、铅(Pb)、锌(Zn)、铟(In)、镉(Cd)、铬(Cr)和钼(Mo)。导电材料也可用于多层结构中以及单层结构中。此外，导电材料可填充穿过衬底100的孔的整个或一部分。
根据用于形成柱体部104的方法的示例，在衬底100的前表面100a上可形成接合焊盘(没有示出)，并且在接合焊盘的邻近部分上形成孔。凹槽可通过采用诸如激光钻孔或深反应离子刻蚀(DRIE)的方法形成，并且可具有垂直形状或锥形形状。而且，在形成孔后，可进行化学处理或物理处理以去除形成孔的残留物，并且适当地进行后续的电镀工艺，从而改善镀层粘附性。然后，形成种子金属膜，并且通过电解电镀在孔中填充导电材料，从而形成柱体部104。
参考图2b，后表面100b的一部分被去除，以暴露柱体部的端部104b。去除的部分可在后表面100b上留下空腔C。部分的后表面100b可例如通过研磨工艺去除，并且所述研磨工艺可执行为使得暴露的端部104b与衬底的后表面100b齐平。可通过用于制造半导体器件的典型研磨设备执行研磨工艺。例如，可通过包括装载区、粗磨区、精磨区以及卸载区等的研磨设备，按照粗磨装载的衬底的后表面100b、用于平滑地研磨衬底的后表面100b的精磨以及用于卸载衬底的卸载的顺序，执行研磨工艺。
承载晶片可采用粘附层而粘贴到前表面100a，然而图2b中没有示出。例如，承载晶片可以由玻璃材料或硅材料形成。承载晶片被暂时粘贴以便于对后表面100b被去除预定厚度之后减薄的衬底100进行处理，并且采用粘附层而被粘贴，所述粘附层包括以后可容易去除的粘附剂。
具有预定深度和宽度的空腔C形成在柱体部的一侧端部104b的周围，以允许柱体部的一侧端部104b从衬底的后表面100b突出。柱体部的侧表面104c也通过空腔C暴露。空腔C可通过以下方式形成：涂覆光致抗蚀剂；通过曝光和显影工艺去除要形成空腔C的区域中的光致抗蚀剂，同时保留其它区域中的光致抗蚀剂；以及使用留下的光致抗蚀剂作为蚀刻掩模执行蚀刻工艺。所述蚀刻可以采用干式蚀刻和湿式蚀刻等。干式蚀刻可以使用诸如CF4、SF6、NF3、Cl2或者CCl2F2的蚀刻气体，而湿式蚀刻可以使用硝酸、乙酸和氟酸的混合溶液。然而，本发明并不限于此。
参考图2c，第一绝缘层108用于填充空腔C，并且涂覆晶片的后表面100b和端部104b。第一绝缘层108可以包括一种或更多种有机绝缘材料和无机绝缘材料。例如，有机绝缘材料可以包括聚酰亚胺、苯并环丁烯、光丙烯(photoacryl)、聚酯、聚芳基醚、全氟环丁烷、聚对二甲苯、包括光致抗蚀剂的光阻树脂、SiOCH、SiCHN或SiCH等。无机绝缘材料可以包括例如氧化硅、氮化硅、硅酸氮化物、碳化硅、金属氧化物、SiC，SiCN等。但是，本发明并不限于此，并且可以包括其它合适的材料。绝缘层的涂覆可采用例如薄膜形成方法来执行，所述薄膜形成方法例如为旋涂、浸涂、溶胶凝胶涂覆、喷涂、真空沉积、溅射或化学气相沉积(CVD)。
光致抗蚀剂可以包括对光敏感的感光剂、用作薄膜主体的树脂以及用于溶解树脂的有机溶剂等，并且正型光致抗蚀剂和负型光致抗蚀剂二者都可使用。在正型光致抗蚀剂的情况下，树脂可以采用例如甲阶酚醛树脂以及酚醛树脂等，而感光剂可以采用二氮醌、聚甲基丙烯酸甲酯(PMMA)或其衍生物等。在负型光致抗蚀剂的情况下，树脂可以采用例如聚乙烯肉桂酸、丙烯酸双环戊烯基酯(DCPA)以及烯丙基酯预聚物等。
SiOCH、SiCHN以及SiCH可以是通过等离子体CVD方法采用聚有机硅烷生长的有机绝缘材料。例如，可用的聚有机硅烷可以包括一种或更多种的聚有机硅烷，诸如三甲基乙烯基硅烷、三乙基乙烯基硅烷、二甲基二乙烯基硅烷、二乙基二乙烯基硅烷、甲基三乙烯基硅烷、乙基三乙烯基硅烷、四乙烯基硅烷、四乙基硅烷以及三乙基硅烷。
参考图2d，将第一绝缘层108图案化以暴露柱体部的上表面(允许柱体部的一侧端部104b突出)。柱体部的暴露的上区域包括端部104b，并且可进一步包括柱体部的侧表面104c。第一绝缘层108的图案化可以根据构成第一绝缘层108的绝缘材料的类型来选择。
例如，当绝缘材料是光致抗蚀剂时，可以采用这样的方法，其调整曝光条件以允许仅将一部分厚度的光致抗蚀剂层108曝光，并且执行显影工艺。也就是说，所述方法可以包括涂覆光致抗蚀剂层，将一部分厚度的光致抗蚀剂层曝光，以及显影曝光的光致抗蚀剂层。对于另一个示例，当绝缘材料是氧化硅SiO2时，光致抗蚀剂可涂覆在氧化硅上，并且可通过曝光和显影工艺而图案化以去除柱体部的上区域上的光致抗蚀剂，并且第一绝缘层可通过干式蚀刻工艺或湿式蚀刻工艺而去除以暴露柱体部的上区域，所述干式蚀刻工艺采用例如C2F6气体和CF4/H2气体，所述湿式蚀刻工艺采用例如缓冲HF(BHF)。然后，剩余的光致抗蚀剂可采用诸如O2等离子体灰化这样的公知技术而去除。
参考图2e，通过例如填充空腔C而形成后电极110。也就是说，后电极110形成为涂覆端部104b和侧表面104c。后电极110可以是单层或多层，其包括一种或更多种金属以及导电有机材料等。每层可包括金(Au)、银(Au)、铜(Cu)、铝(Al)、镍(Ni)、钨(W)、钛(Ti)、铂(Pt)、钯(Pd)、锡(Sn)、铅(Pb)、锌(Zn)、铟(In)、镉(Cd)、铬(Cr)和钼(Mo)中的至少一种。后电极110可采用例如非电解电镀、电解电镀、真空沉积以及溅射等形成。
作为示例，后电极110可通过以下方式具有如图2e所示的形状，沉积导电金属薄膜，在导电金属薄膜上涂覆光致抗蚀剂，通过曝光和显影等图案化光致抗蚀剂，以及通过采用图案化的光致抗蚀剂作为蚀刻掩模而蚀刻金属薄膜。
对于另一个示例，铜薄膜可通过非电解电镀形成。在非电解电镀中使用的电镀溶液可包括铜离子源、PH控制剂以及还原剂，并且可包括乙二胺四乙酸(EDTA)和表面活性剂等作为络合剂。铜离子源可包括例如CuSO4·5H2O和CuSO4等，PH控制剂可包括KOH和NaOH等，而还原剂可包括甲醛等。但是，本发明并不限于此。可使用其它适当的材料。当通过如下反应由还原剂(甲醛)将铜还原时，可执行非电解电镀。
Cu2++2HCHO+4OH-→Cu+2H2O+2HCO2 -
此外，可以采用诸如铂(Pd)或钯锡(Pd/Sn)化合物的催化剂。如果由氢氧化钠而使PH增加至例如约PH10或更大，则由于甲醛的强还原反应而产生电子。这些电子流向铜离子，并且使铜离子沉淀在钯催化剂上，从而可涂覆铜层。
对于另一个示例，后电极110也可通过电解电镀而形成。通常，相比于物理气相沉积(PVD)或化学气相沉积(CVD)，采用电解电镀形成薄膜的优点在于，薄膜形成速度快，并且可以在低温下进行。通过电解电镀，可以形成后电极110，其包括单层的铜和通过依次堆叠铜、镍和金获得的金属膜等。但是，本发明并不限于此，并且可使用其它方法来形成后电极110。
在电解电镀的示例中，电解电镀溶液可包括例如铜离子源、调节导电性的硫酸(H2SO4)以及调节还原反应的盐酸(HCl)等，并且还包括其它添加剂。也就是说，如果将CuSO4作为铜离子源放入硫酸(H2SO4)和水中，CuSO4将溶解为Cu2+离子和SO42-离子。如果柱体部104连接到阴极并且浸入电解槽中，柱体部104可用作晶种层，从而产生铜层。在采用电解电镀来形成镍层的方法中没有限制。例如，可以使用包含NiSO4·6H2O120至230g/L，NiCl25至35g/L以及H3PO45至35g/L的水溶液，或者包含NiSO4·6H2O120至230g/L，Na4Cl10至30g/L以及ZnSO4·7H2O20至50g/L的水溶液。当水溶液温度为大约25℃至50℃并且PH为大约4至7时，可形成镍层。但是，本发明并不限于此，并且可使用其它合适的方法来形成镍层。
为了提高电特性，可执行电解金电镀，并且为了有助于金的粘贴，可以首先在镍表面上执行活化工艺。金-铜成分可容易磨损。如果铜被直接电镀金，由于金成分进入铜并且铜成分进入金，因此采用金电镀的导电性不会提高。在这点上，优选在电解金电镀之前执行镍电镀。关于电解金电镀的电镀溶液，氯金酸盐或硫酸金可用作金源，而氰化物或无氰化物可用作螯合剂。然而，在本发明中对于电解金电镀的电镀溶液没有限制。
参考图3a至图3e描述根据本发明的另一个示例性实施例的制造半导体芯片的方法，并且任何重复的描述将被省略或者简单给出。
参考图3a，类似于图2a至图2c，柱体部104形成在衬底100中，空腔C形成在衬底的后表面100b上，并且第一绝缘层108形成为涂覆空腔C和后表面100b。第一绝缘层108的材料和形成方法可与关于图2a至图2e所述的实质上相同。
参考图3b，通过化学机械抛光(CMP)、研磨以及回蚀等，在第一绝缘层108上可执行平坦化工艺。在必要时，可不执行平坦化工艺。
例如，当第一绝缘层108是氧化硅SiO2或金属氧化物时，可通过化学机械抛光执行平坦化工艺。化学机械抛光以在向抛光垫提供浆料的同时允许晶片往复移动和旋转的这种方式执行，其中所述浆料包括处理溶液(例如，其与氧化硅或金属氧化物起化学反应，诸如KOH、NaOH或NH4OH)、用于分散抛光微粒的分散剂、抑制泡沫的防沫剂以及磨蚀剂中的另一缓冲剂(举例而言，诸如氧化铝(Al2O3)、二氧化锌(ZrO2)、氧化铯(CeO2)或二氧化硅(SiO2)。对于另一个示例，光致抗蚀剂或聚酰亚胺可涂覆在第一绝缘层108上，并且等离子体蚀刻工艺可采用O2或CF4/O2执行，直至第一绝缘层108暴露，并且等离子体蚀刻工艺可通过调整第一绝缘层108的蚀刻速率与光致抗蚀剂或聚酰亚胺的蚀刻速率实质上相同而继续执行，直至光致抗蚀剂或聚酰亚胺被蚀刻掉，从而可将第一绝缘层108平坦化。
同时，当第一绝缘层108是通过旋涂等形成的有机材料时，由于很可能第一绝缘层108的涂覆上表面已经被平坦化，因此平坦化工艺可以省略。当执行平坦化工艺时，第一绝缘层108可通过例如研磨工艺平坦化。
参考图3c，第二绝缘层112涂覆在第一绝缘层108上。
第二绝缘层112可以包括一种或更多种有机绝缘材料和无机绝缘材料，并且可包括与第一绝缘层108实质上相同或不同的材料。例如，有机绝缘材料可包括聚酰亚胺、苯并环丁烯(benxocyclobutene)、光丙烯、聚酯、聚对二甲苯、包括光致抗蚀剂的感光树脂、SiOCH、SiCHN以及SiCH等，而无机绝缘材料可包括氧化硅、氮化硅、硅酸氮化物、碳化硅、金属氧化物、SiC以及SiCN等。但是，本发明并不限于此，并且可采用其它合适的材料。绝缘层的涂覆可通过例如薄膜形成方法执行，所述薄膜形成方法例如为旋涂、浸涂、溶胶凝胶涂覆、喷涂、真空沉积、溅射或CVD。
参考图3d，整个厚度的第二绝缘层112和一部分厚度的第一绝缘层108被去除，以暴露柱体部104的端部104b。暴露的端部104b(第一绝缘层和第二绝缘层被去除的区域)可以大于柱体部的截面面积，并且小于空腔的截面面积。也就是说，从柱体部的中轴到柱体部的暴露上区域的外围的距离D大于从柱体部的中轴到柱体部的外围的距离D1，并且小于从柱体部的中轴到空腔的外围的距离D2。
第二绝缘层112和第一绝缘层108的去除可根据构成第二绝缘层112和第一绝缘层108的绝缘材料的类型来选择。例如，当绝缘材料是光致抗蚀剂时，可采用诸如曝光或显影的方法，或者采用激光烧蚀去除特定部分的方法。对于另一个示例，当绝缘材料是氧化硅SiO2时，光致抗蚀剂可涂覆在氧化硅上并通过曝光和显影工艺图案化，以去除柱体部的上区域上的光致抗蚀剂，并且第一绝缘层和第二绝缘层可通过干式蚀刻工艺或湿式蚀刻工艺去除，以暴露柱体部的上区域，所述干式蚀刻工艺采用C2F6气体，所述湿式蚀刻工艺采用缓冲HF(BHF)。然后，剩余的光致抗蚀剂可采用诸如O2等离子体灰化的公知技术去除。
参考图3e，后电极110形成在暴露的端部104b上。后电极110的材料和形成方法与以上描述实质上相同。
图4a至图4c是示出根据本发明的另一个实施例的制造半导体芯片的示例性方法的剖面图。
参考图4a，类似于图2a至图2c，柱体部104形成在衬底100中，空腔C形成在衬底的后表面100b侧上，而第一绝缘层108涂覆以填充空腔C并同时涂覆衬底的背表面100b。
参考图4b，第一绝缘层可图案化，以保留空腔C中的第一绝缘层108，而位于其它区域中的第一绝缘层被去除。第一绝缘层108的图案化可根据构成第一绝缘层108的绝缘材料的类型来选择。
例如，当绝缘材料是光致抗蚀剂时，曝光条件可调整为使得衬底的后表面100b也被曝光，并且显影工艺执行为使得位于空腔外围的所有光致抗蚀剂被去除且位于空腔C中的光致抗蚀剂的整个或一部分厚度保留。此外，可采用通过激光烧蚀去除晶片的后表面100b和柱体部的一侧端部104b上的光致抗蚀剂的方法。对于另一个示例，当绝缘材料是氧化硅、氮化硅或金属氧化物时，第一绝缘层108可通过在不采用蚀刻掩模的情况下执行干式蚀刻或湿式蚀刻(回蚀)直至暴露衬底的端部104b和后表面100b而图案化。对于另一个示例，也可执行化学机械抛光，直至暴露晶片的端部104b和后表面100b。
参考图4c，如上所述，形成第二绝缘层112和电极110，从而形成硅通路。另外，附加绝缘层可进一步形成在第二绝缘层112上。
参考图5a至图5c描述根据本发明的另一个示例性实施例的制造半导体芯片的方法，并且重复的描述将被省略或仅简单给出。
参考图5a，类似于图2a至图2c，具有预定深度和宽度的空腔C形成在端部104b的周围，以暴露端部104b和侧表面104c。
参考图5b，第一绝缘层108可形成为填充整个或部分厚度的空腔C，其中第一绝缘层108可形成在空腔C中，而不需要单独的图案化工艺。第一绝缘层108可包括一种或更多种有机绝缘材料和无机绝缘材料，并且可通过分配(dispensing)和丝网印刷等形成。
例如，第一绝缘层108可通过以下方式形成，其中通过分配和丝网印刷等在空腔C中涂覆有机绝缘材料(例如，包括热固树脂或光固树脂)并且固化(热固化或光固化)有机绝缘材料。例如，热固树脂可包括酚树脂和环氧树脂等。然而，本发明不限于此，并且可采用其它合适的材料。对于另一个示例，第一绝缘层108可通过以下方式形成，其中通过丝网印刷在空腔C中涂覆包括氧化硅和金属氧化物等的无机绝缘材料，并且执行干燥和烧结。
参考图5c，第二绝缘层112和后电极110可通过与如上所述相同的方式形成。
参考图6a至图6d描述根据本发明的另一个示例性实施例的制造半导体芯片的方法，并且重复的描述被省略或简单给出。
参考图6a，具有三个柱体1041至1043的柱体部104形成在设置有前表面100a和后表面100b的衬底100中，粘贴承载衬底(没有示出)，执行背向研磨，形成空腔C。
参考图6b，第一绝缘层108形成为涂覆空腔C和后电极100b。第一绝缘层108的材料和形成方法与如上所述实质上相同。
参考图6c，第一绝缘层108被图案化以暴露柱体部104的三个柱体1041至1043中每个的上区域。柱体部104的暴露上区域可包括柱体部的端部和柱体部的端部的侧表面。第一绝缘层108的图案化可根据构成第一绝缘层108的绝缘材料的类型来选择，并且其详细描述将省略。采用可固化有机材料，例如，诸如上述热固树脂或光固树脂，也可以省略图案化工艺。
参考图6d，后电极110形成在第一绝缘层108上。后电极110的材料和形成方法与如上所述实质上相同。另外，尽管柱体部104被描述为包括三个柱体1041至1043，但本发明并不需要限于此。例如，柱体部104可以包括两个柱体，或者柱体部104可以包括超过三个柱体。
图7是示出根据本发明的一个示例性实施例的半导体芯片堆叠封装体的剖面图，并且为了方便起见简要示出了半导体芯片堆叠封装体。
参考图7，多个半导体芯片310、312、314和316依次堆叠在封装衬底300上。但是，半导体芯片的数量可以小于四个或大于四个。
封装衬底300将封装体中的半导体芯片310、312、314和316电连接至外部印刷电路板(PCB)，并且支撑半导体芯片310、312、314和316。例如，封装衬底300可以是诸如塑料衬底和陶瓷衬底等任何合适的衬底。在一个实例中，封装衬底300可以是包括环氧芯和电互连等的塑料衬底。对于另一个示例，封装衬底300可以是通过晶片级封装工艺安装有半导体芯片310、312、314和316的印刷电路板，并且可以是柔性印刷电路板、刚性印刷电路板、或其组合。
封装衬底300可以设置有内部连接320和连接端子322。连接端子322可形成在封装衬底300的一个表面上，而焊球324可形成在封装衬底300的另一表面上。连接端子322可通过封装衬底300的内部连接320电连接到焊球324。对于另一个示例，焊球324可用诸如焊料凸块的导电凸块替代。
采用上述硅通路形成方法形成的硅通路310a、312a、314a和316a位于半导体芯片310、312、314和316中，并且可通过例如焊料膏、焊料凸块和导电粘附层(没有示出)等而彼此电连接。此外，半导体芯片可以是相同类型的芯片，例如存储器芯片，诸如闪存、MRAM(磁阻随机存取存储器)、ReRAM(电阻随机存取存储器)、FRAM(铁电随机存取存储器)或DRAM(动态随机存取存储器)，其包括晶体管、电容器以及将这些元件彼此连接的互连。半导体芯片还可包括不同类型的存储器芯片，例如闪存和DRAM。此外，半导体芯片可包括例如存储器芯片和逻辑芯片。
半导体芯片316可以设置有控制芯片(没有示出)，并且可以模制有诸如环氧模塑料(moldingcompound)的模制部件330。控制芯片可包括逻辑电路，例如SER/DES电路。
根据本发明实施例的半导体芯片及制造方法，即使在硅通路的直径减少时也能够有效地防止漏电流，而无关于包括昂贵的光刻设备的设备进步，并且由于半导体部件重量轻、结构纤薄以及尺寸紧凑，因此可以实质上防止制造成本的增加。
出于示例性目的，以上公开了本发明的实施例。本领域技术人员将理解可以进行不同的改变、增加和替换而不脱离随附权利要求书限定的本发明的范围和精神。
本申请要求在2011年2月11日提交至韩国知识产权局的韩国申请No.10-2011-0012488的优先权，其全文被援引结合。

Claims (20)

1.一种半导体芯片，包括：
衬底，具有前表面和与所述前表面相对的后表面；
导电柱体部，从所述前表面到所述后表面穿过所述衬底；
空腔，通过去除所述导电柱体部的端部周围的部分所述后表面形成在所述衬底中，使得所述导电柱体部的所述端部从所述空腔突出；
第一绝缘层，形成在所述空腔中，使得所述导电柱体部的所述端部的一部分暴露；以及
后电极，电连接至所述导电柱体部的暴露端部。
2.根据权利要求1所述的半导体芯片，其中所述第一绝缘层涂覆所述空腔和所述衬底的所述后表面。
3.根据权利要求1所述的半导体芯片，其中所述第一绝缘层包括有机绝缘材料，所述有机绝缘材料包括光致抗蚀剂。
4.根据权利要求1所述的半导体芯片，其中所述后电极覆盖所述第一绝缘层的上表面的一部分。
5.根据权利要求1所述的半导体芯片，其中所述导电柱体部包括彼此间隔开的多个柱体。
6.根据权利要求1所述的半导体芯片，还包括：第二绝缘层，形成在所述第一绝缘层上，所述第二绝缘层的上表面的一部分涂覆有所述后电极。
7.根据权利要求6所述的半导体芯片，其中所述第一绝缘层和所述第二绝缘层由实质上相同类型的材料形成。
8.一种制造半导体芯片的方法，所述方法包括：
在衬底中形成导电柱体部，所述衬底具有前表面和与所述前表面相对的后表面，并且所述导电柱体部从所述前表面到所述后表面穿过所述衬底；
通过去除所述导电柱体部的端部周围的部分所述衬底而在所述衬底中形成空腔；
形成第一绝缘层，所述第一绝缘层填充所述空腔的至少一部分；以及
形成后电极，所述后电极电连接至所述导电柱体部的所述端部。
9.根据权利要求8所述的制造半导体芯片的方法，其中所述第一绝缘层涂覆所述衬底的所述后表面和所述空腔的至少一部分。
10.根据权利要求8所述的制造半导体芯片的方法，其中形成所述第一绝缘层包括：
涂覆光致抗蚀剂层；
将部分厚度的所述光致抗蚀剂层曝光；以及
显影曝光的光致抗蚀剂层。
11.根据权利要求8所述的制造半导体芯片的方法，其中所述第一绝缘层的上表面与所述衬底的后表面齐平。
12.根据权利要求8所述的制造半导体芯片的方法，其中形成所述第一绝缘层包括：
涂覆所述后表面的一部分；以及
去除所述空腔中的所述第一绝缘层之外的所述第一绝缘层。
13.根据权利要求12所述的制造半导体芯片的方法，包括：
形成第二绝缘层，所述第二绝缘层涂覆所述衬底的所述后表面和所述第一绝缘层的上表面的一部分。
14.根据权利要求8所述的制造半导体芯片的方法，其中形成所述第一绝缘层包括：
在空腔中涂覆有机绝缘材料；以及
固化所述有机绝缘材料。
15.根据权利要求14所述的制造半导体芯片的方法，其中所述有机绝缘材料包括一种或更多种热固树脂和光固树脂。
16.根据权利要求14所述的制造半导体芯片的方法，包括：
形成第二绝缘层，所述第二绝缘层涂覆所述衬底的所述后表面和所述第一绝缘层的上表面的一部分。
17.根据权利要求8所述的制造半导体芯片的方法，其中形成所述第一绝缘层包括：
涂覆第一绝缘层；
在所述第一绝缘层上涂覆第二绝缘层：以及
去除所述第一绝缘层和所述第二绝缘层的至少一部分，以暴露所述导电柱体部的所述端部的至少一部分。
18.根据权利要求17所述的制造半导体芯片的方法，其中所述第一绝缘层和所述第二绝缘层由实质上相同类型的材料形成。
19.根据权利要求17所述的制造半导体芯片的方法，其中在暴露所述导电柱体部的端部的至少一部分时，所述第一绝缘层和所述第二绝缘层被去除的面积大于所述导电柱的截面面积并且小于所述空腔的截面面积。
20.根据权利要求8所述的制造半导体芯片的方法，其中所述导电柱体部包括彼此间隔开的多个柱体。
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