FR2970118B1 - Puce de circuits integres et procede de fabrication. - Google Patents

Puce de circuits integres et procede de fabrication.

Info

Publication number
FR2970118B1
FR2970118B1 FR1061355A FR1061355A FR2970118B1 FR 2970118 B1 FR2970118 B1 FR 2970118B1 FR 1061355 A FR1061355 A FR 1061355A FR 1061355 A FR1061355 A FR 1061355A FR 2970118 B1 FR2970118 B1 FR 2970118B1
Authority
FR
France
Prior art keywords
electrical connection
integrated circuit
circuit chip
substrate die
manufacture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR1061355A
Other languages
English (en)
Other versions
FR2970118A1 (fr
Inventor
Laurent-Luc Chapelon
Julien Cuzzocrea
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Crolles 2 SAS
Original Assignee
STMicroelectronics Crolles 2 SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Crolles 2 SAS filed Critical STMicroelectronics Crolles 2 SAS
Priority to FR1061355A priority Critical patent/FR2970118B1/fr
Priority to US13/304,823 priority patent/US9093505B2/en
Publication of FR2970118A1 publication Critical patent/FR2970118A1/fr
Application granted granted Critical
Publication of FR2970118B1 publication Critical patent/FR2970118B1/fr
Priority to US14/743,072 priority patent/US9455239B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
FR1061355A 2010-12-30 2010-12-30 Puce de circuits integres et procede de fabrication. Expired - Fee Related FR2970118B1 (fr)

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US13/304,823 US9093505B2 (en) 2010-12-30 2011-11-28 Integrated circuit chip and fabrication method
US14/743,072 US9455239B2 (en) 2010-12-30 2015-06-18 Integrated circuit chip and fabrication method

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US20180331061A1 (en) * 2017-05-11 2018-11-15 Qualcomm Incorporated Integrated device comprising bump on exposed redistribution interconnect
EP3460835B1 (fr) * 2017-09-20 2020-04-01 ams AG Procédé de fabrication d'un dispositif à semi-conducteur et dispositif à semi-conducteur

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US6451177B1 (en) * 2000-01-21 2002-09-17 Applied Materials, Inc. Vault shaped target and magnetron operable in two sputtering modes
EP1482553A3 (fr) * 2003-05-26 2007-03-28 Sanyo Electric Co., Ltd. Dispositif semi-conducteur et méthode de fabrication associée
JP4282514B2 (ja) * 2004-03-12 2009-06-24 三洋電機株式会社 半導体装置の製造方法
JP4873517B2 (ja) * 2004-10-28 2012-02-08 オンセミコンダクター・トレーディング・リミテッド 半導体装置及びその製造方法
US7723224B2 (en) * 2006-06-14 2010-05-25 Freescale Semiconductor, Inc. Microelectronic assembly with back side metallization and method for forming the same
US8492263B2 (en) * 2007-11-16 2013-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Protected solder ball joints in wafer level chip-scale packaging
US7855455B2 (en) * 2008-09-26 2010-12-21 International Business Machines Corporation Lock and key through-via method for wafer level 3 D integration and structures produced
US7839163B2 (en) 2009-01-22 2010-11-23 International Business Machines Corporation Programmable through silicon via
CN105140136B (zh) * 2009-03-30 2018-02-13 高通股份有限公司 使用顶部后钝化技术和底部结构技术的集成电路芯片
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US8492891B2 (en) * 2010-04-22 2013-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with electrolytic metal sidewall protection
US8685778B2 (en) 2010-06-25 2014-04-01 International Business Machines Corporation Planar cavity MEMS and related structures, methods of manufacture and design structures

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US9093505B2 (en) 2015-07-28
US9455239B2 (en) 2016-09-27
US20120146226A1 (en) 2012-06-14
FR2970118A1 (fr) 2012-07-06
US20150287689A1 (en) 2015-10-08

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