TWI276187B - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
- Publication number
- TWI276187B TWI276187B TW094135823A TW94135823A TWI276187B TW I276187 B TWI276187 B TW I276187B TW 094135823 A TW094135823 A TW 094135823A TW 94135823 A TW94135823 A TW 94135823A TW I276187 B TWI276187 B TW I276187B
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- Prior art keywords
- layer
- pad electrode
- electrode layer
- forming
- semiconductor
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 126
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 58
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- 238000000034 method Methods 0.000 claims description 30
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- 229910000679 solder Inorganic materials 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 3
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- 238000005520 cutting process Methods 0.000 claims description 2
- 229910052732 germanium Inorganic materials 0.000 claims description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims 1
- 229910052790 beryllium Inorganic materials 0.000 claims 1
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- 229910052802 copper Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
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- 229910001080 W alloy Inorganic materials 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
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- 229910001925 ruthenium oxide Inorganic materials 0.000 description 1
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 1
- KZUNJOHGWZRPMI-UHFFFAOYSA-N samarium atom Chemical compound [Sm] KZUNJOHGWZRPMI-UHFFFAOYSA-N 0.000 description 1
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- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
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- 238000001039 wet etching Methods 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Classifications
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
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- General Physics & Mathematics (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
•1276187 - 九、發明說明: 【發明所屬之技術領域】 本發明係關於一種半導體裝置及其製造方法,尤其是 關於一種具有貫穿電極的半導體裝置及其製造方法。/、 【先前技術】 近年來,做為三次元安裝技術及新的封裝技術,cSp (Chip Size Package,晶片尺寸封裝)受到相當的矚目。 所謂CSP係指外型尺寸與半導體晶片的外型尺寸大致相同 β大小的小型封裝體。 •• 以往,具有貫穿電極的BGA ( Ball Gdd Amy,球閘 •::㉟半導體裝置已知為csp的一種。& BGA型半導 版衣置具有貫穿半導體基板並與銲墊電極連接的貫穿電 2 "亥半‘體裝置係將由銲錫等金屬構件所組成的球狀導 電端子以格子狀排列複數個在其背面上。 ^接著將该半導體裝置組裝在電子機器時,係將各導 _包端子連接在電路基板(例如印刷基板)上的配線圖案。 ,有突出側部之導腳(lead pin)的sop (Small 0utline ackage )或 QFp ( Quad Flat package )等其他 型半導 體裝置相較之下,這種BGA型半導體裝置不但可以裝設 車乂多的導電端子,且具有可小型化的優點。 接著概略說明習知例中具有貫穿電極的BGA型半導 體^置㈣造方法。首先,在半導體基板的表面,隔著第 /絕緣膜形成銲墊電極。接著,#由_該半導體基板, 形成從半導體基板背面到銲墊電極的介層孔(“a h〇ie)。 317484 5 1276187 並且’在含介層孔内的半導體基板的背面上,形成在該介 層孔底部露出銲墊電極的第2絕緣膜。 再者,在介層孔内的第2絕緣膜上,形成與在該底部 露出的銲墊電極電性連接的貫穿電極。此外,同時在半導 體基板背面的第2絕緣膜上形成與上述貫穿電極連接的配 線層。接著,在包含上述配線層上的半導體基板背面上形 成保護層,使上述保護層的一部分形成開口而露出上述配 線層的-部分。再者,亦可在此配線層上形成導電端子。 之後再將半導體基板藉由切割(dicing)切斷分離成複 數個半導體晶片。 其相關之技術文獻例如以下之專利文獻。 專利文獻1 :日本專利特開2003-309221號公報 【發明内容】 [發明所欲解決之課題] :著,參照圖面說明上述之習知例之半導體裝置的製 部分步驟。第19圖為顯示習知例之半導體 裂造方法之剖面圖。 如:19圖所示’於所謂前步驟中,在形成有未圖示之 =的半導體基板50表面,隔著P絕緣膜5卜形 成有乐1銲墊電極層52。接 备 ... 莰耆在弟1銲墊電極層52上, Μ及電極層55:在第2鮮墊電極層55的-部 55之門^膜51上’形成有具有露出》2銲墊電極層 之開口邛53W的第2絕緣膜53。 在此’於未圖示之雷+ 件#的琶路測試中,透過半 317484 6 1276187 、導體裝置表面的開口部53W,使探針7〇接觸到上 銲墊電極層55上。然而,當使探針7〇盥第2 55接觸時,第2銲墊電極層55會發生㈣等=_層 損傷會影響到第1銲墊電極層。例如 …、而5亥 列如,產生從第2銲墊雷 極層55到第1銲墊電極層52的磨削等損傷。 电 因此’在其後的步驟中’藉由例如乾核刻、渴式餘 刻或電漿钱刻來形成從半導體基板5〇背面到鲜塾 ^^的…絕緣㈣的介層孔時’由於難刻集中在 •生在弟1銲墊電極層52的上述損傷,導致第^鲜塾 :層52或第2銲墊電極層55發生破損的情形。 • &外’在包含由於上述損傷而產生破損之第1銲塾電 極層52上的介層孔内,在形成由例如銅(⑻而成之未 圖不的貫穿電極之後,在該貫穿電極與第i銲墊電極層% ^狀會產生連接不良之情形。亦即,具有貫穿電極的半 ¥體衣置會發生可靠性降低的問題。其結果使得且有貫 電極的半導體裝置的可靠性及良率降低。 、 、生因此’本發明係於具有貫穿電極之半導體裝置及其製 ^方法中,謀求達成提升該半導體裝置之可 [用以解決課題的手段] 良羊 本發明之半導體裝置及其製造方法,係鑑於以上課題 而研創者’具有以下特徵。亦即,本發明之半導體裝置具 有:半導體晶片;在半導體晶片表面上隔著第1絕緣膜^ 形成的第1銲墊電極層;形成在第1銲塾電極層上的第2 絕緣膜;形成在於第2絕緣膜形成開口的第!介層孔内的 317484 7 1276187 ==;形成在第1絕緣膜上,透過金屬插塞盘第!鋒 ㈣極層電性連接的第2銲墊電極層;從半導體 到弟1杯墊電極層的第2介層孔;以及形成於 : 穿電極。 "層孔與弟以墊電極層電性連接的貫 此外,除上述構成之外,本發明之半 形成於第2銲塾電極層的一部分上 :置,、有· 有露出該第2銲墊帝赶屏之門都 、巴、、膜上,並具 ❸…! _的第1保護層;與貫穿 及在包含配線層的半導體配線層;以 一部分上的第2保護層m = 2出該配線層的 牛=體衣置亦可在配線層的—部分上配置導電端子。 本發明之半導體裝置之製造 面上,P荽笙!奶緣3 去為·在半導體基板表 隔者弟“巴緣膜形成第!銲墊電極層 1銲墊電極層上形成第2絕緣膜的步 ,弟 形成露出第!銲墊電極層的 驟,在弟1絕緣膜, 展w 的弟1介層孔的步驟;在第1介 "”成金屬插塞的步驟;在第2絕緣膜上,形成诱 過金屬插塞與第!銲墊電極層電 =上开/成透 ,/ ^ 1接的弟2銲墊電極® 的乂驟;形成從半導體基板的背面 a 317484 8 1 ^ m λα ^ ^ 】乐11干墊電極層的第 曰孔的^驟,·形成透過第2介層孔與第】 電性連接的貫穿電極的步驟;以及 * ^ 成複數個的半導體晶片的步驟。、U切斷分離 此外,本發明之半導縣置之以方法 驟之外’復具有:在包含第2銲墊 二、〜 星逼極層上的弟2絕緣膜 1276187 上,形成具有使第2銲墊電極層露之 ^ 層的步驟;形成與貫穿電極 汗口P的第1保護 =面上的配線層的步驟;以及在 的一部分上露㈣方式形成第= 層的步驟。再者,本發明之製造方法, 隻 亦可具有:在配線層的—部八b驟之外, μμ„ ,. 的邛刀上形成導電端子的步驟。 、 卜,本务明之半導體裝置之製造方法具 連接有複數個銲墊電極層" 装此北 層的牛v體基板,形成從該半導體 I 數個銲墊電極層中離該半導體基板表面較近 巧墊_層之介層孔的步驟;形成透過介層孔 離半導體基板表面較近的銲墊電極層带 ^ 二 的步驟;以及將半導體基 =接2貝牙電極 的步驟。 极刀畊刀雔成稷數個半導體晶片 此外,本發明之半導體褒 驟之外,其特徵為且有.法’除了上述步 *“ 、有·在+導體基板表賴,形成使複 電極層中距離該半導體基板表面較遠的銲墊電極 層路出的開口部的步驟。 [發明的效果] 〜根據本發明,第1銲墊電極層與第2銲塾電極層,係 =形成在夹持於該等銲塾電極層中的第2絕緣膜 =孔内的金屬插塞而相連接。因此,電路測試時等的探 ^弟2鮮塾電極層相接觸時,若對該第2鲜塾電極層造 ^磨削等損傷時,第2絕緣膜或金屬插塞可發揮 緩衝層的功能’使該損傷難以影響到: 317484 9 1276187 在第1鋅墊電極層產生上述損傷而使該第 紅墊電極層發生破損的情形。 w 2於存在第2絕緣膜,可對第1及第2銲墊電極#的 殘留應力進行所媢的處士知土丨 卞丄电往層的 介層孔時^ 制°亦即,在半導體基板形成 ^、 ㈣此為止蓄積在第1及第2銲墊電極層的 歹欠留應力朝介斧不丨允pq ^ θ i間的方向開放時,藉由第2絕緣膜的 f = k升弟1及第2銲墊電極層的黏接性,藉此可極力 變形。 墊電桎層在w層孔的空間被推出而彎曲 [鲜墊電極層的破損或變 弟1鲜墊電極層相連接之 而提升貫穿電極與第2銲 此外,由於可極力抑制第 形,因而抑制在介層孔底部與該 貫穿電極發生連接不良的情形, 墊電極層連接的可靠性。 ,此方式’第1銲墊電極層用來與貫穿電極相連接 而且第2銲墊電極層用來與探針相連接,各個銲塾電極/ 可以分別使用而不會降低其功能。因此,可以提高具有, 牙電極之半導體裝置的可靠性及良率。 【實施方式】 接著,參照圖面說明本發明之實施形態之半導體裝置 的製造方法。第1圖至第16圖為表示本實施形態之半導體 裝置的製造方法之剖面圖。此外’第1圖至第圖係顯示 半導體基板中未圖示之切割線的附近。 首先士第1圖所示,備妥在表面形成有未圖示之電 子元件的半導體餘1Q。在此,纟圖示之電子元件係為例 317484 10 1276187 广(Charge Coupled Device,電荷耦合元件)或紅外 次感測器等受光元件或是發光元件。或者,未圖示之電子 凡件也可以是上述受光元件或發光元件以外的電子元件。 此外’半導體基板10雖為例如由石夕基板構成者,但亦可為 其他材質的基板。此外,半導體基板1G最好具有約】 m的膜厚。 μ 接者’在包含未圖示之電子元件的半導體基板ι〇表面 ,形成做為層間絕緣膜的第丨絕緣膜u。第丨絕緣膜η :乂如P_TE〇S膜或BPSG膜等構成。此外,第i絕緣 艇11表好以CVD法形成具有約0 8#m的膜厚。 、接著=在半導體基板10表面的第1絕緣膜丨丨上,形 成與未圖示之電子元件相連接的外部連接用電 12。第1銲墊電極層12係由例如鋁(A1)而成, 取^成具有約l//m至2#m的膜厚。 ,著,如第2圖所示,在半導體基板1〇的表面上, ‘墊電極層Μ及第1絕緣膜U上,形成覆蓋該 :電極層12的第2絕緣膜13。第2絕緣膜13係由 歹1如氧化石夕膜(Si〇2膜)或氮化石夕膜(SiN膜)而成,並 二/如私水 CVD ( chemical vapor deposition,化學氣相沈 矛貝法來形成。此外,第2絕緣膜13最好形成具有約U 至的膜厚。 e接著,如第3圖所示,在第2絕緣膜13上的預定區 遙擇性形成第1阻劑層41。形成第1阻劑層41的上述第 絕緣膜π u k z
、 上的預定區域係指除了局部形成在後述之第J η 317484 ^276187 、 銲墊電極層12的届邱μ Μ 域。 。的弟1介層孔的形成區域以外的區 接著’以第1阻劑層41 式蝕列^ 乍為‘罩(mask),最好以乾 '蝕亥k擇性蝕刻第2絕緣膜13 2 部分局部性形成開口,而 μ 、、、巴、、彖版13的- ! ^ 1Π1 成&出昂1銲墊電極層12的第 上層孔101〇在第1介層 層12。 曰孔101的底部露出第1銲墊電極 在此,第1介層孔1〇1且 一 •於第!銲墊電極層52的兩端=2的間隔’且最好形成 介声孔101 口亚… 或其附近上。或者,第1 :η ”要疋在· 1銲墊電極層12的一部分上,亦可 形成於上述以外的位置。此外, .θ ^ ,α π c 卜弟1 "層孔ιοί最好形成 八有、.、".一的直徑。上述飿刻 阻劑層41。 | J玄陈乐丄 接著,如第4圖所示,在上述第i介層孔ι〇ι内,形 ,由金屬構成的插塞14。在此,插塞14係形成為:埋入 #弟1介層孔至與第2絕緣膜13同一平面上為止。插塞Μ 最好是由鶴(W)或鎢合金構成的金屬插塞。或者,插塞Μ 亦可由上述以外的金屬所構成。例如,插塞Η亦可為如高 温I呂(Α1)般的插塞。 此外’插塞14的形成方法並無特別限^,例如可為以 下所示的鑲後法(damascene)。亦即,雖未圖*,卞在包含 第1介層孔HH内的第2絕緣膜13的全面上,形成例如由 鶴(W)構成的金屬層後’該金屬層藉由所謂⑽法 (Chemical Mechanical Polishing ’化學機械研磨法)研磨 317484 12 1276187 至第2絕緣膜1 1主 、 表面蕗出為止。藉此方式,形成1有卜、+、 構成的插塞14。成土 , 乂取具有上述 形成。 或者’插塞14亦可由上述以外的方法來 ”接著如第5圖所示,在含有插塞14上的第2奶缕r· 13的全面上形成 日〕弟2、纟巴緣膜 層Η係透過第八居^電極層15°在此’第2銲墊電極 層12作電性及德 1〇1的插塞14,與第1銲塾電極 祛械性連接。此外,第2銲墊電極声15 # 由例如鋁(Α1)所描 曰 电位層15係 的膜厚。 “冓成,攻好形成具有約〇.3㈣至2㈣ 區域,選擇㈣成!:,在弟2銲墊電極層15上的預定 笛2#埶發 昂 劑層42。形成第2阻劑層42的 、干電極層15上的預定區域係指包含所有第、 101之開口部的區妁.^ 匕3所有罘1介層孔 丨的k域。在本實施形態中,1 一 第1銲墊電極声12的Wr /、例為.在與 阻劑層42。 的形成區域相重疊的區域,形成有第2 接著’以第2阻劑層42為逨輩 擇性蝕刻第2銲墊 為巧取好猎由乾式蝕刻選 列完成# g 分的方式予以圖案化。上述蝕 刻兀成二爰,即將第2阻劑層42去除。 k蝕 接=,如第7圖所示,以覆蓋第2銲墊 式,在第2銲墊電極層15上 θ的方 保鳟声1 6 - 弟2、、、巴緣艇13上形成第1 保虔層16。弟J保護層 /成弟1 m , η , /t 忭马所明的鈍化膜而發揮作 用取好疋由例如氧化石夕膜( 毛禪作
膜)所構成。 2联j或虱化矽膜(SiN 317484 13 J276187 得L著=第8圖所示’在第1保護層16上的預定區域, 。擇性形成弟3阻劑層43。形成第3阻劑層4 護層16上的敎區域係指未形成後述之開^部歸的區 :,=P:第:刪極層15的一部分上及第2銲塾電: 層 5的形成區域以外的區域。 將第3阻劑層43為遮罩’最好以乾細技術 將弟1保濩層加以蝕刻後’形成露出帛2銲墊電極層15 的開口部16W。完成上述钱刻後,再將第3阻劑層二去 除。透過該開口部16W,第2銲墊電極層Μ係作為進行 半導體裝置的電路測試時與未圖^的探針相接觸的電 加以使用。 如上所述,第i銲墊電極層12與第2銲墊電極層Η 係藉由形成於該兩者所包夾之第2絕緣膜13的第1介^孔 101内的插塞Η相連接。如上所述,由於使第i鲜塾;極 層12與第2銲塾電極層15分離,因此當電路測試時等的 探針(probe pin)接觸到第2銲墊電極層15時,即使在該 第2銲墊電極層15造成磨削等損傷時,第2絕緣膜13戋 插塞14亦會發揮保護層紐衝層之功能,該損^難以影響 到第1銲墊電極層12。亦即,可極力抑制在第丨銲墊電極 層12產生上述損傷。 在本實施形態中,對於習知構造中積層有兩㈣塾電 極層者,雖然作為透過絕緣膜而使各別的銲墊電極層分離 者而加以說明,惟習知構造的銲墊電極層將1個分開為2 個鲜塾電極層’且同樣地分離配置該等銲墊電極層的技術 317484 14 1276187 亦包含在本發明中。 =如第9圖所示,在半導體基板1〇的背面 擇性形成第4阻劑層44。亦即 、 在半導體美妬川的此品L ^禮料係形成為: 12= 令’在對應於第1鋒墊電極層 12的位置具有開口部。 膺 接著,以該第4阻劑層44為遮罩, 將半導體基板10加以蝕刻 &式飿刻法 有匕或〇2或等的氣體。此外,使用卯 1作為蝕刻氣體時,其蝕刻條 2 約t & ^、仵取好為·例如其功率(p〇Wer) 、、勺為m氣體流量為w地⑽,屢力為挪。 如此一來,藉由上述蝕 成從半導體基板1〇的背面貫穿^^塾電極層12上形 ⑽。在第2人思„, 貝牙到該表面的第2介層孔 2介,孔102的底部,露出第“邑緣膜n。 電路、二二二上述蝕刻時,第1銲墊電極層12並不會因 電路測试時等與探針相接 u 中可知,由於乾』Γ 傷。因此,在習知例 ^ 式蝕刻或濕式蝕刻所使用的蝕刻廣# 刻溶液侵入第i銲執帝扰R t π π蝕刻轧體或蝕 1々曰批 塾包極層12的損傷部位,可極力抽制筮 1銲墊電極層12發生破損的情形。 了極力抑制弟 與未介層孔1G2形成前的上述電路载時等, Θ不采、十相接觸時,即使第2銲墊電&岸彳<;η 該變形會因第2锅绪m、 干塾电極層15變形, 響到第1銲墊電極層12或5插基σ 14而獲得緩和,難以影 層12在介層孔的’可極力抑制第1銲塾電極 ^ 曰7卫間被押出而彎曲變形。 接著’如第10圖所 口所不,以弟4阻劑層44為遮罩,最 317484 15 J276187 、乾式姓刻將在第2介層孔ι〇2底部露出的第丄絕 底卹+邛7刀砥擇性去除。藉此方式,在第2介層孔102的 再露出第1鮮塾電極層12的一部分。上述蝕刻完成後, 再將弟4阻劑層44去除。 ^ — 士第11圖所示,在含有第2介層孔1〇2内的半 1Rr基板1〇的背面上,形成第3絕緣膜18。第3絕緣膜 糸由,如氧化矽膜(Si〇2膜)或氮化矽膜(sm膜)所 應曰藉由例如電漿CVD法來形成。此外,第3絕緣膜 -取好,成具有約l/im至2/zm的膜厚。 :π接者,如第12圖所示,從半導體基板10的背面侧, 好=異向性乾式_對》3絕緣膜18進行射i。在此, I、j孔102底部的第3絕緣膜i 8,係與該第2介層孔 1〇2的冰度相對應,而形成比半導體基板lGf·面上的第3 絕1緖18還/等。因此,藉由上述钱刻,在第2介層孔102 底4係將第3絕緣膜18去除,而露出部分的第工鮮塾電 ,層丨二,但在半導體基板1〇的背面上及第2介層孔102 的側壁殘留有第3絕緣膜〗8。 接著’如第13圖所*,在第2介層孔1〇2内及半導體 背面的第3絕緣膜18上’形成阻障金屬層19。阻 障主“ 19係由例如鈦化鎮(Tiw)層、氮化欽(则 層或亂化鈕(TaN)層等金屬層所構成。 阻障金屬層!9係藉由例如_法、㈣法、血電解 電鑛=或其他成膜方法來形成。在該轉金屬層]9上,形 "^未.的種Μ °_晶層係成為用以電鐘形成後述 317484 16 .1276187 、-,形成層2GA的電極,由例如銅(Cu)等金屬所構成。 J,弟2介層孔102侧壁的第3絕緣膜18藉由氮化 夕版(SW膜)形成時’該氮切膜膜)成為對於 銅擴散的阻障,故阻障金屬層19亦可省略。 ’’、、、、 接著’以覆蓋形成於半導體基板1G背面上的阻障金屬 “9及種晶層的方式形成配線形成層2〇a。在此,上述配 線形成層2GA係藉由例如電解電鑛法,由例如銅( 所構成的金屬層。 、
/後,如第14圖所示’在上述配線形成層說上的 預疋區域’形成第5阻劑層45。然後以上述第5阻劑層45 為遮罩,將上述配線形成層2GA圖案化,形成貫穿電極 20 ’以及與貫穿電極2()連續電性連接的配線層η。電鐘 膜厚係调整為使貫穿電極2〇不完全嵌埋於第2介層孔搬 =的厚度。或者’貫穿電極2〇亦可形成為完全後埋於第2 介層孔102内。此外,形成上述第5阻劑層45之上述預定 區域係指除了第2介層孔1〇2$成區域以外的區域,並且 為未形成具有後述之預定圖案的配線層21的半導體基板 W背面上的區域。 在此,貫穿電極20係藉著種晶層與阻障金屬層19, 形成為與在第2介層孔1〇2底部露出的第}銲墊電極層12 電性連接。此外’與貫穿電極2〇連續的配線層21係藉由 種晶層與阻障金屬層19,在半導體基板1〇背面上形成具 有預定圖案。接著,在前述第5阻劑層45去除後,以前述 配線層21及種晶層為遮罩,將前述阻障金屬層工9予以圖 317484 17 ,1276187 案化去除。 八 卜上述貝牙私極20及配線層21也可由不同步驟 刀別形成。此外,貫穿電極20及配線層21,不一定藉由 =述之使用銅(Cu)的電解電鍍法來形成,亦可以其他 及成版方法來形成。貫穿電極2()及配線層u係由铭 (A〇或銘合金等所構成’也可以例㈣射法來形成。此 守同在含有弟2介層孔1G2的半導體基板⑺背面上,形成 來ΙΓ的阻障金屬層後,在該阻障金屬層上,藉由減射法 乂τ狄上述金屬構成的貫穿電極及配線層。然後,亦可在 :弟2層孔1G2的形成區域以外的該配線層上的預定 :域’形成未圖示的阻劑層,以該阻劑層為遮罩,將配線 、=以圖案化。或者,貫穿電極20及配線層21亦可以⑽ 法來形成。 =著’如第15圖所*’在含有第2介層孔⑽内的半 、體基板10背面上,亦即在阻障金屬層19上、貫穿電極 Φ 以及崎層21上,以包覆該等構件的方式形成保護 ' 。保濩層22係由例如阻劑材料等所構成。在第2保 護層22之中,在對應於配線層21的位置設有開口部。铁 ,’在該開口部露出的配線層21上,形成有由例如鲜錫等' i屬所構成的球狀導電端子23。 =著’如第16圖所示,沿著未圖示的切割線,將該半 =基板Π)切割。藉此方式’完成由具有貫穿電極2〇的 體晶片1 〇A構成的複數個半導體製置。 如上所述,根據本實施形態之半導體裝置及其製造方 317484 18 1276187 ,’在電路賴時等,探針與第2銲墊電 即使該第2 _極層u產生磨削等損;二接觸時, 13或插塞Η亦發揮保護層或緩衝層的作二,邑緣膜 以影響到第1銲塾電極層!2。亦即,可極力傷難 墊電極層12因上述損傷而產生破損。 Ρ 1 * 1銲 此外,上述探針接觸時,即使第2銲墊 半導體晶片10Α (半導體基板1〇 θ朝向 上述變形係藉由第2絕細或插塞 不會影響到帛1銲塾電極層12。亦即,可以極h 而 銲墊電極層12在介層孔的空間被押出而-曲變形:制第1 此外,第1銲墊電極層12及第2銲墊電極層
St:絕:膜13相連接,故可極力抑止第2銲墊電極: 15的變形。因此,可私制,筮 位屬 ^卩制在弟2介層孔102底部和蛊 1銲墊電極層12連接的貫穿電極 連 二弟 貫穿電極賴,鲜塾電極層12的連:二良靠:提升 如上所述’將第1銲墊電極層12用來 相連接,而且將第2鮮塾電極層15用來與探針相連::° 個銲塾電極層可以分別使用而不會降低其功能。結果,; 以提高具有貫穿電極之半導體裝置的可靠性及良率。 此外,在上述實施形態中,在開口部跡露:的 鮮塾電極層15,雖係作為半導體裝置進行電路測試等日士, 與未圖示之探針相連接之用的電極,但在本發明中並不才偈 限於此。例如,本發明亦可在開口部16W露出的第2銲墊 電極層15 ’形成未圖示的導電端子。此時,在形成有^導 317484 19 1276187 電端子的半導體裝置的表面上,亦可再層積其他半導體裝 置,而確立兩者電性連接。 此外,上述實施形態對於導電端子23的形成並無限 制。亦即’若貫穿電極20及配線層21可與未圖示的電路 基板電性連接,則並不—定需要形成導電端子B。例如, 半$版叙置為LGA ( Land Grip Array )型半導體裝置時, 並不需要在從保護層22局部露出的配線層21的一 上,形成導電端子23。 "刀 此夕卜,上述實施形態對於配線層21的形成並無限制。 ,、,、Ρ,右貫穿電極20完全嵌埋形成於第2介層孔1〇2時, 亚不一定需要形成配線層21。例如 叮 不透過配線層21及導電端子23,而直接貝:::^ 基板相連接。或者,貫穿電極2。係於:第=的電路 的開口部露出的該貫穿電極2。上具傷 不透過配線層21,而透過導電 ^ 板相連接。 舁未圖不的電路基 此外,在上述實施形態巾,雖然在成 極層”及第2銲塾電極層15之間的广塾電 定問陪拟士、士 1 牛、、、巴、、彖版13,以預 疋間㈣成有3個以上的插塞i 頂 此,亦可形成如以下所示之第'明並不限定為 第圖或弟18圖。第π圖及 〜、:本實施形態之半導體裝置的剖面圖。 ’、p,如第17圖所示,本發 將接觸第㈣電極層12及第2辉塾+電;::亦可為 部的插塞14Α,f坚电極層15的一方端 形成於弟2絕緣膜13者。或者,如第u 317484 20 ,1276187 : 料月之半導體裝置’亦可為將接觸第1銲墊電 ,及第2鲜塾電極層15的兩端的插塞 】 昂2絕緣膜13者。在此, 办成於 均形士 * ‘ 、插基14A、14B的任一者, J t成為·不重疊在與探針接 墊電極声12、15 一 率較向的第1及第2銲 才層12 15的十央或中央附近的區域。 於因此’在與探針接觸頻率較高的上述區域中,與第2 、、、巴緣臈13相接的第1録熱♦托 的;* 鲜墊电極層12及第2銲墊電極層15 ==擴散’第2銲墊電極層15的損傷或變形影響到^ 個層12的情形可更確實地加以抑制。並且,由於兩 形:電極層的黏接性增加’故可抑制銲墊電極層發生變 【圖式簡單說明】 之實施形態之半導體裝置的製造 之實施形態之半導體裝置的製造 之實施形態之半導體裝置的製造 之實施形態之半導體裝置的製造 弟1圖為說明本發明 方法之剖面圖。
第2圖為說明本發明 方法之剖面圖。 弟3圖為說明本發明 方法之剖面圖。 第4圖為說明本發明 方法之剖面圖。 乐5圖為說明本發明之實施形態之半導體裝置的製造 万法之剖面圖。 第6圖為說明本發明之實施形態之半導體裝置的製造 方法之剖面圖。 317484 1276187 第7圖為說明本發明之實施形態之半導體裝置的製造 方法之剖面圖。 第8圖為說明本發明之實施形態之半導體裝置的製造 方法之剖面圖。 、。 第9圖為說明本發明之實施形態之半導體裝置的製造 方法之剖面圖。 、。 ^第1〇圖為說明本發明之實施形態之半導體裝置之勢 k方法之剖面圖。 、 明之實施形態之半導體裝置之製 第11圖為說明本發 造方法之剖面圖。 之製 :12圖為說明本發明之實施形態之半導體 乂方法之剖面圖。 造方:夕 13圖為况明本發明之實施形態之半導體裝置之製 、々去之剖面圖。 之製 造=14圖為况明本發明之實施形態之半導體裝置 、乃法之剖面圖。 造方:圖為ϋ兒明本發明之實施形態之半導體裝置之製 J /无之剖面圖。 造方法之明本發明之實施形態之半導體裝置之製 面圖弟17圖為說明本發明之實施形態之半導體裝置之剖 面圖?圖為况明本發明之實施形態之半導體裝置之剖 317484 22 1276187 第19圖為顯示習知例之半導體裝置之製造方法之剖 面圖。 【主要元件符號說明】 10 半導體基板 10A 半導體晶片 11 第1絕緣膜 12 第1銲墊電極層 13 第2絕緣膜 14、 14A、14B 插塞 15 第2銲墊電極層 16 第1保護層 16W 開口部 18 第3絕緣膜 19 阻障金屬層 20 貫穿電極 20A 配線形成層 21 配線層 22 第2保護層 23 導電端子 41 第1阻劑層 42 第2阻劑層 43 第3阻劑層 44 第4阻劑層 45 第5阻劑層 50 半導體基板 51 第1絕緣膜 52 第1焊塾電極層 53 第2絕緣膜 53W 開口部 55 第2銲墊電極層 70 探針 101 第1介層孔 102 第2介層孔 23 317484
Claims (1)
- .1276187 十、申請專利範園·· l 一種半導體裝置’其特徵為具有: 半導體晶片; 第 在則述半導體晶片表面上隔著 銲墊電極層; 巴、、彖膜而形成白、j 形成在前述第1銲墊電極層上的第2絕緣膜. 形成在於前述第2絕緣膜开彡出 、、、 的金屬插塞; 緣㈣成開口的第1介層孔内 前述第?絕緣膜上,並透過前述金屬插塞與 極層電性連接的第2銲塾電極層; 2介層孔;以及 “心W塾電極層的第 形成於前述第2介層孔内,而且 與前述第1銲墊雷托®層孔 乙乐"于墊電極層電性連接的貫穿電極。 .如申請專利範圍第i項之半導體裝置,其中 形成在前述第2銲攀φ 设,、有: 絕緣膜上,並且:二層的一部分上及前述第2 豕胰上卫且具有露出該第 第1保護層; L層之開口部的 與前述貫穿電極電性連接, 片背面上的配線層;以及接且延伸至呵述半導體晶 以露 在前 在含有前述配線層的前述半導體晶片上 配線層之一部分上的方式形成的第2保護層 .如申請專利範圍第2項之铸體裝置,其中 線層的一部分上具有導電端子。 317484 24 1276187 4· 一種半導體裝置之製造方法,具有: 塾導體基板表面上,隔著第1絕緣膜形成第1銲 电極層的步驟,· 在2述第丨銲墊電極層上形成第2絕緣膜的步驟; 在前述第2絕緣膜,形成使前述第 出的第1介層孔的步驟; 層路 在f述第1介層孔内,形成金屬插塞的步驟; 述第2絕緣膜上,形成透過前述金屬插塞與前 M W塾電極層電性連接的第2銲墊電極層的步驟; ,=前述半導體基板㈣面到前述第旧塾電極 層的弟2介層孔的步驟; 性連接的2介層孔與前述第1銲塾電極層電 r逑接的貝牙電極的步驟;以及 片的=述半導體基板切斷分離成複數個的半導體晶 5.如申請專利範圍第4 中,復具有: 體衣置之製造方法,其 在包含前述第2銲墊雷描展 , 上,形成具有使前述第上 1保護層的步驟;、干墊電極層路出之開口部的第 形成與前述貫穿電極 體基板之背面上的配緩妾,且延伸至前述半導 、,上的配線層的步驟;以及 在含有前述配線居& 線層的-部分露出的“:处半導體基板上,以使該配 ^方式形成第2保護層的步驟。 317484 25 1276187 6·如申請專利範圍第5項之半導體裝置之製造方法,其 :,具有在前述配線層的—部分上形成導電端子时 一種半導體裝置之製造方法,具有·· ” f電性連接有複數贿墊電極層的半導體基板,形 成從前述半導體基板背面到前述複數個銲墊電極層中 距離5亥半導體基板表面較近的銲墊電極層之介層孔的 ▲形成透過前述介層孔,而與距離前述半導體基板表 面較近的銲墊電極層f性連接的貫穿電極的步驟;以及 將丽述半導體基板切斷分離成複數個半導 的步驟。 日日乃 8·如申請專利範圍帛7項之半導體裝置之製造方法,其 中具有·在半導體基板表面側,形成使前述複數個銲 墊包極層中距離該半導體基板表面較遠的銲 露出的開口部的步驟。 包桂層 317484 26
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JP4873517B2 (ja) | 2012-02-08 |
CN100428455C (zh) | 2008-10-22 |
EP1653510A3 (en) | 2009-09-02 |
US7646100B2 (en) | 2010-01-12 |
KR20060052241A (ko) | 2006-05-19 |
JP2006128352A (ja) | 2006-05-18 |
EP1653510A2 (en) | 2006-05-03 |
CN1779960A (zh) | 2006-05-31 |
TW200629444A (en) | 2006-08-16 |
US20060108691A1 (en) | 2006-05-25 |
KR100682434B1 (ko) | 2007-02-15 |
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