CN1881557A - 半导体内连接结构的顶金属线上的保护结构及其形成方法 - Google Patents
半导体内连接结构的顶金属线上的保护结构及其形成方法 Download PDFInfo
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- CN1881557A CN1881557A CN200610078791.5A CN200610078791A CN1881557A CN 1881557 A CN1881557 A CN 1881557A CN 200610078791 A CN200610078791 A CN 200610078791A CN 1881557 A CN1881557 A CN 1881557A
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- metal line
- top metal
- guard electrode
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Abstract
本发明是有关一种半导体内连接结构的顶金属线上的保护结构及其形成方法,其揭露了在一内连接结构的一顶金属线上形成一保护结构,特别是一种形成保护结构在一内连接结构的顶金属线上的方法,该方法至少包括以下步骤:提供一保护层于该顶金属线上;提供一电极开口或一连接垫于该顶金属线上的一保护层中;以及形成一贵重金属层的保护电极于该顶金属线上的该电极开口中。本发明结构在该顶金属线上的该保护层中提供一电极开口,以及在该顶金属线上的该电极开口中形成一保护电极,而可以排除经常存在于习知铝焊垫中的高浓度氟,因此可避免焊垫结晶缺陷以及后续晶片封装过程中接合失败。
Description
技术领域
本发明涉及一种在半导体晶圆上形成集成电路的方法,特别是涉及一种减少在一半导体晶圆上形成顶金属内连线的保护结构所需制程步骤的方法,该方法是在一保护层中形成一保护电极,以保护一顶金属内连线。
背景技术
许多固态元件的形成均需要利用平坦基底或者半导体晶圆,以在其表面形成集成电路(即积体电路)。在集成电路制程终结时,一半导体晶圆上的可用集成电路的最终数量或优良率,对半导体制造业者来说极度重要。因此,提升该晶圆上的电路优良率是为半导体制造业的主要目标。经过封装之后,该晶圆上的电路是被测试,其中无用晶片是利用涂墨步骤(inkingprocess)标记,而该晶圆上的可用电路是被分离并且出售。集成电路制造业者充分利用缩减晶片尺寸的方式,来提升一晶圆上的晶片优良率。超过1000个晶片可以形成于具有6到12英时直径的单一晶圆上。
多种制程步骤用于一半导体晶圆上形成集成电路,其中可能包括一双镶嵌制程(dual damascene process)。一典型的双镶嵌制程的流程如以下所示:金属层间介电层(IMD)沉积→介层窗(VIA)微影/蚀刻→金属前图案化(pre-patterning)→金属沟槽微影/蚀刻→物理气相沉积(PVD)金属阻障层(氮化钽等)/晶种层沉积(铜)→铜电镀(electroplating)→铜化学机械研磨(CMP)。
上述的复数个制程步骤是一步一步地施加于该晶圆上的多层导电层以及绝缘层,并且将其图案化以形成该电路。晶圆上可用电路的最终优良率有赖于制程步骤在各层的正确实施。该些层的正确实施则有赖于以经济而效率的方法在晶圆的表面均匀涂布材料。晶圆上的多种层是定义出电路组成或元件,例如电晶体等。
在晶圆基材上形成个别元件之后,必需连接各元件以表现想要的电路功用。此内连接制程通常被称为“金属化(metallization)”,并且利用一些不同微影、沉积、以及移除技术来实施。一般在内连接制程中,导电材料的二内连接通道是被金属层间介电层的垂直分开平面所分隔,并且是互相垂直,在二内连接通道的最接近点是藉由一垂直连接,或者介层窗,来互相连接。
请参阅图1A-1G所示,是显示现有习知的双保护以及一顶金属线上的铝焊垫的形成技术的剖面图,其为根据一习知方法在一传统金属内连接结构10中形成一保护铝焊垫及双保护层以保护一顶金属线的制程步骤的流程图。金属内连接结构10通常包括多层介电层12a-12f,该些介电层是依序沉积于一晶圆基底(图中未示)以及彼此上方。一底金属线16a、一中间金属线16b以及一顶金属线16c是分别形成于介电层12b、12d以及12f中。底介层窗14a是连接底金属线16a以及形成于晶圆基底的元件特征(图中未显示)。同样地,中间介层窗14b是连接中间金属线16b以及底金属线16a,并且顶介层窗14c是连接顶金属线16c以及中间金属线16b。
请参阅图1A所示,完成一顶金属线16c之后,一底保护停止层18以及一底保护层20是沉积于顶介电层12f以及顶金属线16c上。请参阅图1B所示,一光阻层22是接着沉积于顶保护层20上,并且进行图案化以形成一光阻开口23,其对应于后续形成的一保护铝焊垫的位置以及大小。请参阅图1C所示,接着蚀刻底保护层20以形成一焊垫开口21,其对应于光阻开口23的位置以及大小。接下来,光阻层22是自底保护层20上剥除,以及移除顶金属线16c上的底保护停止层18。一铝焊垫26是形成于底保护层20的焊垫开口21冲,并且位于顶金属线16c上方(如图1D所示)。一光阻层(图中未显示)是提供于铝焊垫26上,以蚀刻该铝焊垫形成想要的结构,之后将该光阻层剥除。
请参阅图1E所示,一顶保护层28是接着形成于铝焊垫26以及底保护层20上方。如图1F所示,具有一开口31的图案化光阻层30是形成于顶保护层28上,并且蚀刻开口31下方的顶保护层28以形成一开口29。如图1G所示,光阻层30是自顶保护层28上剥离。最后,氮氧化硅是自焊垫26上移除,接下来是利用氩处理以及湿式剥离将结构10中的高分子残留物移除。顶保护层28是预防铝焊垫26的刮伤以及剥落,而铝焊垫26可以预防顶金属线16c的腐蚀。
在接下来的封装制程中,以内连接结构10作为其部份结构的一集成电路(即积体电路)晶片(图中未显示)是组装于一更高阶的电子结构中。此涉及将一导线架的一内导线(图中未显示)打线接合于铝焊垫26,并且该导线架是电性接触该电子结构的元件。
以上图1A-1G描述的双保护层制程需要13个分离的制程步骤,因此造成一过长的制程周期时间。此外,该制程产生的铝焊垫26含有高浓度氟,增加了焊垫结晶(F-pad)缺陷的可能性,进而造成后续晶片封装过程中接合失败。
因此,需要一种减少在一半导体晶圆上形成顶金属内连线的保护/焊接结构所需制程步骤的方法。
有鉴于上述现有技术存在的缺陷,本发明人基于从事此类产品设计制造多年丰富的实务经验及专业知识,并配合学理的运用,积极加以研究创新,以期创设一种新的半导体内连接结构的顶金属线上的保护结构及其形成保护结构在一半导体内连接结构的顶金属线上的方法,使其更具有实用性。经过不断的研究、设计,并经反复试作及改进后,终于创设出确具实用价值的本发明。
发明内容
本发明的目的在于,提供一种新的半导体内连接结构的顶金属线上的保护结构及其形成方法,使其包括形成一保护电极,其位于一保护层中,用来保护一金属内连接结构的一顶金属内连接线,可以避免氧化、腐蚀、刮伤以及剥落,从而更加适于实用。
本发明的另一目的在于,提供一种半导体内连接结构的顶金属线上的保护结构及其形成方法,用以形成保护结构在一半导体内连接结构的顶金属线上,简化形成顶金属内连接线的保护/焊接结构的制程,因此而可大幅地缩段制程周期时间。
本发明的再一目的在于,提供一种半导体内连接结构的顶金属线上的保护结构及其形成方法,用以形成保护结构在一半导体内连接结构的顶金属线上,不需要利用一双保护结构来避免铝焊垫的刮伤以及剥落。
本发明的还一目的在于,提供一种半导体内连接结构的顶金属线上的保护结构及其形成方法,用以形成保护结构在一半导体内连接结构的顶金属线上,不需要利用一铝焊垫以及双保护结构来避免一顶金属线的腐蚀,而是利用一位于一保护层中的保护电极来保护该顶金属线,从而更加适于实用。
本发明的目的及解决其技术问题是采用以下技术方案来实现的。依据本发明提出的一种形成保护结构在一半导体内连接结构的顶金属线上的方法,该方法至少包括以下步骤:提供一保护层于该顶金属线上;提供一电极开口或一连接垫于该顶金属线上的一保护层中;以及形成一贵重金属层的保护电极于该顶金属线上的该电极开口中。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。
前述的方法,其中所述的顶金属线的材料是自铜及铝所构成的群组中选择其一。
前述的方法,其中所述的保护层是包括单一保护层。
前述的方法,其中所述的保护电极是包括复数层,并且各层的材料是自银、银合金、金、金合金、铂、铂合金、焊锡合金及其组合所构成的群组中选择其一。
前述的方法,其中所述的保护电极是具有一厚度小于约15000埃(angstroms)。
前述的方法,其中所述的保护电极是具有一厚度大于约300埃(angstroms)。
前述的方法,其中所述的形成该保护电极是包括利用电化学电镀(electrochemical plating)形成一保护电极。
前述的方法,其中所述的形成该保护电极是包括利用无电电镀(electroless plating)形成一保护电极。
本发明的目的及解决其技术问题还采用以下的技术方案来实现。依据本发明提出的一种半导体内连接结构的顶金属线上的保护结构,其至少包括:一基底;一介电层是提供于该基板上;一金属栓塞是提供于该介电层中;一金属线是提供于该金属栓塞上;一保护层,具有一电极开口是提供于该介电层上;以及一保护电极是提供于该金属线上的该电极开口中。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。
前述半导体元件结构,其中所述金属线的材料是自铜、铝、银、金、以及铂所构成的群组中选择其一。
前述的半导体元件结构,其中所述的保护电极包括复数层,并且各层的材料是自银、银合金、金、金合金、铂、铂合金、焊锡合金及其组合所构成的群组中选择其一。
前述的半导体元件结构,其中所述的保护电极是具有一厚度小于约15000埃(angstroms)。
前述的半导体元件结构,其中所述的保护电极是具有一厚度大于约300埃(angstroms)。
前述的半导体元件结构,其中所述的保护电极是利用电化学电镀(electrochemical plating)形成。
前述的半导体元件结构,其中所述的保护电极是利用无电电镀(electroless plating)形成。
本发明的目的及其解决其技术问题另外还采用以下的技术方案来实现。依据本发明提出的一种半导体内连接结构的顶金属线上的保护结构,其包括:一基底;一金属线是提供于该基底上;一保护层是提供于该金属线上;以及一保护电极是提供于该金属线上的该保护层中。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。
前述半导体元件结构,其中所述金属线的材料是自铜、铝、银、金、以及铂所构成的群组中选择其一。
前述的半导体元件结构,其中所述的保护电极的材料是自银、银合金、金、金合金、铂、铂合金、焊锡合金及其组合所构成的群组中选择其一。
本发明与现有技术相比具有明显的优点和有益效果。由以上技术方案可知,本发明是关于一形成保护结构在一半导体内连接结构的顶金属线上的方法,可减少在一半导体元件中形成顶金属内连线的保护/焊接结构所需制程步骤。该形成保护结构在一半导体内连接结构的顶金属线上的方法包括在一顶金属线上提供一保护层,在该保护层中蚀刻形成一电极开口,以及在该顶金属线上的该电极开口中形成一保护电极。该方法可明显地缩短形成顶金属线的保护以及焊接结构所需的制程周期时间,其是利用一银接合电极取代现有习知的铝焊垫用来增强保护铝焊垫避免刮伤以及剥落的双保护结构。此外,该方法可排除经常存在于一习知铝焊垫中的高浓度氟,因此可以避免焊垫结晶(F-pad)缺陷以及后续晶片封装过程中接合失败。
借由上述技术方案,本发明半导体内连接结构的顶金属线上的保护结构及其形成方法至少具有下列优点:
(1)、该方法可以明显的减少在一半导体元件中形成顶金属内连线的保护/焊接结构所需的制程步骤;
(2)、具有可增强保护铝焊垫避免刮伤以及剥落的双保护结构;
(3)、较现有习知的铝焊垫,可排除经常存在于习知铝焊垫中的高浓度氟,而具有较低的浓度氟;
(4)、可避免焊垫结晶(F-pad)的缺陷;以及
(5)、能增加后续晶片封装过程中接合成功率。
综上所述,本发明是有关于一种半导体内连接结构的顶金属线上的保护结构及其形成方法,该形成保护结构在一半导体内连接结构的顶金属线上的方法,是揭露了在一内连接结构的一顶金属线上形成一保护结构的方法。该方法包括在该顶金属线上的该保护层中提供一电极开口,以及在该顶金属线上的该电极开口中形成一保护电极。本发明具有上述诸多优点及实用价值,其不论在方法或功能上皆有较大的改进,在技术上有显著的进步,并产生了好用及实用的效果,从而更加适于实用,并具有产业的广泛利用价值,诚为一新颖、进步、实用的新设计。
上述说明仅是本发明技术方案的概述,为了能够更清楚了解本发明的技术手段,而可依照说明书的内容予以实施,并且为了让本发明的上述和其他目的、特征和优点能够更明显易懂,以下特举较佳实施例,并配合附图,详细说明如下。
附图说明
图1A-1G是显示现有习知的双保护以及一顶金属线上的铝焊垫的形成技术的剖面图。
图2A-2F是为剖面图,显示根据本发明的一方法是在顶金属线上的保护层中的电极开口形成一银连接电极以减少制程步骤。
图3是显示根据本发明实行的连续制程步骤的流程图。
图4是显示根据本发明形成的一半导体元件内连接结构的示意图。
10:金属内连接结构 12a~12f:介电层
14a~14c:介层窗 16a~16c:金属线
18:底保护停止层 20:顶保护层
21:连焊开口 23:光阻开口
22、30:光阻层 26:铝焊垫
28:顶保护层 29、31:开口
40:内连接结构 41:晶圆基底
42a~42f:介电层 44a~44c:介层窗
46a~46d:金属线 48:蚀刻停止层
50:保护层 52:光阻层
53:光阻开口 51:电极开口
56:保护电极 62:基底
60:内连接结构 66:金属栓塞
64:介电层 68:金属线
67:栓塞窗 72:电极开口
70:保护层 76:接合线
74:保护电极
具体实施方式
为更进一步阐述本发明为达成预定发明目的所采取的技术手段及功效,以下结合附图及较佳实施例,对依据本发明提出的减少形成金属线保护结构制程步骤的方法其具体实施方式、方法、步骤、特征及其功效,详细说明如后。
请参阅图2A-图2F所示,是显示本发明实施一减少制程步骤方法来形成一金属线的保护结构。除非特别提及,该形成保护结构在一半导体内连接结构的顶金属线上的方法的实施是利用熟知该项技艺者所知悉的沉积以及蚀刻技术。一实施例的内连接结构40包括多层介电层42a-42f,该些介电层是分别利用习知沉积技术以依序沉积于一晶圆基底41以及彼此上方。底介层窗44a是延伸穿过介电层42a,并且连接一介电层42b中的一底金属线46a以及形成于晶圆基底的元件特征(图中未示)。中间金属线46b是形成于介电层42d中。中间介层窗44b是连接中间金属线46b以及底金属线46a。一顶介层窗44c是延伸穿过介电层42e,并且连接顶金属线46c以及中间金属线46b。金属线46a-46c以及介层窗44a-44c是利用一双镶嵌制程形成于各层。一顶金属线46c是形成于顶介电层42f中,顶金属线46c可能为,举例来说,如铜、铝、银、金、或铂。
请参阅图2A所示,根据本发明的形成保护结构在一半导体内连接结构的顶金属线上的方法制程中的第一步骤,一蚀刻停止层48是形成于顶介电层42f以及金属线46c的上表面。蚀刻停止层48例如为氮化硅。一保护层50是接着形成于蚀刻停止层48上。
请参阅图2B所示,一光阻层52可利用一旋转涂布制程以形成于保护层50上。光阻层52经图案化后形成一或多个光阻开口53。各光阻开口53的大小以及位置是对应于后续在顶金属线46d上方形成的一银接合电极的大小以及位置(如以下所述)。
请参阅图2C所示,接着是向下蚀刻保护层50直至蚀刻停止层48,以在光阻开口53下方形成电极开口51。电极开口51是延伸穿过保护层50并且暴露蚀刻停止层48。如笫2D图所示,光阻层52(第2C图)是自其下方的保护层50被剥离,此步骤通常包括依序对光阻层50实施一干式剥离步骤以及一湿式剥离步骤。接着如第2E图所示,蚀刻停止层48是被移除,以藉由电极开口51暴露顶金属线46d的顶表面。后续可能进行一湿式以及干式剥离制程,以移除内连接结构40中的高分子残留物。
请参阅图2F所示,一保护电极56是接着形成于电极开口51中,并且位于顶金属线46d上方。此步骤的实施可能利用一电化学电镀技术,或者相对地,利用一无电电镀(化学电镀)技术。保护电极56的材料可能是银、银合金、金、金合金、铂、铂合金、焊锡合金及其组合。在另一实施例中,该保护电极56包括多层,并且其中任一层的材料是为银、银合金、金、金合金、铂、铂合金、焊锡合金及其组合。保护电极56的厚度约大于300埃(angstroms)或者小于15000埃(angstroms)。
形成保护电极56之后,内连接结构40,作为形成于一半导体晶圆(图中未显示)上的多数集成电路晶片(图中未显示)其中之一晶片的部份结构,是与一电子结构(图中显示)接合。此步骤涉及利用金线连接一接合线(图中未显示)与保护电极56,该接合线是连接于一导线架,而该导线架是电性连接该电子结构。保护电极56是与该晶片封装制程相容,并且可防止发生于习知铝焊垫的连接垫结晶(F-pad)的缺陷。此外,保护电极56是可有效地预防位于下方的顶金属线46d的氧化、腐蚀,以及避免习知铝焊垫的刮伤以及剥落。
请参阅图3所示,是根据本发明方法实行的连续制程步骤的流程图。在步骤1,一蚀刻停止层以及一保护层是依序沉积于一金属内连接结构的一顶金属线上。在步骤2,是图案化并且显影该保护层上方的该光阻层,并且在该保护层中蚀刻形成有一电极开口。在步骤3,该光阻层是自该保护层上剥离。在步骤5,是实施一干式以及一湿式剥离制程,以从该内连接结构移除高分子残留物。在步骤6,一保护电极是准备沉积于该保护电极的该电极开口中,并且是位于该顶金属线上方。
接着请参阅图4所示,是显示根据本发明的另一实施例方法制作的一内连接结构60。该内连接结构60包括一基底62,举例来说,该基底可能为一硅晶圆基底、一介电层、或者一金属层。一介电层64,可以为一金属层间介电层(intermetal dielectric,IMD)或者层间介电层(interlayerdielectric,ILD),是形成于基底62上。一金属栓塞66是延伸经过一蚀刻穿透介电层64的栓塞窗67。一金属线68是形成于介电层64上,并且与金属栓塞66电性连接。该金属线可为铜、铝、银、金、铂、或铜化铝。
一保护层70是形成于介电层64以及金属线68上,一电极开口72是延伸穿透保护层70。一保护电极74是形成于电极开口72中,并且是位于金属线68的上方。保护电极74可为银、银合金、金、金合金、铂、铂合金、焊锡合金及其组合,并且可为单一层或者多层。保护电极74通常具有300~15000埃(angstroms)的厚度,并且是利用电化学电镀或者无电电镀形成。一接合线76与金属线68接合,以连接内连接结构60以及一导线架(图中未显示)。该导线架是电性连接一电子结构(图中未显示),并且内连接结构60是作为该电子结构的一部份。
以上所述,仅是本发明的较佳实施例而已,并非对本发明作任何形式上的限制,虽然本发明已以较佳实施例揭露如上,然而并非用以限定本发明,任何熟悉本专业的技术人员,在不脱离本发明技术方案范围内,当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例,但凡是未脱离本发明技术方案内容,依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰,均仍属于本发明技术方案的范围内。
Claims (18)
1、一种形成保护结构在一半导体内连接结构的顶金属线上的方法,其特征在于该方法至少包括以下步骤:
提供一保护层于该顶金属线上;
提供一电极开口或一连接垫于该顶金属线上的一保护层中;以及
形成一贵重金属层的保护电极于该顶金属线上的该电极开口中。
2、根据权利要求1所述的方法,其特征在于其中所述的顶金属线的材料是自铜及铝所构成的群组中选择其一。
3、根据权利要求1所述的方法,其特征在于其中所述的保护层是包括单一保护层。
4、根据权利要求1所述的方法,其特征在于其中所述的保护电极是包括复数层,并且各层的材料是自银、银合金、金、金合金、铂、铂合金、焊锡合金及其组合所构成的群组中选择其一。
5、根据权利要求1所述的方法,其特征在于其中所述的保护电极是具有一厚度小于约15000埃(angstroms)。
6、根据权利要求1所述的方法,其特征在于其中所述的保护电极是具有一厚度大于约300埃(angstroms)。
7、根据权利要求1所述的方法,其特征在于其中所述的形成该保护电极是包括利用电化学电镀(electrochemical plating)形成一保护电极。
8、根据权利要求1所述的方法,其特征在于其中所述的形成该保护电极是包括利用无电电镀(electroless plating)形成一保护电极。
9、一种半导体内连接结构的顶金属线上的保护结构,其特征在于其至少包括:
一基底;
一介电层是提供于该基板上;
一金属栓塞是提供于该介电层中;
一金属线是提供于该金属栓塞上;
一保护层,具有一电极开口是提供于该介电层上;以及
一保护电极是提供于该金属线上的该电极开口中。
10、根据权利要求9所述的半导体内连接结构的顶金属线上的保护结构,其特征在于其中所述的金属线的材料是自铜、铝、银、金、以及铂所构成的群组中选择其一。
11、根据权利要求9所述的半导体内连接结构的顶金属线上的保护结构,其特征在于其中所述的保护电极包括复数层,并且各层的材料是自银、银合金、金、金合金、铂、铂合金、焊锡合金及其组合所构成的群组中选择其一。
12、根据权利要求9所述的半导体内连接结构的顶金属线上的保护结构,其特征在于其中所述的保护电极是具有一厚度小于约15000埃(angstroms)。
13、根据权利要求9所述的半导体内连接结构的顶金属线上的保护结构,其特征在于其中所述的保护电极是具有一厚度大于约300埃(angstroms)。
14、根据权利要求9所述的半导体内连接结构的顶金属线上的保护结构,其特征在于其中所述的保护电极是利用电化学电镀(electrochemicalplating)形成。
15、根据权利要求9所述的半导体内连接结构的顶金属线上的保护结构,其特征在于其中所述的保护电极是利用无电电镀(electrolessplating)形成。
16、一种半导体内连接结构的顶金属线上的保护结构,其特征在于其包括:
一基底;
一金属线是提供于该基底上;
一保护层是提供于该金属线上;以及
一保护电极是提供于该金属线上的该保护层中。
17、根据权利要求16所述的半导体内连接结构的顶金属线上的保护结构,其特征在于其中所述的金属线的材料是自铜、铝、银、金、以及铂所构成的群组中选择其一。
18、根据权利要求16所述的半导体内连接结构的顶金属线上的保护结构,其特征在于其中所述的保护电极的材料是自银、银合金、金、金合金、铂、铂合金、焊锡合金及其组合所构成的群组中选择其一。
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US7335955B2 (en) * | 2005-12-14 | 2008-02-26 | Freescale Semiconductor, Inc. | ESD protection for passive integrated devices |
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US8502335B2 (en) | 2009-07-29 | 2013-08-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | CMOS image sensor big via bonding pad application for AlCu Process |
US8344471B2 (en) | 2009-07-29 | 2013-01-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | CMOS image sensor big via bonding pad application for AICu process |
US8803292B2 (en) | 2012-04-27 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-substrate vias and methods for forming the same |
US8624324B1 (en) | 2012-08-10 | 2014-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Connecting through vias to devices |
US9006900B2 (en) * | 2013-03-11 | 2015-04-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with advanced pad structure resistant to plasma damage and method for forming the same |
JP6331225B2 (ja) * | 2015-08-19 | 2018-05-30 | 株式会社安川電機 | モータ制御装置、位置制御システム、及びモータ制御方法 |
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JP2563652B2 (ja) * | 1990-07-17 | 1996-12-11 | 株式会社東芝 | 半導体装置及びその製造方法 |
US5346858A (en) * | 1992-07-16 | 1994-09-13 | Texas Instruments Incorporated | Semiconductor non-corrosive metal overcoat |
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