CN1783478A - 改善电子迁移的半导体元件与半导体元件的形成方法 - Google Patents

改善电子迁移的半导体元件与半导体元件的形成方法 Download PDF

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CN1783478A
CN1783478A CN200510088729.XA CN200510088729A CN1783478A CN 1783478 A CN1783478 A CN 1783478A CN 200510088729 A CN200510088729 A CN 200510088729A CN 1783478 A CN1783478 A CN 1783478A
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semiconductor element
barrier layer
layer
glue
electron transfer
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CN100385660C (zh
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张中良
谢静华
眭晓林
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种改善电子迁移的半导体元件与半导体元件的形成方法，所述改善电子迁移的半导体元件，包括表面具有开口的介电层，阻隔层位于开口内，胶层位于阻隔层上，以及导体位于胶层上，以填充开口。本发明所述改善电子迁移的半导体元件与半导体元件的形成方法，是一种改良的结构与方法，其解决了现有技术中内连线有关电子迁移的问题。

Description

改善电子迁移的半导体元件与半导体元件的形成方法
技术领域
本发明是有关于一种半导体元件制造，且特别有关于一种改良的结构与方法，以解决内连线有关电子迁移的问题。
背景技术
在最新的集成电路(IC)中，元件尺寸，如场效应晶体管(MOSFET)的沟道长度，已经达到深次微米的等级，以使电路的速度增快且减少功率的消耗，当各电路元件的尺寸缩小时，内连线的尺寸也会跟着缩小，所以每晶片的电路元件就会增加。
IC的尺寸已缩小至0.35μm以下，但过小的元件却会因晶体管元件的转换速度(switching speed)而产生信号延迟的现象，当晶体管的沟道长度为0.18μm以下时，邻近导体结构间的电阻就会有问题，所以针对寄生RC时间常数的问题，就需要新的材料与方法来形成金属内连线。
传统上金属内连线间为堆叠的介电层，此介电层如包括二氧化硅与/或氮化硅，而金属层常用铝形成，由于铝在较高电流密处经过时会产生很大的电子迁移，所以目前以铜取代之，铜具有较低的电阻，可以降低电子迁移的问题。
然而铜的使用却会产生许多额外问题，如铜无法利用现行的方法大量沉积(化学与物理气相沉积)，再者，铜无法利用现行的非等向性蚀刻进行有效的图案化处理，所以就利用镶嵌技术来形成包含铜线的金属化层，在传统的镶嵌技术中，是先沉积介电层、形成沟槽与介层洞，再用电镀方式将铜填入，如利用电镀或无电镀方式。
铜的另一缺点是它很容易扩散到氧化硅中，这会对元件的效能造成负面影响，甚至使元件完全毁损，所以在铜表面与其邻近材料间必须提供一扩散阻隔来防止此现象的发生，而氮化硅常用来作铜阻隔层，来将铜与层间介电层如二氧化硅隔离。
虽然铜比铝的电子迁移阻性要好，但在元件尺寸持续缩小而增加电流密度的趋势下，会使铜的电子迁移变成无法接受的程度，电子迁移是因电场影响所产生的扩散现象，这电场会使铜沿着电荷载流子移动的方向扩散，这会使铜产生破洞，进而造成元件的损毁，这些破洞常会在氮化硅/铜的界面产生，此为铜金属化结构最常见的主要扩散路径，所以制作高品质的铜与阻隔层的界面，以降低电子迁移至可接受的程度是相当重要的。
如前所述，超大集成电路的元件效能会被邻接内连线的寄生电容所限制，而通过降低其电阻以及介电层的整体介电常数可使寄生电容降低。由于氮化硅的介电常数约为7左右，相对的比二氧化硅4左右或其它以二氧化硅为主的介电层(小于4)要来得高，所以一般希望氮化硅的厚度薄点较好，然而氮化硅的阻隔特性是与其厚度相关，所以在降低整体介电常数而将氮化硅厚度减少的同时，却会使得半导体的元件效能降低。
如上所述，故业界急需提出一种可以解决上述问题的阻隔层，以改善扩散阻隔效率、电子迁移阻性、降低寄生电阻与其它问题。
发明内容
有鉴于此，本发明的目的之一就是提供一种半导体元件，以解决上述与其它问题。
为迭上述目的，本发明提供一种改善电子迁移的半导体元件，包括表面具有开口的介电层；阻隔层位于开口内；胶层位于阻隔层上；以及导体位于胶层上，以填充开口。
本发明所述的改善电子迁移的半导体元件，尚包括一盖层位于该导体上，其中该盖层主要择自Co、W、Al、Ta、Ti、Ni、Ru与其组合所组成的族群。
本发明所述的改善电子迁移的半导体元件，该阻隔层包括第一阻隔层于该开口内与第二阻隔层于该第一阻隔层上。
本发明所述的改善电子迁移的半导体元件，该阻隔层是经过一热处理以增加附着度。
本发明所述的改善电子迁移的半导体元件，该阻隔层的厚度约为10埃至30埃。
本发明所述的改善电子迁移的半导体元件，尚包括一盖层主要择自一含碳介电材、一含氮介电材、一含氮导体、一含硅导电层、硅与其组合所组成的族群。
本发明所述的改善电子迁移的半导体元件，该胶层主要择自一富含金属氮化物、Ru、Ta、Ti、W、Co、Ni、Al、Nb、AlCu与其组合所组成的族群。
本发明所述的改善电子迁移的半导体元件，该胶层与该阻隔层的厚度比约为1～50。
本发明所述的改善电子迁移的半导体元件，该胶层的厚度约为10埃至500埃。
本发明所述的改善电子迁移的半导体元件，该富含金属氮化物包括TaN，其中N对Ta的原子比约小于1。
为达上述目的，本发明尚提供一种降低铜镶嵌元件的电子迁移的方法，包括形成表面具有开口的介电层；形成阻隔层于开口内；形成胶层于阻隔层上；以导体填充开口；对导体进行退火处理；以及形成盖层于导体上。
为达上述目的，本发明尚提供一种半导体元件的形成方法，包括提供包括具有开口的介电层的基底；执行孔洞密封制程；形成阻隔层于开口中；形成胶层于阻隔层上；形成晶种层于胶层上；形成导体于晶种层上；以及形成盖层于导体上。
本发明所述的半导体元件的形成方法，该盖层主要择自Co、W、Al、Ta、Ti、Ni、Ru与其组合所组成的族群。
本发明所述的半导体元件的形成方法，该阻隔层的厚度约为10埃至30埃。
本发明所述的半导体元件的形成方法，该盖层主要择自一含碳介电材、一含氮介电材、一含氮导体、一含硅导电层、硅与其组合所组成的族群。
本发明所述的半导体元件的形成方法，该胶层主要择自一富含金属氮化物、Ru、Ta、Ti、W、Co、Ni、Al、Nb、AlCu与其组合所组成的族群。
本发明所述的半导体元件的形成方法，该胶层与该阻隔层的厚度比约为1～50。
本发明所述的半导体元件的形成方法，该胶层的厚度约为10埃至500埃。
本发明所述的半导体元件的形成方法，该富含金属氮化物包括TaN，其中N对Ta的原子比约小于1。
本发明所述改善电子迁移的半导体元件与半导体元件的形成方法，是一种改良的结构与方法，其解决了现有技术中内连线有关电子迁移的问题。
附图说明
图1为一镶嵌制程中的半导体元件剖面图，用以说明本发明较佳实施例的阻隔层；
图2显示本发明的较佳实施例，包括阻隔层、胶层与晶种层；
图3为一本发明较佳实施例的剖面图，显示一导体沉积于胶层上；
图4为本发明较佳实施例的CMP平坦化图；
图5为一剖面图，用以显示本发明较佳实施例的盖层；
图6为一流程图，用以说明本发明较佳实施例的制程流程。
具体实施方式
本发明较佳实施例的操作与制造将于下进行描述，然而本发明的应用与使用并非只限于在此所描述的内容，这些特定的实施例只是对本发明作说明用，并非用来限定发明的内容或申请专利范围。
本发明是有关于一种半导体元件制造，且特别有关于一种改良的结构与方法，以解决内连线有关电子迁移的问题，本发明较佳实施例的内容为镶嵌制程中铜导线与介层洞的制造，本领域技术人员应了解本发明不只对镶嵌制程有利，对其它改善扩散阻隔或电子迁移的半导体制造应用以及其它未提及的IC内连线应用也同样有利，因此，以下所述的实施例只属说明本发明与其使用方式，并非限定本发明的范围。
请参阅图1，此图显示镶嵌中结构100的剖面图，此结构100形成于半导体基底102的表面中，此为本发明的实施例所要处理的镶嵌结构。此基底102如可包括功能性或逻辑性元件，或是包括其它内连线层，详细的镶嵌制程可参考Bao等人的美国专利第6,248,665号与美国专利公开第2004/0121583号。
图1显示本发明应用例的部分半导体元件的剖面图，图中显示此元件具有经非等向性蚀刻处理、制造中的双镶嵌结构100，此制造中的双镶嵌结构100具有介层洞104与沟槽106，有许多方式可形成双镶嵌结构，其一为利用至少两光微影图案化与非等向性蚀刻步骤，以先形成介层开口104，再利用类似制程在一个或多个介层开口104上形成沟槽开口106。
依然请参阅图1，例如以氮化硅所形成的第一蚀刻停止层103形成于导体区108上，例如铜镶嵌结构。如在现有的镶嵌制程，“铜”一字包括适用的铜合金，第一蚀刻停止层103上方是另一绝缘介电层112，也称为金属间介电(IMD)层。
IMD层112为低介电常数(即介电常数小于4)介电质，如为有机金属硅玻璃(OSG)与含碳氧化物，在另一实施例中，低介电常数材料可包括硼磷硅玻璃(BPSG)、硼硅玻璃(BSG)、磷硅玻璃(PSG)，且以5000～9000埃的厚度沉积于半导体结构表面上，且较佳经平坦化处理，此外，有机低介电常数材料包括聚亚芳香醚(polyarylene ether)、含氢硅酸盐(hydrogensilesquioxane，HSQ)、甲基硅酸盐(methyl silesquioxane，MSQ)、聚硅酸盐(polysilesquioxane)、聚亚酰胺(polyimide)、苯环丁烯(benzocyclobutene)与非晶铁氟龙(Teflon)，本发明的其它类型的低介电常数材料包括氟硅玻璃(FSG)与多孔氧化物，在一较佳实施例中，低介电常数材料较佳含C、O、Si与F，如掺杂氟的-(O-Si(CH3)2-O)-。
位于低介电常数材料如IMD层112中的开孔会降低元件效能，因此实施例中的孔洞密封方法包括利用Ar与NH3的等离子孔洞密封、电子束孔洞密封、有机金属孔洞密封、或较佳为气相孔洞密封，在较佳实施例中，低介电常数表面会用四甲基硅烷(4MS)在约400℃下处理，此4MS可用三甲基硅烷、二甲基硅烷或甲基硅烷取代，此气相可由有机或有机金属分子组成，且较佳具有大于10埃的尺寸，且在约350～450℃下处理约5～30秒。
在电子束孔洞密封中，所使用的电子束的条件一般为2000～5000keV、1～6mA、75～100μC/cm2，等离子孔洞密封是利用Ar等离子轰击低介电常数表面，以使双镶嵌侧壁空洞封住。
依然请参阅图1，蚀刻停止层114形成于IMD层112上，且可包括如氮化硅与/或氮氧化硅(Si0N)，以作为蚀刻停止与抗反射涂布(ARC)层，且其厚度较佳为500～1500埃。
双镶嵌结构100的形成是在蚀刻停止层114、IMD层112与至少部分第一蚀刻停止层103中通过微影图案化与非等向性蚀刻而形成介层开口104，再利用类似的光微影图案化与非等向性蚀刻制程在蚀刻停止层114与部分IMD层112中形成沟槽开口106，这些步骤会使沟槽开口106形成于一个或多个介层开口104上，且沟槽开口106与介层开口104分别形成在中间夹有蚀刻停止层114的堆叠IMD层112中。
依然请参阅图1，全面性沉积阻隔层116，以使阻隔层116至少沿着双镶嵌开口形成，阻隔层116的厚度较佳为10～30埃，以作为Cu阻隔层，阻隔层116可包括金属氮化物，如TaN、TiN、WN、TbN、VN、ZrN、CrN、WC、WN、WCN、NbN、AlN与其组合。在另一实施例中，阻隔层116可为整体或只在表面富含金属(metal rich)，而富含金属(metal rich)的阻隔层的氮对金属的原子比较佳小于1。
在另一实施例中，阻隔层包括位于低介电常数表面上的第一阻隔层与位于第一阻隔层上的第二阻隔层，第一阻隔层为原子层沉积(ALD)材料，主要择自Ta、W与其组合，而第二阻隔层主要择自Ni、Co、Al、AlCu合金、W、Ti、Ta、Ra、Ru与其组合，而铜晶种层可视需要沉积于第二阻隔层上。
阻隔层116可利用物理气相沉积(CVD)、化学气相沉积(CVD)、等离子增进式化学气相沉积(PECVD)或等离子增进式原子层沉积(PEALD)沉积，在一较佳实施例中，阻隔层116是利用原子层沉积(ALD)所形成的TaN。
在双镶嵌结构中，利用原子层沉积(ALD)所形成的TaN阻隔层116，可降低电容与电阻迁移效应，当半导体尺寸持续地缩小，导体结构间的电容问题会越来越严重，由ALD所形成的阻隔层116比其它如PVD制程较佳，在此较佳实施例中，由ALD所形成的TaN阻隔层116在邻近导体间的寄生电容要比PVD制程大幅降低约11.5％，因此ALD沉积的阻隔层可使金属线做得更薄，因为具有ALD阻隔的金属线具有较低的有效电阻。
在另一实施例中，阻隔层116包括Ta/TaN双层结构，此双层结构包括PEALD TaN与ALD Ta、ALD TaN与PEALD Ta、或PEALD TaN与PEALD Ta。
请参阅图2，在较佳实施例中，胶层118形成于阻隔层116与导体(如下述，请参阅图3的120)间，以增加其附着度，胶层118较佳包括可黏着铜与/或阻隔层的材料，且其厚度约10～500埃，较佳小于约150埃，材料也以富含金属(metalrich)材料较佳。
在另一实施例中，胶层118较佳包括两层(未特别绘出)，第一层较佳为130～170埃的富含金属(metal rich)薄层，且其厚度较佳为150埃，第二层为500～600埃的化学计量组成金属氮化物层，且其厚度较佳为550埃，胶层118可利用PVD、CVD、PECVD、PEALD形成，且较佳以沉积速率小于1埃/sec、约100～300℃的ALD形成。
在另一实施例中，胶层118可为Ru、Ta、Ti、W、Co、Ni、Al、Nb、AlCu合金与其组合，在一较佳实施例中，胶层118与阻隔层116的厚度比约为1～50。
在沉积导体之前，晶种层119可视需要以PVD与/或CVD沉积于胶层118上，较佳为铜的晶种层119可以PVD在晶圆表面上沉积约400～700埃的连续层，以提供连续的导电表面在电化学沉积(ECD)制程时形成铜块材。
依然请参阅图2，接下来较佳于300℃下进行约1分钟的退火处理，以降低堆叠的阻隔层/胶层/晶种层的有效电阻，一般而言，包括Ta与Co的胶层最好。
在本发明另一实施例中，还有另一方式可改善阻隔层其邻近层间的附着度，上述的阻隔层沉积尚可利用包括如电子束退火或快速热处理(RTP)进行热处理，以增进阻隔层与铜层间的可湿性(wetability)与/或附着度。
在阻隔层的ALD沉积时，较佳在其间执行一热附着度制程，一般而言，阻隔层如ALD TaN的形成包括许多步骤，首先利用Ta前驱物以形成饱和表面层，接下来利用NH3还原且氮化饱和表面层，以形成TaxNy单层，而热附着度处理是于此两制程间执行，若以WCN为阻隔层时，就需要三步沉积制程，而热附着度是于还原步骤前执行，RTP是于ALD反应室中进行，且其温度约为200～400℃。
请参阅图3，在沉积胶层118后，再利用电镀如一般电化学沉积(ECD)制程填充双镶嵌沟槽106与介层洞104，在另一实施例中，晶种层(未显示)位于胶层118与导体120间，虽然可利用如PVD与CVD等其它同填充方法，较佳还是利用电镀(电沉积)方式，因为它具有较好的间隔填充能力与阶梯覆盖度，在其它的实施例中，导体120至少包括Cu、Al、Au、Ag与其组合或合金。
接下来可利用化学机械研磨(CMP)使导体与元件对齐。在另一实施例中，可利用电研磨或过载还原(overburdenreduction)取代CMP，或与CMP一起使用，此外，可执行同步的CMP与电镀制程，如图4所示，CMP制程会产生凹蚀区121，因为导体120较软。
依然请参阅图4，在另一实施例中，是将凹蚀的导体上方部分122移除，通过氧化暴露的导体(如铜)上方部分122，使凹蚀区121的深度增加，然后利用另一CMP步骤或湿蚀刻步骤将铜构件上方氧化部分122移除。
在CMP平坦化后，另一较佳实施例包括晶种层(未显示)与导体120退火步骤，且此退火步骤较佳于150～450℃、N2/H2形成气体下处理约0.5～5分钟，此退火步骤会使晶种层中的金属位移或扩散至铜填充层(120)中，以形成铜金属填充层(120)，较佳者，铜晶种层包括钛，退火处理会使导体层120中的Ti形成大致的分布，且形成均匀的铜-钛填充层(120)，且退火处理会在导体层120表面形成颗粒(granularity)，以增进导体层120与其上的盖层(如图5所示)间的附着度。
请参阅图5，在本发明实施例经CMP处理后，再于镶嵌结构上沉积盖层124，此层厚度较佳为50～500埃，以防止铜的扩散，且可由一般ALD、PVD、PECVD、PEALD与/或CVD等方式沉积，包括现有的氮化与硅化方式，盖层124较佳包括至少一层W、Al、Ta、Ti、Ni、Ru或其氮化物，较佳为以CVD或ALD所沉积的Co或氮化钴盖层。
在另一实施例中，盖层包括至少一层含碳介电质(如SiC、SiOC、SiCN)、含氮介电质、含氮导体层或含硅层。
请参阅图5，在CMP与盖层制程后，可沉积氮化硅蚀刻停止层126于制程晶圆表面上，以覆盖铜构件上的阻隔盖层。
请参阅图6，此图显示本发明多个较佳实施例的流程图。在制程602中，提供一基底，且此基底包括形成于低介电常数绝缘层(ILD)中的构件开口；在制程604中，将低介电常数质的孔洞密封住；在制程605中，金属氮化阻隔层沿着开口形成；在制程606中，对阻隔层进行处理，以增加其附着度；在制程608中，形成富含金属(metal rich)的氮化物胶层；在制程610中，形成铜晶种层；在制程612中，开口以导体填充；在制程614中，对结构进行CMP处理；在制程616中，对导体执行退火处理；在制程618中，形成盖层。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。
附图中符号的简单说明如下：
85：开口
100：结构
102：基底
103、114、126：蚀刻停止层
104：介层洞
106：沟槽
108：导体区
110、112：介电层
116：阻隔层
118：胶层
119：晶种层
120：导体
121：凹蚀区
122：导体上方
124：盖层

Claims (18)

1、一种改善电子迁移的半导体元件，所述改善电子迁移的半导体元件包括：
一介电层，该介电层具有一开口；
一阻隔层位于该开口内；
一胶层位于该阻隔层上；以及
一导体位于该胶层上，该导体填充该开口。
2、根据权利要求1所述的改善电子迁移的半导体元件，其特征在于：尚包括一盖层位于该导体上，其中该盖层主要择自Co、W、Al、Ta、Ti、Ni、Ru与其组合所组成的族群。
3、根据权利要求1所述的改善电子迁移的半导体元件，其特征在于：该阻隔层包括第一阻隔层于该开口内与第二阻隔层于该第一阻隔层上。
4、根据权利要求1所述的改善电子迁移的半导体元件，其特征在于：该阻隔层是经过一热处理以增加附着度。
5、根据权利要求1所述的改善电子迁移的半导体元件，其特征在于：该阻隔层的厚度为10埃至30埃。
6、根据权利要求1所述的改善电子迁移的半导体元件，其特征在于：尚包括一盖层主要择自一含碳介电材、一含氮介电材、一含氮导体、一含硅导电层、硅与其组合所组成的族群。
7、根据权利要求1所述的改善电子迁移的半导体元件，其特征在于：该胶层主要择自一富含金属氮化物、Ru、Ta、Ti、W、Co、Ni、Al、Nb、AlCu与其组合所组成的族群。
8、根据权利要求1所述的改善电子迁移的半导体元件，其特征在于：该胶层与该阻隔层的厚度比为1～50。
9、根据权利要求1所述的改善电子迁移的半导体元件，其特征在于：该胶层的厚度为10埃至500埃。
10、根据权利要求7所述的改善电子迁移的半导体元件，其特征在于：该富含金属氮化物包括TaN，其中N对Ta的原子比小于1。
11、一种半导体元件的形成方法，所述半导体元件的形成方法包括：
提供一基底，该基底包括具有一开口的一介电层；
执行一孔洞密封制程；
形成一阻隔层于该开口中；
形成一胶层于该阻隔层上；
形成一晶种层于该胶层上；
形成一导体于该晶种层上；以及
形成一盖层于该导体上。
12、根据权利要求11所述的半导体元件的形成方法，其特征在于：该盖层主要择自Co、W、Al、Ta、Ti、Ni、Ru与其组合所组成的族群。
13、根据权利要求11所述的半导体元件的形成方法，其特征在于：该阻隔层的厚度为10埃至30埃。
14、根据权利要求11所述的半导体元件的形成方法，其特征在于：该盖层主要择自一含碳介电材、一含氮介电材、一含氮导体、一含硅导电层、硅与其组合所组成的族群。
15、根据权利要求11所述的半导体元件的形成方法，其特征在于：该胶层主要择自一富含金属氮化物、Ru、Ta、Ti、W、Co、Ni、Al、Nb、AlCu与其组合所组成的族群。
16、根据权利要求11所述的半导体元件的形成方法，其特征在于：该胶层与该阻隔层的厚度比为1～50。
17、根据权利要求11所述的半导体元件的形成方法，其特征在于：该胶层的厚度为10埃至500埃。
18、根据权利要求15所述的半导体元件的形成方法，其特征在于：该富含金属氮化物包括TaN，其中N对Ta的原子比小于1。
CNB200510088729XA 2004-12-01 2005-07-29 改善电子迁移的半导体元件与半导体元件的形成方法 Active CN100385660C (zh)

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