CN1832159A - 半导体元件 - Google Patents

半导体元件 Download PDF

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Publication number
CN1832159A
CN1832159A CNA2005101126775A CN200510112677A CN1832159A CN 1832159 A CN1832159 A CN 1832159A CN A2005101126775 A CNA2005101126775 A CN A2005101126775A CN 200510112677 A CN200510112677 A CN 200510112677A CN 1832159 A CN1832159 A CN 1832159A
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China
Prior art keywords
layer
electroconductive polymer
copper
semiconductor element
dielectric layer
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CNA2005101126775A
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CN100399563C (zh
Inventor
石健学
蔡明兴
苏鸿文
眭晓林
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN1832159A publication Critical patent/CN1832159A/zh
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Abstract

本发明提供一种半导体元件，其包括：一具有开口的介电层；一铜基第一金属层，填满该介电层的该开口并具有一上表面；以及一第一导电性高分子，覆盖该铜基第一金属层的该上表面。本发明还提供一种半导体元件，其包括：一铜基金属层，埋设于一介电层并具有一上表面；一导电性高分子，覆盖该铜基金属层的该上表面；以及一铝基金属垫，设置于该导电性高分子上。该导电性高分子夹置于两金属层间，可作为粘着层，阻障层或活化晶种层。该导电性高分子可包覆铜连线结构以避免铜扩散至其上层，以及增加铜与其上层的附着力。

Description

半导体元件
技术领域
本发明涉及半导体结构与集成电路元件的制造方法，特别涉及铜连线与金属垫。
背景技术
以图案化半导体为基础的微电子集成电路，仍继续朝高密度的电路元件发展。在缩小元件尺寸上，成功与否取决于组成元件的材料表现。特别在进一步要求较小元件具有较高导电度与较佳机械完整性后，现在的主流材料为铜(Cu)。铜的导电度是铝的两倍，钨的三倍。此外还要求使用于电路间，金属线间或电路的其他元件间的介电材料，其介电常数(k)越低越好。作为集成电路主要介电质其介电常数最好低于二氧化硅(约3.9)，以避免电容耦合(串音)与传播延迟的问题。
铜在制程中非常容易氧化，也容易扩散至其他材料如介电层，因此必需以阻障材料包覆铜连线。一般铜镶嵌制程是将阻障材料包括氮化钛或氮化钽，沉积于铜层与其下层材料间。在沉积铜层后，包覆阻障层如氮化硅，钨，氮化钨，或氮化钛沉积于铜层上。美国专利No.6,716,753描述一种氮化铜层的上表面以形成自我保护层(包括氮化钛)的方法。美国专利No.6,130,157描述一种以氮化钨作为铜连线上包覆层的方法。现有技术中包覆铜的问题，在于铜与阻障材料间附着力太差。因此需要一种可阻障铜扩散至其上层，又能增加铜与其上层的附着力的阻障材料。
以物理气相沉积(以下简称PVD)形成阻障层有悬突，不对称，侧壁覆盖的问题，越来越难连续性地衬垫在双镶嵌结构上。太薄的衬垫或表面上的不连续，均造成铜迁移并降低可靠度。与PVD相比，化学气相沉积(以下简称CVD)或原子层沉积(以下简称ALD)在沉积阻障材料有较佳的阶梯覆盖，但较昂贵且低介电系数材料与铜之间的附着力不佳。因此需要一种可增加低介电系数的介电质与铜的附着力，以及避免铜扩散与被氧化的阻障材料。
铜连线的线焊技术常以铝层覆盖露出的铜垫。铝盖的使用使铜垫可应用常规铝连线技术的线焊工具与制程。然而大部分沉积于铜上的铝将与铜反应形成二铝化铜(CuAl2)，因此需将氮化钽夹设于铜垫与铝盖间，但仍需克服伴随而来的氮化钽与铜之间附着力不佳的问题。美国专利No.6,350,667叙述一种铝粘着层夹设于氮化钽与铜间，以增加该金属垫结构的附着力。本发明除了避免铜连线氧化外，还增加最上层的铜与线焊铝垫间的表面附着力。
发明内容
本发明提供一种半导体元件，其包括：一具有开口的介电层；一铜基第一金属层，填满该介电层的该开口并具有一上表面；以及一第一导电性高分子，覆盖该铜基第一金属层的该上表面。
所述半导体元件还包括一第二金属层设置于该第一导电性高分子上。所述半导体元件还包括一第一扩散阻障层，衬垫该介电层的开口，该扩散阻障层夹设于该铜基第一金属层与该介电层间；该第一扩散阻障层包括钽、氮化钽、钛、氮化钛、前述物质的组合、钴、镍、铂、铷、钨、钯或金。
该第一扩散阻障层也可以是一第二导电性高分子，包括下列电致共轭导电性高分子：聚苯胺、聚吡咯、聚噻吩、聚乙烯基乙烯撑、或聚4-乙烯基吡啶。
其中，该第二导电性高分子连结至该第一导电性高分子。
所述半导体元件还包括一第二扩散阻障层衬垫该介电层的开口，其中该第二扩散阻障层夹设于该第二导电性高分子与该铜基第一金属层之间。其中，该第二扩散阻障层包括钽、氮化钽、钛、氮化钛、前述物质的组合、钴、镍、铂、铷、钨、钯、或金。
所述半导体元件中，该铜基第一金属层的该上表面与该介电层等高。
所述的半导体元件中，该第一导电性高分子与该介电层等高。
本发明实施例是以导电性高分子包覆一金属层，以增加金属层与其上层的附着力。
本发明其他实施例是以导电性高分子包覆一金属层，以作为之后金属电镀制程的活化晶种层。
在本发明一实施例中，在第一金属层与第二金属层间夹设第一导电性高分子。该第一导电性高分子优选有机材料，包括电致共轭导电性高分子如聚苯胺、聚吡咯、聚噻吩、聚乙烯基乙烯撑(polyethylenevinylene)、或聚4-乙烯基吡啶。第一金属层优选铜，而第二金属层优选铜、铜基合金、钴、镍、钴基合金、镍基合金、铝、或铝基合金。夹设于第一导电性高分子与第二金属层间的扩散阻障层，选自钽、氮化钽、钛、氮化钛、钴、镍、铂、铷、钨、钯、或金。
在本发明另一实施例中，具有开口的介电层形成于半导体基板上，而铜基金属层形成于开口中，且第一导电性高分子形成于该金属层表面上。该第一导电性高分子优选有机材料，包括电致共轭导电性高分子如聚苯胺、聚吡咯、聚噻吩、聚乙烯基乙烯撑、或聚4-乙烯基吡啶。在第一导电性高分子上形成一金属层如铜、铜基合金、钴、镍、钴基合金、镍基合金。该介电质的介电常数优选低于约3.9。
另一实施例中，以钽、氮化钽、钛、氮化钛、钴、镍、铂、铷、钨、钯、或金形成的扩散阻障层衬垫介电层开口，并夹设于铜基金属层与介电层间。第二导电性高分子可形成在介电层的开口上，并夹设于介电层与铜基金属层间。该第二导电性高分子与第一导电性高分子相接。根据情况可将扩散阻障层夹设于第二导电性高分子与铜基金属层间。第一导电性高分子的上表面与介电层的上表面相比，可较高或等高。
本发明另一实施例，半导体元件的介电层形成于半导体基板上，铜基金属层被埋设于介电层中且露出表面，导电性高分子形成于该金属层表面上，铝基金属垫形成于该导电性高分子上。该导电性高分子优选有机材料，包括电致共轭导电性高分子如聚苯胺、聚吡咯、聚噻吩、聚乙烯基乙烯撑、或聚4-乙烯基吡啶。所述半导体元件，还包括一保护层，保护层优选形成于介电层上并具有一开口，该开口即为铜基金属层的露出表面。以钽、氮化钽、钛、氮化钛形成的阻障层可衬垫保护层开口，并夹设于铝基金属垫层与导电性高分子间。
附图说明
图1A为本发明一实施例的剖视图，是以导电性高分子包覆的铜镶嵌结构；
图1B为本发明一实施例的剖视图，是铜连线叠层；
图2为本发明一实施例的剖视图，是以导电性高分子以及金属盖层包覆铜镶嵌结构；
图3为本发明一实施例的剖视图，是以连续性导电性高分子埋设于铜镶嵌结构并覆盖铜表面；
图4为本发明一实施例的剖视图，是以连续性导电性高分子埋设于铜镶嵌结构并覆盖铜表面，其上为一金属盖层；
图5为本发明一实施例的剖视图，是以连续性高分子与扩散阻障层埋设于铜镶嵌结构；
图6为本发明一实施例的剖视图，是以连续性高分子与扩散阻障层埋设于铜镶嵌结构，其上为一金属盖层；
图7-12为本发明实施例的剖视图，是不同的铜镶嵌结构均具有形成于凹陷区域的导电性高分子；
图13为本发明实施例的剖视图，是一金属垫层结构中，导电性高分子夹设于铜电路与铝垫间；以及
图14为本发明实施例的剖视图，是一金属垫结构中，导电性高分子与扩散阻障层夹设于铜电路与铝垫间。
具体实施方式
本发明实施例的导电性高分子夹设于两金属层间，可作为粘着层，阻障层及/或活化晶种层。实施例中，导电性高分子可用来包覆铜连线结构，以避免铜扩散至其上层，并增加铜与其上层间的附着力。其上层包括但不限于介电材料、扩散阻障层、铜(Cu)、钴(Co)、镍(Ni)、铂(Pt)、铷(Ru)、钽(Ta)、氮化钽(TaN)、钛(Ti)、氮化钛(TiN)、钨(W)、钯(Pd)、金(Au)、含钴合金、或含镍合金。导电性高分子也可作为活化晶种层，进行含钴合金或含镍合金的自发式无电沉积。实施例中，导电性高分子作为扩散阻障层，夹设于铜镶嵌结构的铜层与层间介电层之间；亦作为粘着层及/或铜电镀制程的晶种层。层间介电层优选低介电常数(低于约3.9)的材料。实施例中，导电性高分子夹设于铝垫与其下的铜连线间，使两者粘着较佳以形成坚固的金属垫。
本发明较佳实施例可应用在许多领域，包括制造集成电路，微电子，光学电子。本发明所提及的“铜”，包括纯元素铜，含无可避免的杂质的铜，以及主成分为铜的合金，其余成分包括钽、铱、锡、锰、铬、钛、锗、锶、铂、镁、铝、或锆。文中所提“镶嵌”指的是图案层埋设于另一层内，且此两层的上表面为共平面。通过重复多次镶嵌制程，可形成含有金属内连线与接触孔(vias)的多重内连线。虽然本发明优选实施例的铜连线图案应用于双镶嵌制程，本发明也可应用于单镶嵌与非镶嵌制程。
接下来本发明实施例将配合附图做解释。在不同的附图中，已尽可能使用相同符号定义一样事物。而较夸张的厚度与形状是为了方便与清楚的描述实施例。该描述将着重于本发明的装置元件。必需了解的是，为特别描述或图示的元件可以本领域技术人员所熟知的各种形式存在。此外，当某层在其他层或基板“上”时，有可能是指“直接”在其他层或基板上，或指某层在其他层或基板上，或指其他层或基板之间夹设其他层。
图1A为本发明一实施例的剖视图，是以导电性高分子包覆的铜镶嵌结构。图1B为本发明一实施例的剖视图，是铜连线叠层。
图示例的一基板10包括一半导体基板，集成电路可形成于该基板上及/或中。该半导体基板组成的材料可包括硅块材、半导体晶片、绝缘体上硅(silicon-on-insulator)基板、或硅锗基板。该集成电路具有许多独立的电路元件，比如晶体管、二极管、电阻、电容、电感、以及其他主动与被动半导体元件。基板10包括一导电区域12，为导电电路的一部分，若必要时其露出的表面可以用平坦化制程如化学机械研磨(以下简称CMP)处理过。该导电区域12的适当材质包括铜、铝、铜合金、或其他导电材料。
如图1A所示，将层间介电层(interlayer dielectric layer)14沉积于基板10上，接着图案化该层间介电层14以形成一双镶嵌开口20，包括上面的沟槽部分18与下面的接触孔(via hole)部分16。本发明实施例虽然以双镶嵌结构举例，也可应用于单镶嵌与其他镶嵌结构。为定义接触区域，下面的接触孔部分16将露出部分导电区域12。双镶嵌技术中，以典型掩膜光刻制程(lithographicprocess with masking technology)与各向异性蚀刻(比如等离子蚀刻与反应性离子蚀刻)可形成上面的沟槽部分18与下面的接触孔部分16。作为何时停止蚀刻依据的底部蚀刻停止层，中间蚀刻停止层，研磨停止层，或抗反射层均可视情况沉积于层间介电层上或该层间介电层中。实施例中，如图1B的蚀刻停止层15，在图1A中为了简洁而省略。蚀刻停止层15组成可为氧化硅、氮化硅、碳化硅、氮氧化硅、或上述物质的组合，其厚度约为10-1000埃，可由多种沉积技术形成包括低压化学气相沉积(以下简称LPCVD)、常压化学气相沉积(以下简称APCVD)、等离子增强化学气相沉积(以下简称PECVD)、PVD、溅镀、以及未来发展的沉积技术。
层间介电层14的厚度约为1000-20000埃，可由多种技术形成，包括旋转涂布、CVD、以及未来发展的沉积技术。层间介电层14优选介电常数低于约3.9的介电材料，比如3.5或更低。各种低介电系数材料可应用于本发明实施例，比如旋转涂布的无机介电质、旋转涂布的有机介电质、多孔质介电材料、有机高分子、有机硅玻璃、氟化硅玻璃(以下简称FSG)、类金刚石碳、氢化倍半硅氧烷(Hydrogen silsesquioxane，以下简称HSQ)系列材料、甲基倍半硅氧烷(methyl silsesquioxane，以下简称MSQ)系列材料、或多孔质有机系列材料。
将一扩散阻障层22顺应性地沉积于双镶嵌开口20的底部与侧壁之后再进行铜填满制程，即可兼顾扩散阻障与导电性。以电镀法将金属层24填入双镶嵌开口20。以CMP或其他合适的回蚀制程(etch back process)移除超出层间介电层14上表面的金属层24与扩散阻障层22，但优选以CMP制程平坦化层间介电层14。以PVD、CVD、ALD、或电镀形成的扩散阻障层22包括耐火材料、氮化钛、氮化钽、钽、钛、氮硅化钛、氮硅化钽、钨、氮化钨(WN)、铬、铌、钴、镍、铂、铷、钯、金、磷化钴(CoP)、磷化钴钨(CoWP)、磷化镍(NiP)、磷化镍钨(NiWP)、上述物质的混合物、或其他可抑制铜扩散至层间介电层14的材料。该扩散阻障层22的厚度约50-500埃。
金属层24是低电阻导体材料包括铜，铜基合金。举例来说，铜填入制程包括厚度约50-2500埃的金属晶种层沉积，以及厚度约5000-15000埃的铜电化学电镀。PVD、CVD、或ALD沉积的金属晶种层包括括铜、镍、钼、铂。当氮化钽、氮化钛、氮硅化钽、氮硅化钛、钽、钛、或上述物质的组合物形成扩散阻障层22后，需要沉积金属晶种层以进行后续铜电镀制程。若以钴、镍、铂、铷、钯、金、钨、磷化钴、磷化钨钴、磷化镍、或磷化钨镍形成扩散阻障层，该阻障层可直接作为铜电镀制程的晶种层，而不需另外沉积金属晶种层。
本发明的优点在于将导电性高分子26选择性沉积于金属层24以及扩散阻障层22两者的露出表面以形成包覆层，可避免金属层24扩散至其上层，以及增加金属层与其上层的附着力。导电性高分子可以化学接枝法、电接枝法、无电沉积法、光活化法、或任何其他合适的表面接枝技术形成，优选有机材料，包括含碳、氟、氮、或氢的电致共轭导电性高分子如聚苯胺、聚吡咯、聚噻吩、聚乙烯基乙烯撑、或聚4-乙烯基吡啶。优选的导电性高分子组成为聚4-乙烯基吡啶，且厚度约为10-50埃。
在完成一层连线电路后(如图1A所示的双镶嵌结构)，重复上述步骤可形成多层连线电路(如图1B所示的叠层连线)。与现有技艺相比，本发明的连线结构与方法有较多优点。首先，薄且顺应性的导电性高分子26覆盖该铜连线更可阻障铜离子扩散。其次，该导电性高分子26可作为粘着层，增加铜与其上层材料如介电蚀刻停止层15的附着力。之后若需沉积金属于导电性高分子26上，该导电性高分子也可作为金属电镀制程的活化晶种层，并增加铜与其上层金属的附着力。
图2为本发明另一实施例的剖视图，是以导电性高分子与金属盖层包覆的铜双镶嵌结构，并省略与图1A类似部分的描述。
形成导电性高分子26后，将一金属盖层(capping layer)28选择性沉积在导电性高分子26上，可减少金属层24的原子传递并增加金属层与其上层的附着力。金属层24上的金属盖层28与导电性高分子26的组合可大大增加元件可靠度。沉积金属盖层28的技术如电镀制程，材料包括：钴、镍、铂、铷、钽、钨、钯、金、含钴合金(如磷化钴(CoP)、磷化钨钴(CoWP)、硼化钴(CoB)、硼化钨钴(CoWB))、或含镍合金(如磷化镍(NiP)、磷化钨镍(NiWP)、硼化镍(NiB))。优选的金属盖层28厚度为5-20纳米。该导电性高分子26可作为自发型钴合金(或镍合金)沉积的活化晶种层。
图3为本发明又一实施例的剖视图，是将连续性的导电性高分子埋设于铜镶嵌结构并覆盖铜表面，并省略与图1类似部分的描述。
与图1中以含金属材料形成的扩散阻障层22相比较，另一导电性高分子30选择性地形成于沟槽18与接触孔16的层间介电层14上，以作为扩散阻障层以阻止金属层24扩散至层间介电层14。导电性高分子30可以通过无电制程、光接枝法、电化学聚合法、或任何其他合适的表面接枝技术所形成，优选含碳、氟、氮、或氢的有机材料，包括电致共轭导电性高分子如聚苯胺(polyaniline)、聚吡咯(polypyrrole)、聚噻吩(polythiophene)、聚乙烯基乙烯撑(polyethylenevinylene)、或聚4-乙烯基吡啶(poly-4-vinyl pyridine)。例如电接枝法可应用于电致共轭导电单体如苯胺(aniline)、吡咯(pyrrole)、噻吩(thiophene)、乙烯基乙烯撑(ethylenevinylene)、或4-乙烯基吡啶(4-vinylpyridine)。光引发接枝聚合法可应用于苯甲酮(benzophenone)。聚合反应只发生于层间介电层14的表面，而不发生于导电区域12上，因为前者可提供聚合反应所需的氢。所以导电性高分子30只形成于层间介电14的表面而不形成于导电区域12上。优选的导电性高分子组成为聚4-乙烯基吡啶，且厚度约为10-50埃。
与现有技艺相比较，本发明的连线结构与方法有许多优点。首先，该导电性高分子30较能阻障铜扩散。其次，与物理气相沉积相比，该薄且顺应性的导电性高分子30在双镶嵌结构中，可避免悬突、不对称、侧壁覆盖等问题，并具有较佳的连续衬垫覆盖与可靠度。第三，该导电性高分子30作为一粘着层，可增进层间介电层14与金属层24的附着力。另外，接续的表面接枝制程可使导电性高分子26与导电性高分子30结合以形成一连续的导电性高分子架构。
此时如图2在导电性高分子26上选择性沉积一金属盖层28，该导电性高分子26可减少金属层24的原子传递并增加金属层24与其上层的附着力。图4为本发明再一实施例的剖视图，是以连续性导电性高分子埋设于铜镶嵌结构并覆盖铜表面，其上为一金属盖层，与图2类似部分的描述将予以省略。
导电性高分子30的材料可为一具有乙烯基的末端官能基化低聚物。若该低聚物链具有足够的导电度，将可作为铜电镀制程的晶种层，除此之外也可活化一扩散阻障层如铜扩散阻障层的无电镀沉积。如图5所示，扩散阻障层22沉积于双镶嵌结构的开口20底部与侧壁的导电性高分子30与导电区域12上，而与图1与图3类似部分的描述将予以省略。在层间介电层14与金属层24间，夹置导电性高分子30与阻障层22可大大提升元件可靠度。
在图6的实施例中，是在铜镶嵌结构的层间介电层14与金属层24间，夹设导电性高分子30与扩散阻障层22的组合；并于金属层24上覆盖导电性高分子26与金属盖层28的组合。
图7-12为本发明实施例的剖视图，是以导电性高分子包覆铜镶嵌结构的凹陷区域，并省略与图1A-图6类似部分的解释。将金属层24的上表面磨蚀至比层间介电层14的上表面还低后，将导电性高分子26填入凹陷区域25，且导电性高分子26的上表面与层间介电层14的上表面等高。举例来说，在CMP移除超过层间介电层14上表面的部分金属层24后，以H2或NH3等离子清除铜层上表面的氧化铜，形成深度约50-1000埃的凹陷区域25。接续的化学接枝法以导电性高分子26填满凹陷区域25，以形成金属层24上的包覆阻障层。特别注意图11与图12，在沟槽18上缘的导电性高分子26与导电性高分子30，被扩散阻障层隔开且形成不连续的导电性高分子架构。
图13为本发明金属垫层结构的实施例，一导电性高分子夹设于铜电路与铝垫间。例如制造连线的基板40，为包括制造半导体集成电路的半导体基板，集成电路可形成于其中及/或其上。集成电路可具有许多独立电路元件，比如晶体管，二极管，电容，电感，以及其他主动与被动元件。基板40包括层间介电层42，以及埋设于层间介电层42的一第一金属电路44。以平坦化制程如CMP处理露出的第一金属电路44。适合作为第一金属电路44的材料包括铜、铝、铜合金、或其他可能的导电材料。层间介电层的材料包括氧化硅、氮化硅、氮氧化硅、PSG、BPSG、含氟氧化硅、或多种介电常数低于约3.9的低介电薄膜。沉积并图案化保护层46以形成开口47，该开口定义第一金属电路44的接触区域。该保护层可保护半导体晶片免受外在环境的影响。该保护层可为单层或多层结构，组成包括TEOS(四乙基原硅酸盐)氧化物、氮化硅(SiNx)、或等离子加强型氧化硅。
在金属垫制程前，将导电性高分子48选择性沉积于露出的第一金属电路44上，可增加第一金属电路44与其上层的附着力。导电性高分子48可以任一合适的表面接枝技术形成，优选有机材料，包括电致共轭导电性高分子如聚苯胺、聚吡咯、聚噻吩、聚乙烯基乙烯撑、或聚4-乙烯基吡啶。化学接枝法可应用于电致共轭导电性单体如苯胺、吡咯、噻吩、乙烯基乙烯撑、或4-乙烯基吡啶。优选的导电性高分子48为厚约10-50埃的聚4-乙烯基吡啶。
将一金属层沉积于导电性高分子48与保护层46上，且至少填满开口47。以掩膜光刻技术与蚀刻制程可将该金属层图案化为金属垫50。该金属垫50的组成可为铝、铜化铝、或铜基合金。后续制程如视情况进行的图案化另一保护层，接着进行封装/组装制程。导电性高分子48提供对坚固金属垫的良好附着力，避免剥落与界面破损的问题，在线焊拉引测试上具有高可靠度。
图14为本发明实施例的剖视图，是将导电性高分子与扩散阻障层，夹设于铜电路与铝垫间。导电性高分子48形成后，进一步将一扩散阻障层52衬垫保护层46的开口47。扩散阻障层52的组成包括钽、氮化钽、钛、或氮化钛。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。
附图中符号的简单说明如下：
10：基板
12：导电区域
14，14”：层间介电层
15：蚀刻停止层
16：接触孔
18：沟槽
20：开口
22，22”：扩散阻障层
24：金属层
25：凹陷区域
26，30：导电性高分子
28：金属盖层
40：基板
42：介电层
44：第一金属电路
46：保护层
47：开口
48：导电性高分子
50：金属垫
52：扩散阻障层

Claims (14)

1.一种半导体元件，其特征在于，包括：
一具有开口的介电层；
一铜基第一金属层，填满该介电层的该开口并具有一上表面；以及
一第一导电性高分子，覆盖该铜基第一金属层的该上表面。
2.根据权利要求1所述的半导体元件，其特征在于，该第一导电性高分子是有机材料，包括下列电致共轭导电性高分子：聚苯胺、聚吡咯、聚噻吩、聚乙烯基乙烯撑、或聚4-乙烯基吡啶。
3.根据权利要求1所述的半导体元件，其特征在于，还包括一第二金属层设置于该第一导电性高分子上。
4.根据权利要求1所述的半导体元件，其特征在于，还包括一第一扩散阻障层，衬垫该介电层的开口，该扩散阻障层夹设于该铜基第一金属层与该介电层间；该第一扩散阻障层包括钽、氮化钽、钛、氮化钛、前述物质的组合、钴、镍、铂、铷、钨、钯或金。
5.根据权利要求4所述的半导体元件，其特征在于，该第一扩散阻障层还包括一第二导电性高分子，该第二导电性高分子包括下列电致共轭导电性高分子：聚苯胺、聚吡咯、聚噻吩、聚乙烯基乙烯撑、或聚4-乙烯基吡啶。
6.根据权利要求5所述的半导体元件，其特征在于，该第二导电性高分子连结至该第一导电性高分子。
7.根据权利要求6所述的半导体元件，其特征在于，还包括一第二扩散阻障层衬垫该介电层的开口，其中该第二扩散阻障层夹设于该第二导电性高分子与该铜基第一金属层之间。
8.根据权利要求7所述的半导体元件，其特征在于，该第二扩散阻障层包括钽、氮化钽、钛、氮化钛、前述物质的组合、钴、镍、铂、铷、钨、钯、或金。
9.根据权利要求1所述的半导体元件，其特征在于，该铜基第一金属层的该上表面与该介电层等高。
10.根据权利要求1所述的半导体元件，其特征在于，该第一导电性高分子与该介电层等高。
11.一种半导体元件，其特征在于，包括：
一铜基金属层，埋设于一介电层并具有一上表面；
一导电性高分子，覆盖该铜基金属层的该上表面；以及
一铝基金属垫，设置于该导电性高分子上。
12.根据权利要求11所述的半导体元件，其特征在于，该导电性高分子为有机材料，包括下列电致共轭导电性高分子：聚苯胺、聚吡咯、聚噻吩、聚乙烯基乙烯撑、或聚4-乙烯基吡啶。
13.根据权利要求11所述的半导体元件，其特征在于，还包括一保护层，其形成于该介电层上并具有一开口露出该铜基金属层的该上表面。
14.根据权利要求13所述的半导体元件，其特征在于，还包括一扩散阻障层衬垫该保护层的开口，且夹设于该铝基金属垫与该导电性高分子间。
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