CN1819179A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN1819179A
CN1819179A CN200610007039.1A CN200610007039A CN1819179A CN 1819179 A CN1819179 A CN 1819179A CN 200610007039 A CN200610007039 A CN 200610007039A CN 1819179 A CN1819179 A CN 1819179A
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insulating barrier
semiconductor device
metal cap
film
layer
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上野和良
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NEC Electronics Corp
NEC Corp
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NEC Corp
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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Abstract

氮化的金属帽膜(35)位于包括CoWP的金属帽(34)的上部。金属帽(34)和氮化的金属帽膜(35)的层厚可以是例如1nm到100nmm。氮化的金属帽层(35)的层厚和金属帽(34)的层厚的比率可以是例如0.1到1。此外，通过氮化SiOC层(14a)的表面获得的SiOCN层(16)形成于SiOC层(14a)上。SiOCN层(16)是包括氮在表面上被隔离的区域的层，并且厚度可以是例如1nm到100nm。

Description

半导体器件及其制造方法
本申请基于日本专利申请No.2005-035162，在此参考引进其内容。
技术领域
本发明涉及一种半导体器件的结构和制造该半导体器件的方法，并且特别涉及表面上具有金属帽膜的铜互连线。
背景技术
最近，在需要更高速的半导体器件的情况中，铜被更广泛地用作互连材料。与迄今为止还在使用的铝互连线相比，铜具有更低的电阻和更低的电容，并且在抗电迁移和应力迁移上更优越。另一方面，甚至在含有氧的大气中、在150℃的低温下，铜也具有易被氧化的特性。因此，用氧化阻挡膜来涂覆铜表面的技术通常被用在形成铜互连线的工艺中。可以通过不使用氧的化学气相生长来淀积氮化硅膜、碳化硅膜等，它们都被用作阻挡膜来防止氧化和Cu扩散。但是，这些氧化阻挡膜具有高的介电常数(氮化硅膜的介电常数是8，碳化硅膜的介电常数是5)，从而引起互连之间的寄生电容增加。
作为上面问题的解决方案，已知如下技术：通过非电镀，在铜互连线的表面上选择性地提供金属帽膜。例如，有如下提议：根据该提议，通过用CoWP涂覆，CoWP膜被选择性地形成在易于氧化的铜互连线的表面上，此后，淀积在氧化气氛中生长的诸如氧化硅的绝缘层。
但是，上面的技术却有下面的问题。也就是说，为了去除残留在互连之间的绝缘层的表面上的铜和钴原子，当用氢氟酸等执行清洗时，CoWP膜被刻蚀和损坏，并且，在极端的情况中，CoWP膜会消失。原因是CoWP被诸如氢氟酸的清洗液侵蚀。此外，CoWP和铜相比几乎不被氧化，并且，当CoWP被暴露在形成氧化硅的化学气相生长气氛中时，CoWP被氧化而形成氧化钴，所以在一些情况下会增加通路的连接电阻。
因此，如在未决公开专利申请No.2002-43315中所公开的，提出了一种技术：用抗氧化和抗氢氟酸的硅化钴层涂覆CoWP膜。在该技术中，如图6所示，下层铜互连线2、上层铜互连线3和铜通路4形成在各互连之间的间层1中，金属帽膜5和金属帽膜中的硅化物层6形成在下层铜互连线2和上层铜互连线3的上表面上。此处，在形成金属帽膜5之后，通过将金属帽膜5暴露于硅烷气体中来形成金属帽膜中的硅化物层6。
但是，为了形成上面所描述的硅化钴层，当各互连之间的绝缘层(SiO2等)的表面暴露于硅烷气体时，存在如下可能性：该表面通过吸收硅烷分解的Si原子而被电激活，导致漏电流增加。此外，由于没有刻蚀停止物，当执行通路刻蚀时，用于形成铜通路4的通路孔甚至会到达未对准部分中的下层铜互连线2的侧面。因此，会引起通路金属的劣质填充。
发明内容
根据本发明，提供一种半导体器件，包括：半导体衬底；具有凹(沟槽)部且位于半导体衬底上的绝缘层；包括铜且嵌入凹(沟槽)部中的金属层；和覆盖金属层的上部的金属帽膜，其中金属帽膜的至少上部被氮化。此处，“氮化”是指“含有氮”。
此外，本发明提供一种制造半导体器件的方法，包括：在半导体衬底上形成绝缘层；选择性地去除绝缘层和形成凹(沟槽)部；在凹(沟槽)部中形成包括铜的金属层；在金属层的表面上形成金属帽膜；以及氮化金属帽膜的表面和绝缘层的表面。
因为本发明具有金属帽膜的上部被氮化的结构，所以根据本发明，改善了包括铜的金属层和位于其上的金属层之间的接触(通路)部分的可靠性。
附图说明
本发明的上述的和其他目的、优点和特征，从下面结合附图的描述中将会更清楚，其中：
图1A是根据实施例的互连结构的截面图；
图1B是根据实施例的互连结构的截面图；
图2A是示出了制造图1A和1B中所示的互连结构的方法中的步骤的工艺图；
图2B作为图2A的继续，示出了制造图1A和1B中所示的互连结构的方法中的步骤的工艺图；
图2C作为图2B的继续，示出了制造图1A和1B中所示的互连结构的方法中的步骤的工艺图；
图2D作为图2C的继续，示出了制造图1A和1B中所示的互连结构的方法中的步骤的工艺图；
图2E作为图2D的继续，示出了制造图1A和1B中所示的互连结构的方法中的步骤的工艺图；
图2F作为图2E的继续，示出了制造图1A和1B中所示的互连结构的方法中的步骤的工艺图；
图3A作为图2F的继续，示出了制造图1A和1B中所示的互连结构的方法中的步骤的工艺图；
图3B作为图3A的继续，示出了制造图1A和1B中所示的互连结构的方法中的步骤的工艺图；
图3C作为图3B的继续，示出了制造图1A和1B中所示的互连结构的方法中的步骤的工艺图；
图3D作为图3C的继续，示出了制造图1A和1B中所示的互连结构的方法中的步骤的工艺图；
图4是示出了制造图1A和1B中所示的互连结构的方法中的步骤的工艺图；
图5是根据实施例的互连结构的截面图；
图6是常规互连结构的截面图；以及
图7是根据实施例的互连结构的截面图。
具体实施方式
现在，将参考说明性的实施例在此描述本发明。本领域技术人员将认识到，使用本发明的讲解，能够实现很多可选择的实施例，并且本发明不限于为了解释的目的而说明的实施例。
图1A是示出了根据本实施例的互连结构的截面图。
图1A所示的半导体器件包括：
半导体衬底；
具有凹部且位于所述半导体衬底上的绝缘层；
包括铜且嵌入所述凹(沟槽)部中的金属层；和
覆盖所述金属膜的上部的金属帽，其中
所述金属帽的至少上部被氮化。
绝缘层具有多层结构，该多层结构包括第一绝缘层和位于所述第一绝缘层的上部的第二绝缘膜。第二绝缘层的上表面和所述金属的上表面处于相同高度。第一绝缘层是多孔膜，而所述第二绝缘层是致密膜。
在下文中，参考图1A和图1B来说明根据本实施例的互连结构。
氮化的金属帽膜35位于含有CoWP的金属帽34的上部。金属帽34和氮化的金属帽膜35的层厚可以是例如1nm到100nm。氮化的金属帽层35和金属帽34的层厚的比率可以是例如0.1到1。此外，通过氮化SiOC层14a的表面获得的SiOCN层16形成于SiOC层14a上。SiOCN层16是含氮的层，并且厚度可以是例如1nm到100nm。
SiCN层12、SiOC层14a、通过氮化SiOC层14a的表面形成的SiOCN层16、氧化硅层18、SiCN层20，和SiOC层14b以这种顺序堆叠在硅衬底(未示出)的绝缘层106上。第一铜互连线22a形成在SiOC层14a中，而第二铜互连线22b形成在SiOC层14b中。此处，“SiOC层”是含有Si、O、C和H的层，并且使用有机硅烷气体等根据等离子体CVD方法来形成。在这个实施例中使用具有多孔结构的SiOC膜。
第一铜互连线22a包括钽基阻挡金属膜24a和铜膜26a。连接栓塞28形成在氧化硅层18中，其连接到第一铜互连线22a的上表面。连接(通路)栓塞28包括钽基阻挡金属层30和铜层32。第二铜互连线22b形成在SiOC层14b中，其连接到连接孔的上表面。第二铜互连线22b包括钽基阻挡金属层24b和铜层26b。
第一铜互连线22a、连接(通路)栓塞28和第二铜互连线22b具有近似相同的宽度，并且形成具有无边界接触的互连线。
金属帽34形成在第一铜互连线22a的上表面上。金属帽34的组成材料包括：含有金属的钴，诸如Co、CoWP、CoWB、CoB和CoP；含有金属的镍，诸如Ni、NiMoP、NiMoB、NiWP、NiWB、NiReP、NiReB、NiB和NiP；含有金属的银，诸如Ag和AgCu；等等。
此处，以使金属帽34的上表面高于SiOC层14a的上表面的方式来设置金属帽34。
氮化的金属帽层35形成在金属帽34的上部。当金属帽34包括例如CoWP时，氮化的金属帽膜35变成CoWPN。
金属帽34和氮化的金属帽膜35的层厚可以是例如1nm到100nm，优选地，10nm到50nm。因此，抗应力迁移性确实能够提高。氮化的金属帽膜35和金属帽34的层厚的比率可以被假定为例如0.1到1。因此，实现了稳定的通路接触。在本实施例中假设金属帽34的层厚是5nm，氮化的金属帽膜35的层厚是5nm。
帽金属34的氮化表面还有另一个作用，即改善诸如电阻的铜互连的热稳定性。CoWP帽金属的表面氮化能够改善其热稳定性，抑制由于Co扩散到Cu互连中造成的电阻增加。
SiOC层14a的表面被氮化，以在SiOC层14a上形成SiOCN层16。SiOCN层16和金属帽34的表面被同时氮化。SiOCN层16是由含有氮的区域构成的层，并且可以是例如1nm到100nm，优选地，2nm到50nm。尽管能够在本实施例中形成含氮层，但由于在用于硅烷处理的常规技术中，硅淀积在SiOC层14a的表面，所以难以形成具有均匀厚度的含氮层(SiOCN层16)。根据本实施例，因为SiOC层14a的干净的表面被氮化，所以能够稳定地形成这样的层。此处，尽管这个实施例具有如下结构：以金属帽34的上表面和侧面被覆盖的方式如图1A所示地形成氮化的金属帽膜35；但其也可以应用如下结构：氮化的金属帽膜35堆叠在金属帽34的上表面上，如图1B所示。
在下文中，参考图2A到图4来说明制造根据本实施例的互连结构的方法。
图2A示出了在SiCN层12和SiOC层14a中形成互连沟槽的状态。根据如下处理来形成互连沟槽，其中：形成SiCN层12和SiOC层14a，在14a上设置具有预定图形的抗蚀膜(未示出)，并且分步刻蚀SiCN层12和SiOC层14a。
随后，通过溅射法，在衬底的整个表面上形成钽基阻挡金属膜24a，在钽基阻挡金属膜24a中堆叠了Ta和TaN(图2B)。随后，在钽基阻挡金属膜24a上形成铜膜26a并进行退火，如图2C所示。
然后，通过化学机械抛光(CMP)，去除不希望地形成在互连沟槽的外部的铜膜26a和钽基阻挡金属膜24a，并且以铜膜26a等仅保留在互连沟槽内部这样的方式来形成第一铜互连线22a(图2D)。
随后，在第一铜互连线22a的表面上形成金属帽34，如图2E所示。能够通过非电镀等形成金属帽34。用于非电镀的催化剂可以包括例如钯。此外，能够通过不使用钯催化剂的非电镀将金属帽34淀积在铜表面上，这被称为自引发工艺。如上所述，金属帽34的组成材料是例如含有金属的钴，诸如CoWP；含有金属的镍，诸如NiWP；和含有金属的银，诸如AgCu。
如上所述制造的结构的表面被氮化。因此，如图2F所示形成氮化的金属帽膜35和SiOCN层16。对表面进行氮化的方法包括：等离子体工艺，诸如NH3等离子体工艺、N2-H2等离子体工艺、和N2等离子体工艺；NH3热处理(热氮化)；N2离子注入，等等。这个实施例采用了氨气等离子体工艺。
其后，在氮化的金属帽膜35和SiOCN层16上形成氧化硅层18，如图3A所示。
随后，氧化硅层18被选择性地刻蚀，并且形成连接孔40，其达到氮化的金属帽膜35的上表面(图3B)。
其后，以嵌入连接(通路)孔40内部的方式依次形成钽基阻挡金属层30和铜层32(图3C)。以和第一铜互连线22a中的铜膜26a相同的方式，通过镀的方法形成铜层32。其后，铜层32通过CMP被平坦化，以形成连接(通路)栓塞28(图3D)。
随后，根据类似于上面所描述的工艺，通过在连接(通路)栓塞28上形成铜互连线22b，来形成图1A和1B中所示的铜互连线的结构。以和铜互连线22a相同的方式，金属帽和氮化的金属帽膜甚至能够形成在铜互连线22b的上部。
随后，通过重复上面所描述的工艺，能够形成具有三层或者多层的多层结构互连的半导体器件。
根据本实施例的半导体器件具有下面的优点。首先，在根据本实施例的半导体器件中，改善了抗氧化性和铜互连线与其上的部分之间的铜扩散的阻挡特性，这是因为该半导体器件具有金属帽34的上部被氮化的金属帽膜35覆盖的结构。此处，金属帽34具有如下结构，其中：为了降低互连之间的漏电流，去除了各互连之间的绝缘层的表面，并且金属帽的上表面位于比SiOC层14a的上表面更高的位置。根据上述结构，能够实现与通路栓塞的稳定接触。因此，获得能够改善接触(通路)电阻的稳定性等优点。
其次，很难产生由于在通路刻蚀时未对准造成的间隙，并且不易产生铜不佳地填充进该间隙，这是因为根据本实施例的半导体器件具有具有起到刻蚀停止物作用的SiOCN层16。因此，能够防止由间隙引起的不完全制造和可靠性的降低。此处，由于SiOCN层16是通过SiOC层14a的表面的氮化而获得的层，所以与提供氮化的层作为扩散阻挡层的常规情况相比，更能控制互连之间的绝缘层的介电常数的增加，以助于降低互连之间的串扰。
第三，由于SiOC层14a的表面被氮化，从而形成SiOCN层16，所以互连之间的绝缘层的表面被氮去激活，并且能够减小漏电流。与执行金属帽的硅烷处理的上述常规技术不同的是，互连之间的绝缘层的表面不需要暴露于硅烷气体，并且不生成由Si原子引起的漏电流，该Si原子是通过硅烷分解产生的并附着到互连之间的绝缘层的表面。此处，在这个实施例中SiOC层14a由多孔材料组成。因此，在氮化等离子体工艺期间，等离子体渗透到该层中以促进氮化，并且能够以稳定的方式形成具有期望厚度的SiOCN层16。
上面已经参照附图描述了根据本发明的实施例。但是，上面的实施例被认为是作为说明性的而不是限制性的，并且除了上面的实施例之外，本发明还能够采用各种构造。
例如，尽管上述实施例具有金属帽34的上部被氮化金属帽膜35覆盖的结构，但是可以通过氮化处理来氮化整个金属帽34，以形成氮化层。此外，尽管上述实施例具有金属帽的上表面位于比SiOC层14a的上表面更高的位置的结构，但是金属帽的上表面可以位于比SiOC层14a的上表面更低的位置。此外，尽管上面的实施例示出了如下例子：金属帽34被选择性地仅形成于第一铜互连线22a的表面上；但是也可以采用如下例子：形成金属帽34，使得帽34甚至延伸到除了第一铜互连线22a的表面之外的部分，并且覆盖SiOC层14a的一部分表面。
此外，尽管这个实施例具有由多孔SiOC层14a构成互连之间的绝缘层(该层形成在铜互连线22a的下表面的水平和上表面的水平之间的区域中)的结构，但是，也可以采用如图4所示的两层结构。
互连之间的绝缘层能够由另一绝缘膜形成。绝缘层的上部能够优选地由防水的(疏水的)绝缘材料构成。因此，可以消除电流泄漏。防水的(疏水的)绝缘材料是例如SiOC、含氟聚合物、聚芳醚(PAE)、多孔SiOC、或多孔PAE。
如图4所示，铜互连线22a中的互连之间的绝缘层有这样的结构，其中堆叠了多孔SiOC层14a和位于其上的具有致密(非多孔)结构的SiOC层50a。根据上面的结构，与全部都是致密SiOC结构相比，能够实现互连之间的绝缘层的介电常数的减小；并且同时，与全部都是多孔SiOC结构相比，能够增加互连之间的绝缘层的表面的机械强度，从而改善抗CMP性等。
此外，尽管这个实施例具有由多孔SiOC层14a构成互连之间的绝缘层(该层形成在铜互连线22a的下表面的水平和上表面的水平之间的区域中)的结构，但是可以采用如图4中所示的两层结构。
尽管这个实施例具有氧化硅层18形成于氮化的金属帽膜35和SiOCN层16之上的结构，但是SiC膜、SiCN膜或SiOC膜能够形成在氮化的金属帽膜35和SiOCN层16之上。
尽管在本实施例中已经示出了铜被用作互连材料的例子，但是也可以使用其他金属材料。例如，可以使用含有不同的金属诸如银和铝的铜合金。
此外，尽管上面的实施例使用了CVD-SiOC膜，但是在互连之间的绝缘层中，也可以使用甲基倍半硅氧烷(MSQ)等的涂覆膜、或芳香烃(aromatic hydrocarbon)化合物等的有机膜。
此外，尽管上面的实施例描述了由单大马士革工艺形成的互连结构作为例子，但是本发明能够被应用到由双大马士革工艺形成的互连结构。
此外，金属帽34和氮化的金属帽35都能够被嵌入到沟槽中，如图7所示。
本发明能够被应用于铜被嵌入到凹部中的互连结构。凹部可以是沟槽或者孔。尽管本实施例示出了铜被嵌入到沟槽中的例子，但是铜也能够被嵌入到孔中。
<例1>
图5示出了根据本例子的半导体器件的结构的视图。在互连之间的间层1内形成下层铜互连线2、上层铜互连线3和铜通路4。在下层铜互连线2的上表面和上层铜互连线3的上表面上形成金属帽膜5和在金属帽膜中的氮化层7。在互连之间的间层1中，在各层之间的边界处形成互连之间的间层中的氮化层8。
在这个例子中，CoWP被用作金属帽膜。金属帽膜的层厚被设定为100nm，并且互连之间的间层中的氮化层8的层厚被设定为50nm。NH3等离子体工艺被用作在金属帽膜中形成氮化层7和在互连之间的间层中形成氮化层8的方法。
根据这个例子，能够通过在金属帽膜5上形成金属帽膜5中的氮化层7来改善金属帽膜5的抗氧化和铜扩散的阻挡特性。此外，不用担心SiOC膜的表面通过对硅烷分解的Si原子的吸收被电激活，导致漏电流增加，这是因为当氮化层7形成时，在金属帽膜中的氮化层7不需要暴露于硅烷气体。
此外，因为在互连之间的间层中形成了氮化层8，并且互连之间的绝缘层的表面被氮去激活(钝化)，所以能够减小漏电流。
此外，很难产生由于在通路刻蚀时未对准造成的间隙，也不易产生铜不佳地填充进该间隙，这是因为在互连之间的间层中的氮化层8本身有作为刻蚀停止物的功能。因此，能够防止由间隙引起的不完全制造和可靠性的降低。此外，在金属帽的表面不被氮化的常规技术中，在铜通路4中的通路孔甚至会到达通路刻蚀时未对准部分中的下层铜互连线2的侧面，从而引起不佳的填充(图6)。另一方面，在根据这个例子的互连结构中，氮化层8具有作为刻蚀停止物的功能。因此，铜通路4中的通路孔不能达到下层铜互连线2的侧面(图5)，并且能够改善接触(通路)的可靠性。
显然，本发明不限于上面的实施例，在不偏离本发明的范围和精神的情况下，可以修改和变化。

Claims (16)

1.一种半导体器件，包括：
半导体衬底；
具有凹部并位于所述半导体衬底上的绝缘层；
包括铜且嵌入所述凹部中的金属层；和
覆盖所述金属膜的上部的金属帽，其中
所述金属帽的至少上部被氮化。
2.根据权利要求1的半导体器件，
其中所述凹部是沟槽部。
3.根据权利要求1的半导体器件，
其中所述凹部是孔部。
4.根据权利要求1的半导体器件，
其中所述绝缘层的至少上部被氮化。
5.根据权利要求1的半导体器件，
其中所述金属帽是以所述金属帽的上表面高于所述绝缘层的上表面的方式来提供的。
6.根据权利要求1的半导体器件，
其中所述绝缘层的至少上部由疏水的绝缘材料构成。
7.根据权利要求1的半导体器件，
其中所述绝缘层是SiOC膜，并且SiOCN层位于所述绝缘层的表面上。
8.根据权利要求7的半导体器件，
其中SiOC膜由多孔材料构成。
9.根据权利要求1的半导体器件，
其中所述绝缘层包括多孔材料。
10.根据权利要求1的半导体器件，
其中所述绝缘层具有多层结构，该多层结构包括第一绝缘层和位于所述第一绝缘层的上部上的第二绝缘膜，并且
第二绝缘层的上表面与所述金属的上表面处于相同的高度，并且
所述第一绝缘层是多孔膜，而所述第二绝缘层是致密膜。
11.根据权利要求1的半导体器件，
其中所述金属膜形成金属互连线，并且
电连接所述金属膜和位于其上的另一金属膜的导电栓塞位于所述金属膜上。
12.根据权利要求9的半导体器件，其中所述导电栓塞和所述金属膜具有近似相同的宽度。
13.一种制造半导体器件的方法，包括：
在半导体衬底上形成绝缘层；
选择性地去除所述绝缘层并形成凹部；
在所述凹部中形成包括铜的金属膜；
在所述金属膜的表面上形成金属帽；以及
氮化所述金属帽的表面和所述绝缘层的表面。
14.根据权利要求13的制造半导体器件的方法，
其中所述凹部是沟槽部。
15.根据权利要求13的制造半导体器件的方法，
其中所述凹部是孔部。
16.根据权利要求13的制造半导体器件的方法，
其中在所述氮化步骤中，所述金属帽和所述绝缘层被暴露于含有等离子体的氮，以对所述金属帽的表面和所述绝缘层的表面进行氮化。
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