WO2017105448A1

WO2017105448A1 - Templated metal apparatus for efficient electric conduction

Info

Publication number: WO2017105448A1
Application number: PCT/US2015/066200
Authority: WO
Inventors: Sasikanth Manipatruni; Kanwal Jit Singh; Jessica M. TORRES; Christopher J. WIEGAND; Ian A. Young
Original assignee: Intel Corporation
Priority date: 2015-12-16
Filing date: 2015-12-16
Publication date: 2017-06-22
Also published as: TW201737264A

Abstract

Described is an apparatus which comprises: a metal layer with ordered crystalline structure; and a crystallinity templating layer coupled to the metal layer. Described is another apparatus which comprises: a first metal layer; a first crystallinity templating layer coupled to the first metal layer; a second metal layer coupled to the first crystallinity templating layer such that the first crystallinity templating layer is sandwiched between the first metal layer and the second metal layer; and a second crystallinity templating layer coupled to the second metal layer.

Description

TEMPLATED METAL APPARATUS FOR EFFICIENT ELECTRIC CONDUCTION

BACKGROUND

[0001] Scaling the width of backend metal wires is a critical part of the Moore's law scaling. Moore's law scaling is the observation that the number of transistors in a dense integrated circuit (IC) doubles approximately every two years. As such, for the same die size or smaller die size, metal wires have to scale down in size to support more transistors. However, interconnect scaling increases the resistivity of the metals as the width/thickness of the metal approaches the electron mean free path. Interconnect scaling results in less control by processing or fabricating tools over the grain size of the metals. For example, the metal interconnect may have mixture of inconsistent grain sizes (e.g., smaller, medium, large grains) that may increase resistivity of the metal interconnect.

[0002] Fig. 1 illustrates plot 100 showing resistivity p (μΩ cm) of Copper (Cu) layers at

298 degrees Kelvin (K) versus thickness dcu (nm). Plot 100 shows three waveforms— 101, 102, and 103. Waveform 101 is the resistivity of Cu with small grain size. Waveform 102 is the resistivity of Cu with medium grain size, and waveform 103 is the resistivity of Cu with large grain size. As the grain size getters larger, the resistivity reduces. However, as the metal interconnect scales down, the metal interconnect may have inconsistent grains which result in less control over resistivity of the metal interconnect.

[0003] Traditional metals such as Cu also require an electro-migration barrier around the metal interconnect which reduces the effective area available for low resistance metal interconnect. As metal interconnects scale down in size, the effective area available for low resistance metal interconnect further reduces.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

[0005] Fig. 1 illustrates plot 100 showing resistivity p (μΩ cm) of Copper (Cu) layers at

298 degrees Kelvin versus thickness dcu (nm). [0006] Figs. 2A-G illustrate cross-sections of a die showing fabrication of templated metal interconnect and vias, in accordance with some embodiments of the disclosure.

[0007] Figs. 3A-G illustrate cross-sections of a die showing fabrication of templated metal interconnect and vias, in accordance with some embodiments of the disclosure.

[0008] Figs. 4A-D illustrate cross-sections of metal interconnect or vias with various templating configurations, in accordance with some embodiments of the disclosure.

[0009] Fig. 5A illustrates a lattice structure of an ordered metal interconnect and its templating layer with reference to Fig. 4A, in accordance with some embodiments of the disclosure.

[0010] Fig. 5B illustrates a Transmission Electron Microscopy (TEM) image of ordered

MgO and Fe crystallinity, in accordance with some embodiments of the disclosure.

[0011] Figs. 6A-B illustrate cross-sections of metal interconnect or vias with various templating configurations, in accordance with some embodiments of the disclosure.

[0012] Fig. 7 illustrates a lattice structure of an ordered metal interconnect and its templating layer with reference to Fig. 6B, in accordance with some embodiments of the disclosure.

[0013] Fig. 8 illustrates a lattice structure of an ordered metal interconnect made of Co and its templating layer made of Ag, in accordance with some embodiments of the disclosure.

[0014] Fig. 9 illustrates a lattice structure of an ordered metal interconnect made of Co-

Fe and its templating layer made of Ge-Ga, in accordance with some embodiments of the disclosure.

[0015] Fig. 10 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with templated metal interconnects and/or vias, according to some embodiments of the disclosure.

DETAILED DESCRIPTION

[0016] Some embodiments describe a highly efficient templating method and apparatus for creating high crystalline metal wires (or interconnect), vias, transistor gates, and/or contacts. In some embodiments, an apparatus is provided which comprises: a metal layer with ordered crystalline structure; a crystallinity templating layer coupled to the metal layer; and an oxide layer coupled to the crystallinity templating layer. In some embodiments, the metal layer is one of: Fe (Iron), Co (Cobalt), Ni (Nickel), Ru (Ruthenium), Cu (Copper), alloys of Fe and Co;

alloys of Ni and Co; Ag, and Heusler alloy metals. In some embodiments, the Heusler alloy metals is at least one of: CmMnAl, CmMnln, CmMnSn, NhMnAl, Ni₂MnIn, Ni₂MnSn,

Ni₂MnSb, Ni₂MnGa, Co₂MnAl, Co₂MnSi, Co₂MnGa, Co₂MnGe, Pd₂MnAl, Pd₂MnIn, Pd₂MnSn, Pd₂MnSb, Co₂FeSi, Co₂FeAl, Fe₂VAl, Mn₂VGa, Co₂FeGe.

[0017] In some embodiments, the crystallinity templating layer is one of: MgO

(Magnesium Oxide), STO (Strontium Titanate), MgAlO (Magnesium Aluminum Oxide, Ag (Silver), DySc0₃, GdSc0₃, BTO (e.g., BaTi0₃), or Molybdenum. In some embodiments, the crystallinity templating layer and the metal layer together form a pair of layers which is one of: MgO and Fe; MgO and Co; MgO and Ni; MgO and NiFe; MgO and NiCo; STO and Fe; STO and Co; STO and Ni; STO and NiFe; STO and NiCo; Ag and X₂YX, where X₂YX is a Heusler alloy; Ag and Si[l 11]; MgAlO and Fe; MgAlO and Co; MgAlO and Ni; MgAlO and NiFe; or MgAlO and NiCo. In some embodiments, for the case of the crystallinity templating layer being MgO and the metal layer being Co, a lattice of MgO is matched to a lattice of Co when rotated by 90°. In some embodiments, for the case of the crystallinity templating layer being Ag and the metal layer being a Heusler alloy, a lattice of Ag when rotated by 45° matches with a lattice of the Heusler alloy.

[0018] In some embodiments, the metal layer is Ru and the crystallinity templating layer is Molybdenum. In this case, a metal templates another metal. In some embodiments, a crystalline axis of the metal layer is set by the crystallinity templating layer. In some

embodiments, the metal layer and the crystallinity templating layer together form at least one of: a via; an interconnect; contact, or a transistor gate. In some embodiments, the crystallinity templating layer is coupled to three sides of the metal layer. In some embodiments, the crystallinity templating layer is coupled to four sides of the metal layer. In some embodiments, the crystallinity templating layer is coupled to two sides of the metal layer. In some

embodiments, the crystallinity templating layer is coupled to one side of the metal layer. In some embodiments, the crystallinity templating layer has an unordered structure.

[0019] There are many technical effects or benefits of the various embodiments. For example, in some embodiments, the templating of metal improves crystallinity of the metal which in turn reduces the resistivity and electro-migration of the metal. As such, the metal can be used for forming interconnect and mitigate the scaling impact of process technology nodes. The templating of metal as described with reference to the various embodiments also improves fabrication using subtracting processing. Other technical effects or benefits will be evident from the description of various embodiments and figures.

[0020] In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

[0021] Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

[0022] Throughout the specification, and in the claims, the term "connected" means a direct physical, electrical, or wireless connection between the things that are connected, without any intermediary devices. The term "coupled" means either a direct electrical or wireless connection between the things that are connected or an indirect electrical or wireless connection through one or more passive or active intermediary devices. The term "circuit" means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" means at least one current signal, voltage signal, magnetic signal, electromagnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0023] The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- 10% of a target value (unless specifically specified). Unless otherwise specified the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0024] For the purposes of the present disclosure, phrases "A and/or B" and "A or B" mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or

C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0025] The terms "left," "right" "front," "back," "top," "bottom," "over," "under," and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions.

[0026] Figs. 2A-G illustrate cross-sections 200, 220, 230, 240, 250, 260, and 270, respectively, of a die showing fabrication of templated interconnect and vias, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Figs. 2A-G having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0027] Although the fabrication processes with reference to Figs. 2A-G are shown in a particular order, the order of the actions can be modified. Thus, the illustrated embodiments can be performed in a different order, and some actions/fabrication processes may be performed in parallel. Some of the fabrication processes listed in Figs. 2A-G are optional in accordance with certain embodiments. The numbering of the fabrication processes presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur. Additionally, operations from the various flows may be utilized in a variety of combinations.

[0028] Fig. 2A illustrates one example of a starting point. Here, the die cross-section

200 shows deposition of a layer of dielectric 201. In some embodiments, the dielectric is an oxide (e.g., SiCte). In some embodiments, the process of fabricating the templated metal interconnect and vias can start at various points in the fabrication process as described with reference to various embodiments. Fig. 2B illustrates cross-section 220 of the die after deposition of a metal layer 202a of layer 201. For example, a layer of Cu, Fe, Ni, Co, Ag, NiFe, NiCo, or Heusler Alloy is deposited as metal layer 202a over layer of oxide 201. This layer of metal 202a may have an unordered crystalline structure.

[0029] Here, the term unordered crystalline structure generally refers to a crystalline structure in which the electron wave diffraction is not defined by Bragg' s law. Unordered materials may exhibit high directional and angular isotropy without long range spatial/directional periodicity. Unordered materials are characterized by a signature on a TEM (Transmission Electron Microscopy), STEM (Scanning Transmission Electron Microscopy) or RHEED

(Reflection High-Energy Electron Diffraction), XRD (X-ray Powder Diffraction) metrology.

[0030] Fig. 2C illustrates cross-section 230 of the die after deposition of a templating material 203 over metal layer 202a. In some embodiments, after increasing temperature, e.g., to 298K, templating material 203 causes metal layer 202a to transform to metal layer 202b, where metal layer 202b has an ordered crystalline structure while metal layer 202a has an unordered crystalline structure. In some embodiments, metal layer 202a is Metal 0 (M0) layer. In other embodiments, metal layer 202a can be any metal layer of a process technology node.

[0031] Fig. 2D illustrates cross-section 240 of the die after templating material 203 is removed and dielectric layer 204 (e.g., layer of oxide) is deposited over ordered metal layer 202b. Here, the term "ordered" generally refers to material condition that shows electron wave diffraction as defined by Bragg' s law. Ordered material may be characterized by one of the space groups combined with a unit cell. Ordered material exhibit long range periodicity both in direction and displacement. In Metrology tools such as XRD and RHEED, an interferometric signature is evident for ordered materials.

[0032] In some embodiments, templating material 203 is a sacrificial layer which is removed after the crystalline structure of metal layer 202b is ordered to be metal layer 202a. In some embodiments, templating material 203 remains as is and further processing steps are performed above templating material 203.

[0033] In some embodiments, metal layer 202a/b is one of: Fe, Co, Ni, Ru, Cu, alloys of

Fe and Co; alloys of Ni and Co; Ag, and Heusler alloy metals. In some embodiments, the Heusler alloy metals is at least one of: CmMnAl, CuzMnln, CuzMnSn, NhMnAl, Ni₂MnIn, Ni₂MnSn, Ni₂MnSb, Ni₂MnGa, Co₂MnAl, Co₂MnSi, Co₂MnGa, Co₂MnGe, Pd₂MnAl, Pd₂MnIn, Pd₂MnSn, Pd₂MnSb, CozFeSi, Co₂FeAl, Fe₂VAl, MmVGa, or CozFeGe.

[0034] In some embodiments, templating material 203 is a crystallinity templating layer which is one of: MgO, STO, MgAlO, Ag, DySc0₃, GdSc0₃, BTO (e.g., BaTi0₃), or

Molybdenum. In some embodiments, templating material 203 and metal layer 202a/b together form a pair of layers which is one of: MgO and Fe; MgO and Co; MgO and Ni; MgO and NiFe; MgO and NiCo; STO and Fe; STO and Co; STO and Ni; STO and NiFe; STO and NiCo; Ag and X2YX, where X₂YX is a Heusler alloy; Ag and Si[l 11]; MgAlO and Fe; MgAlO and Co;

MgAlO and Ni; MgAlO and NiFe; or MgAlO and NiCo.

[0035] In some embodiments, for the case of templating material 203 being MgO and metal layer 202a/b being CoxFey (or Co) a lattice of MgO is matched to a lattice of Co when rotated by 90°. In some embodiments, for the case of templating material 203 being Ag and metal layer 202a/b being a Heusler alloy, a lattice of Ag when rotated by 45° matches with a lattice of the Heusler alloy. In some embodiments, metal layer 202a/b is Ru and templating material 203 is Molybdenum. This is a case of metal templating another metal. In some embodiments, a crystalline axis of metal layer 202a/b is set by templating material 203.

[0036] Fig. 2E illustrates cross-section 250 of the die after trenches 205 are etched through dielectric layer 204. Any known suitable process of forming trenches 205 may be used. In this example, two trenches are etched (e.g., the left and right trenches) and each trench is a future location of a via to couple to metal layer 202b and a future location of another metal layer. In some embodiments, the other metal layer extends orthogonal to metal layer 202b. For example, metal layer 202b is metal layer 1 (Ml) and the other metal layer (later shown as 207) is metal layer 2 (M2).

[0037] Fig. 2F illustrates cross-section 260 of the die after templating material 206 is deposited along the outer walls of trenches 205. In some embodiments, templating material 206 is any of the materials discussed with reference to templating material 203. Any known method for depositing templating material 206 along the outer walls may be used. In this example, templating material 206 behaves as a liner which separates the via and interconnect metal from dielectric 204.

[0038] Fig. 2G illustrates cross-section 270 of the die after metal 207 is deposited in trench 205. In some embodiments, material deposited for the via is different from the material deposited for the metal interconnect. For example, material for via is Ag while the material for the metal interconnect is Cu. In some embodiments, metal 207 is any of the materials discussed with reference to metal layer 202a/b. In some embodiments, after increasing temperature (e.g., to 298K), templating material 206 causes metal 207 to transform from unordered crystalline structure to ordered crystalline structure.

[0039] In some embodiments, damascene based processing method are used for creating templated interconnect 202b and 206. In some embodiments, subtractive processing methods are used for creating templating interconnect 202b and 206. In some embodiments, recess processing method are used to take advantage of the templated interconnect 202b and 206. In some embodiments, super-lattice stacks comprising of repeated patterns of template enhancing material (e.g., as those described with reference to Figs. 6A-B) are used for metal 202b and metal 206.

[0040] Figs. 3A-G illustrate cross-sections 300, 320, 330, 340, 350, 360, and 370, respectively, of a die showing fabrication of templated interconnect and vias, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Figs. 3A-G having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0041] Although the fabrication processes with reference to Figs. 3A-G are shown in a particular order, the order of the actions can be modified. Thus, the illustrated embodiments can be performed in a different order, and some actions/fabrication processes may be performed in parallel. Some of the fabrication processes listed in Figs. 3A-G are optional in accordance with certain embodiments. The numbering of the fabrication processes presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur. Additionally, operations from the various flows may be utilized in a variety of combinations.

[0042] Figs. 3A-E are similar to Figs. 2A-E, and so they are not repeated again but a presented for completeness sake. In some embodiments, instead of forming liners of templating material along the edges of the trenches 205, metal 307 is deposited into trenches 205 as illustrated with reference Fig. 3F. In some embodiments, material deposited for the via is different from the material deposited for the metal interconnect. In some embodiments, metal 307 is any of the materials discussed with reference to metal layer 202a/b. In some

embodiments, templating material layer 308 is deposited over metal 307 to transfer unordered metal 307 to ordered metal 309. In some embodiments, after the crystalline structure of metal 307 is ordered, templating layer 308 may be removed. In some embodiments, after the crystalline structure of metal 307 is ordered, templating layer 308 is not removed and further processing continues. In some embodiments, templating layer 308 is formed of any of the materials of templating material 203. [0043] In some embodiments, damascene based processing method are used for creating templated interconnect 309. In some embodiments, subtractive processing methods are used for creating templated interconnect 309. In some embodiments, recess processing method are used to take advantage of the templated interconnect 309. In some embodiments, super-lattice stacks comprising of repeated patterns of template enhancing material (e.g., as those described with reference to Figs. 6A-B) are used for metal 308.

[0044] Figs. 4A-C illustrate cross-sections 400, 420, and 430, respectively, of interconnect or vias with various templating configurations, in accordance with some

embodiments of the disclosure. Fig. 4D illustrates cross-section 440 after templating layer is removed, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Figs. 4A-D having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0045] Cross-section 400 illustrates the case where templating material 401 is deposited on all four sides of interconnect metal 402. In some embodiments, templating material is any of the materials used for templating material 203. In some embodiments, metal 402 is any of the materials used for metal layer 202a/b. In some embodiments, the crystalline structure of templating material 401 is ordered while the crystalline structure of metal 402 is unordered. In some embodiments, the crystalline structure of templating material 401 is unordered while the crystalline structure of metal 402 is ordered. In some embodiments, when the combination of templating material 401 and metal 402 is heated (e.g., to about 298K), unordered crystalline structure metal 402 becomes ordered. As such, resistivity of metal 402 improves compared to its unordered crystalline state.

[0046] Cross-section 420 illustrates the case where the templating material is deposited along three sides of metal 402. In some embodiments, when the combination of templating material 421 and metal 402 is heated to about 298K, unordered crystalline structure metal 402 becomes ordered. As such, resistivity of metal 402 improves compared to its unordered crystalline state.

[0047] Cross-section 430 illustrates the case where templating material 431 is deposited along one side of metal 402. In some embodiments, when the combination of templating material 431 and metal 402 is heated (e.g., to about 298K), unordered crystalline structure metal 402 becomes ordered. As such, resistivity of metal 402 improves compared to its unordered crystalline state. Cross-section 440 illustrates the case where templating materials 431, or 421 or 401 are removed after chemical processing (e.g., etching process) leaving behind an ordered metal 402 with improved resistivity.

[0048] Fig. 5A illustrates lattice structure 500 of an ordered metal interconnect and its templating layer with reference to Fig. 4A, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Fig. 5A having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Lattice structure 500 shows that after templating layer 501/401 causes the crystalline structure of metal 502/402 to become ordered, the crystalline structure of metal 502/402 matches with that of templating layer 501/401. For example, when the crystalline structure of metal 502/402 is rotated by 90°, it matches with the crystalline structure of templating layer 501/401.

[0049] Fig. 5B illustrates a Transmission Electron Microscopy (TEM) image 520 of ordered MgO and Fe crystallinity, in accordance with some embodiments of the disclosure. Here, MgO is the templating layer and Fe is the metal interconnect that has ordered crystallinity due to MgO.

[0050] Figs. 6A-B illustrate cross-sections 600 and 620, respectively, of interconnect or vias with various templating configurations, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Figs. 6A-B having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0051] Cross-section 600 illustrates the case where a super-lattice interconnect stack is formed comprising of repeated patterns of template enhancing materials. In this example, metal 602, 603, and 604 is sandwiched between templating material layers 601a, 601b, 601c, and 601d. Here, metal layers 602, 603, and 604 are formed of any of the materials described with reference to metal 202a/b. In some embodiments, templating material layers 601a/b/c/d are formed of any of the materials described with reference to metal templating material 203. In some

embodiments, templating material layers 601a/d may not exist. In one such embodiments, templating layer 601b is sandwiched between metal layer 602 and metal layer 604, while templating layer 601c is sandwiched between metal layers 604 and 603 as shown. [0052] In some embodiments, metal layers 602, 603, and 604 are of the same material.

In some embodiments, metal layers 602, 603, and 604 are of different material. In some embodiments, templating material layers 601a/b/c/d are formed of the same material. In some embodiments, templating material layers 601a/b/c/d are formed are formed of different material. Cross-section 620 is similar to cross-section 600 except that templating material 621 surrounds the stack of metal layers and templating layers, in accordance with some embodiments. In some embodiments, in both cases (i.e., cross-sections 600 and 620), the crystalline structure of metal layers 602, 603, and 604 transforms from unordered to ordered due to the templating layer.

[0053] In some embodiments, the crystalline structure of templating layers 601a, 601b,

601c, and/or 601d is ordered while the crystalline structure of metal layers 602, 603, and/or 604 is unordered. In some embodiments, the crystalline structure of templating layers 601a, 601b, 601c, and/or 601d is unordered while the crystalline structure metal layers 602, 603, and/or 604 is ordered.

[0054] Fig. 7 illustrates lattice structure 700 of an ordered metal interconnect and its templating layer with reference to Fig. 6B, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Fig. 7 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0055] In some embodiments, the stack of metals 602, 603, and 604 comprise Co or Fe and alloys of BCC (body centered cube) crystallinity while the stack of templating layers 601b and 601c comprises of MgO with FCC (face centered cube) crystallinity. The lattice match occurs due to the ability for MgO to be deposited crystalline and seed a crystal structure into the metal, in accordance with some embodiments.

[0056] Fig. 8 illustrates lattice structure 800 of an ordered metal interconnect made of Co and its templating layer made of Ag, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Fig. 8 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0057] Here, three sections of lattice structure 800 are shown— 801, 802, and 803.

Sections 801 and 803 are templating material (e.g., Ag) while section 802 is the templated Heusler alloy which is a complex alloy of Co, Fe, and/or Ni. In this example, Ag lattice 801/803 when rotated by 45° matches with the lattice structure of the Heusler alloy.

[0058] Fig. 9 illustrates lattice structure 900 of an ordered metal interconnect made of

Co-Fe and its templating layer made of Ge-Ga, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Fig. 9 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Here, three sections of lattice structure 900 are shown— 901, 902, and 903. Sections 901 and 903 are templating material (e.g., Ag) while section 902 is the templated Ge-Ga.

[0059] Fig. 10 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with templated metal interconnects, contacts, transistor gates, and/or vias, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 10 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0060] Fig. 10 illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In some embodiments, computing device 1600 represents a mobile computing device, such as a computing tablet, a mobile phone or smart- phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 1600.

[0061] For purposes of the embodiments, the transistors in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors, which include drain, source, gate, and bulk terminals. The transistors also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon Transistors or other devices implementing transistor functionality like carbon nanotubes or spintronic devices. MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here. A TFET device, on the other hand, has asymmetric Source and Drain terminals. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors— BJT P P/NPN, BiCMOS, CMOS, eFET, etc., may be used without departing from the scope of the disclosure. [0062] In some embodiments, computing device 1600 includes first processor 1610 with templated metal interconnects, contacts, transistor gates, and/or vias, according to some embodiments discussed. Other blocks of the computing device 1600 may also include a spin logic device with stacking of magnets below a spin channel and with matched spacer for improved spin injection, according to some embodiments. The various embodiments of the present disclosure may also comprise a network interface within 1670 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

[0063] In some embodiments, processor 1610 (and/or processor 1690) can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor 1610 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 1600 to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

[0064] In some embodiments, computing device 1600 includes audio subsystem 1620, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1600, or connected to the computing device 1600. In one embodiment, a user interacts with the computing device 1600 by providing audio commands that are received and processed by processor 1610.

[0065] In some embodiments, computing device 1600 comprises display subsystem

1630. Display subsystem 1630 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1600. Display subsystem 1630 includes display interface 1632, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface 1632 includes logic separate from processor 1610 to perform at least some processing related to the display. In one embodiment, display subsystem 1630 includes a touch screen (or touch pad) device that provides both output and input to a user.

[0066] In some embodiments, computing device 1600 comprises I/O controller 1640.

I/O controller 1640 represents hardware devices and software components related to interaction with a user. I/O controller 1640 is operable to manage hardware that is part of audio subsystem 1620 and/or display subsystem 1630. Additionally, I/O controller 1640 illustrates a connection point for additional devices that connect to computing device 1600 through which a user might interact with the system. For example, devices that can be attached to the computing device 1600 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

[0067] As mentioned above, I/O controller 1640 can interact with audio subsystem 1620 and/or display subsystem 1630. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1600. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 1630 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 1640. There can also be additional buttons or switches on the computing device 1600 to provide I/O functions managed by I/O controller 1640.

[0068] In some embodiments, I/O controller 1640 manages devices such as

accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 1600. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

[0069] In some embodiments, computing device 1600 includes power management 1650 that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 1660 includes memory devices for storing information in computing device 1600. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 1660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1600.

[0070] Elements of embodiments are also provided as a machine-readable medium (e.g., memory 1660) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein). The machine-readable medium (e.g., memory 1660) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

[0071] In some embodiments, computing device 1600 comprises connectivity 1670.

Connectivity 1670 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1600 to communicate with external devices. The computing device 1600 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

[0072] Connectivity 1670 can include multiple different types of connectivity. To generalize, the computing device 1600 is illustrated with cellular connectivity 1672 and wireless connectivity 1674. Cellular connectivity 1672 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile

communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 1674 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

[0073] In some embodiments, computing device 1600 comprises peripheral connections

1680. Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 1600 could both be a peripheral device ("to" 1682) to other computing devices, as well as have peripheral devices ("from" 1684) connected to it. The computing device 1600 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 1600. Additionally, a docking connector can allow computing device 1600 to connect to certain peripherals that allow the computing device 1600 to control content output, for example, to audiovisual or other systems.

[0074] In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 1600 can make peripheral connections 1680 via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

[0075] Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or

characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an

embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

[0076] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive. [0077] While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

[0078] In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

[0079] The following examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

[0080] For example, an apparatus sis provided which comprises: a metal layer having an ordered crystalline structure; a crystallinity templating layer adjacent to the metal layer; and an oxide layer adjacent to the crystallinity templating layer. In some embodiments, the metal layer is one of: Fe, Co, Ni, Ru, Cu, alloys of Fe and Co; alloys of Ni and Co; Ag; and Heusler alloy metals. In some embodiments, the Heusler alloy metals is at least one of: CmMnAl, CmMnln, CmMnSn, Ni₂MnAl, Ni₂MnIn, Ni₂MnSn, Ni₂MnSb, Ni₂MnGa, Co₂MnAl, Co₂MnSi, Co₂MnGa, Co₂MnGe, Pd₂MnAl, Pd₂MnIn, Pd₂MnSn, Pd₂MnSb, CozFeSi, Co₂FeAl, Fe₂VAl, MmVGa, or CozFeGe.

[0081] In some embodiments, the crystallinity templating layer is one of: MgO, STO,

MgAlO, Ag, DyScCb, GdScCb, BTO, or Molybdenum. In some embodiments, the crystallinity templating layer and the metal layer together form a pair of layers which is one of: MgO and Fe; MgO and Co; MgO and Ni; MgO and NiFe; MgO and NiCo; STO and Fe; STO and Co; STO and Ni; STO and NiFe; STO and NiCo; Ag and X₂YX, where X₂YX is a Heusler alloy; Ag and Si[l 11]; MgAlO and Fe; MgAlO and Co; MgAlO and Ni; MgAlO and NiFe; or MgAlO and NiCo.

[0082] In some embodiments, for the case of the crystallinity templating layer being

MgO and the metal layer being CoxFey, a lattice of MgO is matched to a lattice of Co when rotated by 90°. In some embodiments, for the case of the crystallinity templating layer being Ag and the metal layer being a Heusler alloy, a lattice of Ag when rotated by 45° matches with a lattice of the Heusler alloy. In some embodiments, the metal layer is Ru and the crystallinity templating layer is Molybdenum. In some embodiments, a crystalline axis of the metal layer is aligned with the crystallinity of templating layer. In some embodiments, the metal layer and the crystallinity templating layer together form at least one of: a via; an interconnect; or a transistor gate. In some embodiments, the crystallinity templating layer is adjacent to three sides of the metal layer. In some embodiments, the crystallinity templating layer is adjacent to four sides of the metal layer. In some embodiments, the crystallinity templating layer is adjacent to one side of the metal layer. In some embodiments, the crystallinity templating layer has an unordered structure.

[0083] In another example, a system is provided which comprises: a memory; a processor coupled to the memory, the processor comprising an apparatus according to the apparatus described above; and a wireless interface allowing the processor to communicate with another device.

[0084] In another example, an apparatus is provided which comprises: a metal layer with an unordered crystalline structure; a crystallinity templating layer adjacent to the metal layer; and a dielectric layer adjacent to the crystallinity templating layer. In some embodiments, the crystallinity templating layer has an ordered structure. In some embodiments, the crystallinity templating layer is a material selected from the group consisting of MgO, STO, MgAlO, Ag, DySc0₃, GdSc0₃, BTO, and Molybdenum.

[0085] In some embodiments, the crystallinity templating layer and the metal layer together form a pair of layers which is one of: MgO and Fe; MgO and Co; MgO and Ni; MgO and NiFe; MgO and NiCo; STO and Fe; STO and Co; STO and Ni; STO and NiFe; STO and NiCo; Ag and X₂YX, where X₂YX is a Heusler alloy; Ag and Si[l 11]; MgAlO and Fe; MgAlO and Co; MgAlO and Ni; MgAlO and NiFe; or MgAlO and NiCo. [0086] In some embodiments, for the case of the crystallinity templating layer being

[0087] In another example, a system is provided which comprises: a memory; a processor coupled to the memory, the processor comprising an apparatus according to the apparatus described above; and a wireless interface allowing the processor to communicate with another device.

[0088] In another example, an apparatus is provided which comprises: a first metal layer; a first crystallinity templating layer adjacent to the first metal layer; a second metal layer adjacent to the first crystallinity templating layer such that the first crystallinity templating layer is sandwiched between the first metal layer and the second metal layer; and a second crystallinity templating layer adjacent to the second metal layer. In some embodiments, the apparatus comprises a third crystallinity templating layer adjacent to a portion of the first metal layer, the first crystallinity templating layer, the second metal layer, and the second crystallinity templating layer.

[0089] In some embodiments, material of the first crystallinity templating layer is same as material of the second crystallinity templating layer. In some embodiments, material of the first crystallinity templating layer is different from material of the second crystallinity templating layer. In some embodiments, the first and second metal layers are one of: Fe, Co, Ni, Ru, Cu, alloys of Fe and Co; alloys of Ni and Co; Ag; and Heusler alloy metals. In some embodiments, the first and second crystallinity templating layers are one of: MgO, STO, MgAlO, Ag, DyScCb, GdScC-3, BTO, or Molybdenum.

[0090] In some embodiments, the first crystallinity templating layer and the and the first metal layer together form a pair of layers which is one of: MgO and Fe; MgO and Co; MgO and Ni; MgO and NiFe; MgO and NiCo; STO and Fe; STO and Co; STO and Ni; STO and NiFe; STO and NiCo; Ag and X₂YX, where X₂YX is a Heusler alloy; Ag and Si[l 11]; MgAlO and Fe; MgAlO and Co; MgAlO and Ni; MgAlO and NiFe; or MgAlO and NiCo.

[0091] In another example, a system is provided which comprises: a memory; a processor coupled to the memory, the processor comprising an apparatus according to the apparatus described above; and a wireless interface allowing the processor to communicate with another device.

[0092] In another example, an integrated circuit die is provided which comprises: an interlayer dielectric layer; and an interconnect formed within the interlayer dielectric layer, the interconnect comprising a crystalline metal. In some embodiments, the interconnect further comprises a material selected from the group consisting of MgO, STO, MgAlO, Ag, DySc0₃, GdSc0₃, BTO, and Molybdenum. In some embodiments, the integrated circuit die comprises a layer adjacent to the interconnect, wherein layer is formed of a material selected from a group consisting of MgO, STO, MgAlO, Ag, DySc0₃, GdSc0₃, BTO, and Molybdenum.

[0093] In another example, a system is provided which comprises: a memory; a processor coupled to the memory, the processor comprising an integrated circuit die according to the integrated circuit described above; and a wireless interface allowing the processor to communicate with another device.

[0094] In another example, a method is provided which comprises: depositing a metal layer having an ordered crystalline structure; depositing a crystallinity templating layer adjacent to the metal layer; and depositing an oxide layer adjacent to the crystallinity templating layer. In some embodiments, the metal layer is one of: Fe, Co, Ni, Ru, Cu, alloys of Fe and Co; alloys of Ni and Co; Ag; and Heusler alloy metals. In some embodiments, the Heusler alloy metals is at least one of: CmMnAl, Cu₂MnIn, CmMnSn, Ni₂MnAl, Ni₂MnIn, Ni₂MnSn, Ni₂MnSb,

Ni₂MnGa, Co₂MnAl, Co₂MnSi, Co₂MnGa, Co₂MnGe, Pd₂MnAl, Pd₂MnIn, Pd₂MnSn, Pd₂MnSb, Co₂FeSi, Co₂FeAl, Fe₂VAl, MmVGa, or Co₂FeGe. [0095] In some embodiments, the crystallinity templating layer is one of: MgO, STO,

MgAlO, Ag, DySc0₃, GdSc0₃, BTO, or Molybdenum. In some embodiments, the crystallinity templating layer and the metal layer together form a pair of layers which is one of: MgO and Fe; MgO and Co; MgO and Ni; MgO and NiFe; MgO and NiCo; STO and Fe; STO and Co; STO and Ni; STO and NiFe; STO and NiCo; Ag and X₂YX, where X₂YX is a Heusler alloy; Ag and Si[l 11]; MgAlO and Fe; MgAlO and Co; MgAlO and Ni; MgAlO and NiFe; or MgAlO and NiCo. In some embodiments, for the case of the crystallinity templating layer being MgO and the metal layer being CoxFey, a lattice of MgO is matched to a lattice of Co when rotated by 90°.

[0096] In some embodiments, for the case of the crystallinity templating layer being Ag and the metal layer being a Heusler alloy, a lattice of Ag when rotated by 45° matches with a lattice of the Heusler alloy. In some embodiments, the metal layer is Ru and the crystallinity templating layer is Molybdenum. In some embodiments, a crystalline axis of the metal layer is aligned with the crystallinity of templating layer. In some embodiments, the metal layer and the crystallinity templating layer together form at least one of: a via; an interconnect; or a transistor gate. In some embodiments, the crystallinity templating layer is adjacent to three sides of the metal layer. In some embodiments, the crystallinity templating layer is adjacent to four sides of the metal layer. In some embodiments, the crystallinity templating layer is adjacent to one side of the metal layer. In some embodiments, crystallinity templating layer has an unordered structure.

[0097] In another example, a method is provided which comprises: depositing a metal layer with an unordered crystalline structure; depositing a crystallinity templating layer adjacent to the metal layer; and depositing a dielectric layer adjacent to the crystallinity templating layer. In some embodiments, the crystallinity templating layer has an ordered structure. In some embodiments, the crystallinity templating layer is a material selected from the group consisting of MgO, STO, MgAlO, Ag, DySc0₃, GdSc0₃, BTO, and Molybdenum.

[0098] In another example, a method is provided which comprises: depositing an interlayer dielectric layer; and depositing an interconnect formed within the interlayer dielectric layer, the interconnect comprising a crystalline metal. In some embodiments, the interconnect further comprises a material selected from the group consisting of MgO, STO, MgAlO, Ag, DySc0₃, GdSc0₃, BTO, and Molybdenum. In some embodiments, the method comprises depositing a layer adjacent to the interconnect, wherein layer is formed of a material selected from a group consisting of MgO, STO, MgAlO, Ag, DySc0₃, GdSc0₃, BTO, and Molybdenum [0099] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

CLAIMS We claim:

1. An apparatus comprising:

a metal layer having an ordered crystalline structure;

a crystallinity templating layer adjacent to the metal layer; and

an oxide layer adjacent to the crystallinity templating layer.

2. The apparatus of claim 1, wherein the metal layer is one of: Fe, Co, Ni, Ru, Cu, alloys of Fe and Co; alloys of Ni and Co; Ag; and Heusler alloy metals.

3. The apparatus of claim 2, wherein the Heusler alloy metals is at least one of: CmMnAl, Cu2MnIn, CmMnSn, NiiMnAl, Xi A ! n u Ni2MnSn, NiiMnSb, N MnGa, Co2MnAl,

Co₂MnSi, OoA f nGa. Co₂MnGe, Pd₂MnAl, P lA f n ln. PdzMnSn, Pd₂MnSb, Co₂FeSi,

Co2FeAI, Fe₂VAl, MmVGa, or CdFeGe.

4. The apparatus of claim 2, wherein the crystallinity templating layer is one of: MgO, STO, MgAlO, Ag, DySc0₃, GdSc0₃, BTO, or Molybdenum.

5. The apparatus of claim 1, wherein the crystallinity templating layer and the metal layer together form a pair of layers which is one of: MgO and Fe; MgO and Co; MgO and Ni; MgO and NiFe; MgO and NiCo; STO and Fe; STO and Co; STO and Ni; STO and NiFe; STO and NiCo; Ag and X₂YX, where X₂YX is a Heusler alloy; Ag and Si[l 11]; MgAlO and Fe; MgAlO and Co; MgAlO and Ni; MgAlO and NiFe; or MgAlO and NiCo.

6. The apparatus of claim 5, wherein for the case of the crystallinity templating layer being MgO and the metal layer being CoxFey, a lattice of MgO is matched to a lattice of Co when rotated by 90°.

7. The apparatus of claim 5, wherein for the case of the crystallinity templating layer being Ag and the metal layer being a Heusler alloy, a lattice of Ag when rotated by 45° matches with a lattice of the Heusler alloy.

8. The apparatus of claim 1, wherein the metal layer is Ru and the crystallinity templating layer is Molybdenum.

9. The apparatus of claim 1, wherein a crystalline axis of the metal layer is aligned with the crystallinity of templating layer.

10. The apparatus of claim 1, wherein the metal layer and the crystallinity templating layer together form at least one of: a via; an interconnect; or a transistor gate.

11. The apparatus of claim 1, wherein the crystallinity templating layer is adjacent to three sides of the metal layer.

12. The apparatus of claim 1, wherein the crystallinity templating layer is adjacent to four sides of the metal layer.

13. The apparatus of claim 1, wherein the crystallinity templating layer is adjacent to one side of the metal layer.

14. The apparatus of claim 1, wherein the crystallinity templating layer has an unordered

structure.

15. An apparatus comprising:

a metal layer with an unordered crystalline structure;

a crystallinity templating layer adjacent to the metal layer; and

a dielectric layer adjacent to the crystallinity templating layer.

16. The apparatus of claim 15, wherein the crystallinity templating layer has an ordered

structure.

17. The apparatus of claim 15, wherein the crystallinity templating layer is a material selected from the group consisting of MgO, STO, MgAlO, Ag, DySc0₃, GdSc0₃, BTO, and

Molybdenum.

18. The apparatus of claim 15 according to any one of claims 2 to 13.

19. An apparatus comprising:

a first metal layer;

a first crystallinity templating layer adjacent to the first metal layer;

a second metal layer adjacent to the first crystallinity templating layer such that the first crystallinity templating layer is sandwiched between the first metal layer and the second metal layer; and

a second crystallinity templating layer adjacent to the second metal layer.

20. The apparatus of claim 19 comprises a third crystallinity templating layer adjacent to a

portion of the first metal layer, the first crystallinity templating layer, the second metal layer, and the second crystallinity templating layer.

21. The apparatus of claim 20, wherein material of the first crystallinity templating layer is same as material of the second crystallinity templating layer.

22. The apparatus of claim 20, wherein material of the first crystallinity templating layer is

different from material of the second crystallinity templating layer.

23. The apparatus of claim 20, wherein the first and second metal layers are one of: Fe, Co, Ni, Ru, Cu, alloys of Fe and Co; alloys of Ni and Co; Ag; and Heusler alloy metals.

24. The apparatus of claim 23, wherein the first and second crystallinity templating layers are one of: MgO, STO, MgAlO, Ag, DySc0₃, GdSc0₃, BTO, or Molybdenum.

25. The apparatus of claim 20, wherein the first crystallinity templating layer and the and the first metal layer together form a pair of layers which is one of: MgO and Fe; MgO and Co; MgO and Ni; MgO and NiFe; MgO and NiCo; STO and Fe; STO and Co; STO and Ni; STO and NiFe; STO and NiCo; Ag and X₂YX, where X₂YX is a Heusler alloy; Ag and Si[l 11];

MgAlO and Fe; MgAlO and Co; MgAlO and Ni; MgAlO and NiFe; or MgAlO and NiCo.

26. An integrated circuit die comprising:

an interlayer dielectric layer; and

an interconnect formed within the interlayer dielectric layer, the interconnect comprising a crystalline metal.

27. The integrated circuit die of claim 26, wherein the interconnect further comprises a material selected from the group consisting of MgO, STO, MgAlO, Ag, DySc0₃, GdSc0₃, BTO, and Molybdenum.

28. The integrated circuit die of claim 26 comprises a layer adjacent to the interconnect, wherein layer is formed of a material selected from a group consisting of MgO, STO, MgAlO, Ag, DySc0₃, GdSc0₃, BTO, and Molybdenum.