WO2017048229A1

WO2017048229A1 - Large signal two transistor memory with magneto-electric spin orbit device

Info

Publication number: WO2017048229A1
Application number: PCT/US2015/050056
Authority: WO
Inventors: Sasikanth Manipatruni; Dmitri E. Nikonov; Anurag Chaudhry; Ian A. Young
Original assignee: Intel Corporation
Priority date: 2015-09-14
Filing date: 2015-09-14
Publication date: 2017-03-23
Also published as: TW201721644A

Abstract

Described is an apparatus which comprises: a first transistor; a second transistor having a first terminal coupled to a first terminal of the first transistor; a first conductor coupled to a second terminal of the second transistor; a magnetoelectric (ME) layer coupled to the first conductor; and a ferromagnetic (FM) layer coupled to the ME layer and to a second terminal of the first transistor.

Description

LARGE SIGNAL TWO TRANSISTOR MEMORY WITH MAGNETO-ELECTRIC SPIN

ORBIT DEVICE

BACKGROUND

[0001] Detecting a state of a magnet is a basic computation step for magnetic memory and magnetic logic devices. The state of the magnet determines whether it is storing a logic zero or logic one. An example of a magnetic memory is Spin Transfer Torque (STT) Magnetic Random Access Memory (MRAM). In STT MRAM, the state of the magnetic memory is determined by sensing a resistance of a magnetic device of the memory, and then comparing that resistance against a reference resistance. Conversion of the magnetic state to a charge variable is also important for magnetic spin logic and interconnects. For example, a charge variable such as current can flow through long interconnects to other magnetic spin logic. Existing magnet detection is based on magnetic tunnel junctions (MTJs) and/or spin current interconnects which suffer from several limitations, however.

[0002] For example, conversion from spin current to charge variable mediated by

Tunneling Magneto Resistance (TMR) has limited conversion efficiency, TMR based readout from a memory limits the device resistance to a range of 4k to 8K Ohms, and spin current based interconnects are limited in interconnect length due to spin degradation along the length of the interconnect. These limitations and constraints result in inefficient switching, limited read speeds of the STT MRAM, and limited interconnect options for spin logic.

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

[0004] Fig. 1A illustrates a three dimensional (3D) view of a Magneto-electric Spin

Orbit Coupling (ME SOC) Device, according to some embodiments of the disclosure.

[0005] Fig. IB illustrates a 3D view of a ME SOC Device, according to some embodiments of the disclosure.

[0006] Fig. 2 illustrates a schematic of a two-transistor (2T) memory bit-cell with a

ME SOC Device, according to some embodiments of the disclosure.

[0007] Fig. 3 illustrates a layout of a 2T memory bit-cell with ME SOC Device, according to some embodiments of the disclosure. [0008] Figs. 4A-B illustrate schematic and layout, respectively, of a row or column of

2T memory bit-cells with ME SOC Devices, according to some embodiments of the disclosure.

[0009] Fig. 5A illustrates a plot showing magnetic hysteresis during operation of a 2T memory bit-cell with a ME SOC Device, according to some embodiments of the disclosure.

[0010] Fig. 5B illustrates a plot showing output read-out current relative to an input current for a 2T memory bit-cell with a ME SOC Device, according to some embodiments of the disclosure.

[0011] Fig. 6 illustrates a 3D magnetization plot showing operation of a 2T memory bit-cell with a ME SOC Device, according to some embodiments of the disclosure.

[0012] Fig. 7 illustrates a plot showing comparison of transient operating speed of a memory formed using magneto-electric switching relative to a memory formed using Spin Torque Transfer based switching, in accordance with some embodiments of the disclosure.

[0013] Figs. 8A-C illustrate a flowchart of a method for reading a logic state from the

2T memory bit-cell, schematic, and layout of the 2T memory bit-cell during read operation, in accordance with some embodiments of the disclosure.

[0014] Figs. 9A-C illustrate flowchart of a method for writing a logic state to 2T memory bit-cell, schematic and layout of the 2T memory bit-cell during write operation, in accordance with some embodiments of the disclosure.

[0015] Fig. 10 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with a 2T memory bit-cell with ME SOC Device, according to some embodiments.

DETAILED DESCRIPTION

[0016] Some embodiments describe a two-transistor (2T) memory bit-cell with

Magneto-electric Spin Orbit Coupling (ME SOC) Device. In some embodiments, the readout from the 2T bit-cell is via Inverse Spin Orbit Coupling (ISOC). In some embodiments, writing to the 2T bit-cell is via magneto-electric (ME) effect. In some embodiments, the two transistors of the 2T bit-cell are controlled by a read word-line (WL) and a write WL, respectively. In some embodiments, a bit-line (BL) is coupled to the two transistors. In some embodiments, a source-line (SL) is coupled to the ME SOC Device.

[0017] There are many technical effects of the various embodiments. For example, high speed switching is realized along with large adjustable signal read-out for use as high speed non-volatile logic element. As such, the output of the 2T memory bit-cell is large enough to drive another stage and/or is operable to be read using a simple read circuit, in accordance with some embodiments. In some embodiments, the adjustable strength output signal is generated by ISOC based transduction.

[0018] The 2T bit-cell of the various embodiments achieves high speed operation using magneto-electric write mechanism as opposed to spin torque transfer (STT) based switching mechanism. For example, the 2T bit-cell achieves 200ps or faster response time. The 2T bit-cell of the various embodiments performs at lower power because low

programming voltages are enabled by the magneto-electric effect. For example, the programming voltages can be on the order of lOOmV. The 2T bit-cell of the various embodiments achieves lower write error rates (WERs) to enable faster memory. For example, the memory operates at less than 0.5ns. The architecture of the 2T bit-cell of the various embodiments achieves a decoupled write and read path. Other technical effects will be evident by the various embodiments.

[0019] In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

[0020] Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

[0021] Throughout the specification, and in the claims, the term "connected" means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices. The term "circuit" or "module" may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0022] The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- 10% of a target value (unless specifically specified). Unless otherwise specified the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0023] For the purposes of the present disclosure, phrases "A and/or B" and "A or B" mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0024] For purposes of the embodiments, the transistors in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include drain, source, gate, and bulk terminals. The transistors and/or the MOS transistor derivatives also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon Transistors, ferroelectric FET (FeFETs), or other devices implementing transistor functionality like carbon nanotubes or spintronic devices. MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here. A TFET device, on the other hand, has asymmetric Source and Drain terminals. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors— BJT PNP/NPN, BiCMOS, CMOS, eFET, etc., may be used without departing from the scope of the disclosure. The term "M " indicates an n-type transistor (e.g., NMOS, NPN BJT, etc.) and the term "MP" indicates a p-type transistor (e.g., PMOS, PNP BJT, etc.).

[0025] Fig. 1A illustrates a three dimensional (3D) view of ME SOC Device 100, according to some embodiments of the disclosure. In some embodiments, ME SOC Device 100 comprises non-magnetic conducting interconnects lOla/b (collectively referred to as 101), a stack of Inverse Spin Orbit Coupling (ISOC) materials (collectively referred to as ISOC layer 154), magneto-electric (ME) layer 105, and ferromagnet (FM) layer 106. Here, non-magnetic conducting interconnect 101a is the input interconnect while non-magnetic conducting interconnect 101b is the output interconnect. In some embodiments, interconnect 101a and interconnect 101b extend parallel to one another.

[0026] In some embodiments, non-magnetic interconnect is made of any suitable conducting material such as Copper (Cu). In some embodiments, ISOC layer(s) 154 is formed of layers 102, 103, and/or 104 convert spin current to charge current. In some embodiments, spin-to-charge conversion is achieved using ISOC layer 154 via spin orbit interaction in metallic interfaces (i.e., using Inverse Rashba-Edelstein Effect (IREE) and/or Inverse spin Hall effect (ISHE), where a spin current injected from FM layer 106 produces a charge current in output conductor 101b.

[0027] Table 1 summarizes transduction mechanisms for converting spin current to charge current and charge current to spin current for bulk materials and interfaces.

Table 1: Transduction mechanisms for Spin to Charge and Charge to Spin Conversion using SOC

[0028] In some embodiments, ISOC layer 154 comprises a stack of layers formed of layers 102, 103, and/or 104 with materials exhibiting IREE and ISHE. In some

embodiments, ISOC layer 154 comprises a metal layer 104, such as a layer of Copper (Cu), Silver (Ag), or Gold (Au), or other high spin diffusion length materials such as Aluminum (Al) which is coupled to FM layer 106. In some embodiments, material(s) used for metal layer 104 is a material with high density of states and with large spin diffusion length. In some embodiments, metal layer 104 may behave as a spacer between FM layer 106 and the spin injection stack (which is part of ISOC layer 154). In some embodiments, metal layer 104 is a non-alloy metal layer. In some embodiments, the metal of metal layer 104 which is directly coupled to FM layer 106 is a noble metal (e.g., Ag, Cu, or Au) doped with other elements from group 4d and/or 5d of the Periodic Table.

[0029] In some embodiments, ISOC layer 154 acts as the appropriate template for creating FM layer 106 or provides a suitable atomic structure for high spin injection and low lattice mismatch. In some embodiments, the ISOC layer comprises layer(s) of a surface alloy 103, e.g. Bismuth (Bi) on Ag coupled to metal layer 104 and bulk layer 102. In various embodiments, metal layer 104 is considered to be part of ISOC layer 154. However, ISOC layer 154 can also be defined as a layer formed of surface alloy layer 103 and bulk layer 102. [0030] In some embodiments, bulk layer 102 is a stack of materials such as a stack of

Ag-Bi-Ag; Cu-Bi-Ag; Cu-Bi-Ag-[Cu-Bi-Ag]_n (where 'n' is an integer); Cu-Bi-Ag-[Cu-Bi- Ag][PbAg-SbAg]_; Cu and Cu-Bi-Ag- -Ta; Cu and Cu-Bi-Ag, β-W; Cu and Cu-Bi-Ag- β-Hf; Cu and Cu-Bi-Ag-Bi_xSe_y, etc. In some embodiments, ISOC layer 154 comprises elements of 5d transition series or materials with high spin to orbit coupling (topological materials) such as BiSe and BiTe. In some embodiments, ISOC layer 154 comprises bulk layer 102 which is directly coupled to FM layer 106 and interconnect 101b.

[0031] In some embodiments, surface alloy 103 is a templating metal layer (also referred to as the interface layer) to provide a template for forming FM layer 106. In some embodiments, surface alloy 103 is one of: Bi-Ag, Antimony-Bismuth (Sb-Bi), Sb-Ag, Lead- Nickel (Pb-Ni), Bi-Au, Pb-Ag, Pb-Au, β-Ta; β-W; Pt; or Bi2Te3. In some embodiments, one of the metals of surface alloy 103 is an alloy of heavy metal or of materials with high SOC strength, where the SOC strength is directly proportional to the fourth power of the atomic number of the metal.

[0032] In some embodiments, surface alloy is formed between Bi and Ag such that a surface corrugation is maintained (i.e., the positions of Bi atoms are offset by varying distance from a plane parallel to a crystal plane of the underlying metal). In some embodiments, surface alloy 103 is a structure not symmetric relative to the mirror inversion defined by a crystal plane. This inversion asymmetry and/or material properties lead to spin- orbit coupling in electrons near the surface (also referred to as the Rashba effect).

[0033] In some embodiments, ME layer 105 together with interconnect 101a and FM layer 106 forms the magnetic storage element (i.e., ME oxide capacitor 155). In some embodiments, ME oxide capacitor 155 defines an input node of the device that includes interconnect 101a and FM layer 106 as electrical conductors or plates separated by magnetoelectric dielectric material 105 such as bismuth ferrite (BFO), chromium (III) oxide (Cr203) (i.e., Chromia), or magnesium oxide (MgO). In some embodiments, ME oxide capacitor 155 may comprise of multi-phase multi-ferroics which are formed via layered or ordered deposition of correlated oxides such as BFO/CoFeO. In some embodiments, ME layer 105 may employ the use of hybrid magneto-electric effect using strain as an intermediate variable for transduction.

[0034] In some embodiments, a material for ME layer 105 is a single material that directly produces a magnetoelectric effect. In some embodiments, the material for ME layer 105 is a combination of materials such as multiple layers of oxides and intermetallics that define a dielectric stack. Such combination of materials may achieve a magnetoelectric effect through, for example, cascading of two transductions or physical phenomena in materials (e.g., cascading of a voltage to strain transduction and a strain to magnetization transduction). In some embodiments, the charge current carried by interconnect 101a produces a voltage on ME capacitor 155 including magnetoelectric dielectric material 105 (also referred to as ME layer 105) in contact with FM layer 106.

[0035] In some embodiments, the materials for ME layer 105 are either intrinsic multiferroics or composite multiferroic structures. These multi-phase materials may comprise of two phases of dielectrics where a 0D material is embedded in 3D, ID material embedded in 3D (nanotubes in a matrix), 2D-2D (layered stack), etc. In some embodiments, as the charge accumulates on ME capacitor 155, a strong magnetoelectric interaction causes a switching of magnetization in FM layer 106. In some embodiments, switching of a direction of magnetization in FM layer 106 is a result of an exchange bias from dielectric material 105 such as BFO that creates a surface magnetization to switch FM layer 106; a result of magnetostrictive stress anisotropy in a ferromagnetic material (Fe3Ga) such as lead- zirconium-titinate (PZT); or surface anisotropy as a result of application of a voltage to a dielectric material such as MgO.

[0036] In some embodiments, magnetoelectric capacitor 155 representatively has the following parameters: thickness IME = 5 nm, dielectric constant ε = 500, area A = 60 nm x 20 nm. Then the capacitance of magnetoelectric capacitor 155 can be expressed as: = ^! « lF

*ME

[0037] Demonstrated values of the magnetoelectric coefficient is ( ~10/ , where 'c' is the speed of light. This translates to an effective magnetic field exerted on FM layer 106 of about 0.06 Tesla (T):

B_UF = x E = ^aME^VisHE 0.06Γ

ME ME ,

ME

[0038] This is a strong field sufficient to switch a direction of magnetization in FM layer 106. Continuing with the example, the charge on ME capacitor 155 is give as:

Q = 1/F * 10 mV = 10 aC. The time to fully charge ME capacitor 155 to the induced voltage is td = 10 Q/Ia ps (with the account of decreased voltage difference as ME capacitor 155 charges). If the driving voltage is Vd = 100 mV, then the energy to switch FM layer 106 is approximately: Esw = 100 mV* 100 μΑ* 1 ps 10 aJ,

which is comparable to the switching energy of CMOS transistors.

[0039] In some embodiments, FM layer 106 is a free magnet that is made from CFGG

(i.e., Cobalt (Co), Iron (Fe), Germanium (Ge), or Gallium (Ga) or a combination of them). In some embodiments, FM layer 106 is a free magnet that is formed from Heusler alloy.

Heusler alloy is ferromagnetic metal alloy based on a Heusler phase. Heusler phase is intermetallic with certain composition and face-centered cubic crystal structure. The ferromagnetic property of the Heusler alloy is a result of a double-exchange mechanism between neighboring magnetic ions.

[0040] In some embodiments, FM layer 106 is a Heusler alloy lattice matched to Ag

(i.e., the Heusler alloy is engineered to have a lattice constant close (e.g., within 3%) to that of Ag or to a rotated lattice). In some embodiments, the direction of the spin polarization is determined by the magnetization direction of FM layer 106. In some embodiments, the magnetization direction of FM layer 106 depends on the direction of the strain provided by ME layer 105, which in turn depends on the direction of the input charge current Icharge (IN).

[0041] In some embodiments, FM layer 106 is formed of Heusler alloy, Co, Fe, Ni,

Gd, B, Ge, Ga, or a combination of them. In some embodiments, Heusler alloy that forms FM layer 106 is one of: Cu₂MnAl, Cu₂MnIn, Cu₂MnSn, Ni₂MnAl, Ni₂MnIn, Ni₂MnSn, Ni₂MnSb, Ni₂MnGa Co₂MnAl, Co₂MnSi, Co₂MnGa, Co₂MnGe, Pd₂MnAl, Pd₂MnIn, Pd₂MnSn, Pd₂MnSb, Co₂FeSi, Co₂FeAl, Fe₂VAl, Mn₂VGa, Co₂FeGe, MnGa, or MnGaRu.

[0042] In some embodiments, when the spin current L in FM layer 106 flows through the 2D (two dimensional) electron gas between Bi and Ag of ISOC layer 154 with high SOC, charge current I_c (i.e., output charge current Icharge (OUT)) is generated. In some

embodiments, the interface surface alloy 103 of BiAg2/PbAg2 of ISOC layer 154 comprises of a high density 2D electron gas with high Rashba SOC. The spin orbit mechanism responsible for spin-to-charge conversion is described by Rashba effect in 2D electron gases. In some embodiments, 2D electron gases are formed between Bi and Ag, and when current flows through the 2D electron gases, it becomes a 2D spin gas because as charge flows, electrons get spin polarized.

[0043] The Hamiltonian energy HR of the SOC electrons in the 2D electron gas corresponding to the Rashba effect is expressed as:

HR = c_R (k x ζ). σ . . . (3) where a_Ris the Rashba coefficient, 'k' is the operator of momentum of electrons, z is a unit vector perpendicular to the 2D electron gas, and σ is the operator of spin of electrons.

[0044] The spin polarized electrons with direction of polarization in-plane (in the xy- plane) experience an effective magnetic field dependent on the spin direction which is given as:

_B(_k = ^ ( z) . . . (4)

where ^_Bis the Bohr magneton.

[0045] This results in the generation of a charge current in interconnect 101b proportional to the spin current I_s from FM layer 106, in accordance with some embodiments. The spin orbit interaction at the Ag/Bi interface (i.e., the Inverse Rashba-Edelstein Effect (IREE)) produces a charge current I_c (i.e., Icharge (OUT)) in the horizontal direction which is expressed as:

I_c = ^ . . . (5)

where w_m is width of the magnet, and λ_ΙΚΕΕ is the IREE constant (with units of length) proportional to a_R .

[0046] The IREE effect produces spin-to-charge current conversion around 0.1 with existing materials at lOnm magnet width. For scaled nanomagnets (e.g., 5nm width) and exploratory SHE materials such as Bi2Se3, the spin-to-charge conversion efficiency can be between 1 and 2.5, in accordance with some embodiments. The net conversion of the input charge current I_d (i.e., Icharge (IN)) to magnetization dependent charge current (i.e., Icharge (OUT)) is:

j_± £½ _ ₍₆₎

w_m

where P is the spin polarization. The charge current I_c (i.e., Icharge (OUT)) then propagates through non-magnetic interconnect 101b. In some embodiments, charge current L (i.e., Icharge (OUT)) conducts through non-magnetic interconnect 101b without loss to another transducer (not shown).

[0047] In some embodiments, to write a logic state into ME SOC device 100, Icharge

(IN) is provided via interconnect 101a that charges ME capacitor 155. The capacitance stored in ME capacitor 155 is the stored logic state. In some embodiments, charge to spin conversion (i.e., converting Icharge (IN) to Is), is achieved via magnetoelectric effect in which the charge current produces a voltage on ME capacitor 155 leading to switching magnetization of FM layer 106. The direction of magnetization of FM layer 106 depends on the direction of Icharge (IN), in accordance with some embodiments.

[0048] In some embodiments, to read a logic state into ME SOC device 100, Isu_PPiy is provided to FM layer 106 which causes injected spin current I_s in FM layer 106 to convert to charge current Icharge (OUT). In some embodiments, spin to charge conversion is achieved via FREE (or bulk SHE) where a spin current injected from FM layer 106 produces charge current on interconnect 101b. In some embodiments, the direction of Icharge (OUT) determines the logic state stored in ME SOC device 100. For example, if Icharge (OUT) is flowing away from ME SOC device 100, then the state read is a logic state ' 1 ', and if Icharge (OUT) is flowing into ME SOC device 100, then logic state is 'Ο.'

[0049] Fig. IB illustrates a 3D view of a ME SOC Device 120, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. IB having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. So as not to obscure the embodiments of Fig. IB, differences between Fig. IB and Fig. 1A are described.

[0050] In some embodiments, instead of forming ME capacitor 155 below FM layer

106 such that interconnect 101a and interconnect 101b are on the same metal layer (e.g., metal 1 (Ml) layer) as shown in Fig. 1A, ME capacitor 155 is formed above FM layer 106 as shown in Fig. IB. In this case, interconnect 101a is at a different metal layer than interconnect 101b. For example, interconnect 101a is on metal 3 (M3) while interconnect 101b is on metal 1 (Ml). Operation wise, ME SOC Device 120 behaves similar to ME SOC Device 100. In some embodiments, interconnect 101a and interconnect 101b extend parallel to one another.

[0051] Fig. 2 illustrates a schematic of 2T memory bit-cell 200 with ME SOC Device

100/120, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 2 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0052] In some embodiments, 2T memory bit-cell 200 comprises read transistor, write transistor, bit-line (BL), source-line (SL), read word-line (WLr), write word-line (WL_W), and ME SOC Device 100/120 (i.e., one of ME SOC Device 100 or ME SOC Device 120). In the following embodiments, read and write transistors are described as n-type transistors MN1 and MN2, respectively. However, the embodiments are can also operate with p-type transistors for read and write transistors. In some embodiments, a combination of p-type and n-type transistors may be used. For example, the read transistor may be a p-type transistor while the write transistor may be an n-type transistor.

[0053] In some embodiments, the gate terminal of transistor MN1 is coupled to WL_r, the drain terminal (dl) of transistor MN1 is coupled to BL, and the source terminal (s i) of transistor MN1 is coupled to one edge of FM layer 106 which has ISOC layer 154. In some embodiments, transistor MN1 provides the function of reading by supplying I_SUppiy to FM layer 106 for determining the magnetization direction of FM layer 106 (and hence the value stored in ME capacitor 155).

[0054] In some embodiments, the gate terminal of transistor M 2 is coupled to WL_W, the drain terminal (d2) of transistor M 2 is coupled to BL, and the source terminal (s2) of transistor M 2 is coupled to another edge of FM layer 106 which has ME capacitor 155. In some embodiments, the source terminal of transistor M 2 is coupled to input conductor 101a. In some embodiments, transistor M 2 provides the function of writing to FM layer 106 via ME capacitor 155.

[0055] In some embodiments, output conductor 101b is coupled to SL. In some embodiments, the BL is formed on metal 4 (M4) while SL is formed in metal 0 (M0) such that ME SOC Device 100/120 is formed between M4 and M0. In other embodiments, the BL and SL may be formed on other metal layers. In some embodiments, the SL provides a virtual ground. In some embodiments, the virtual ground is generated by a sense amplifier (not shown) which is coupled to an end of the SL. For example, an operational amplifier (OPAMP) can create a virtual ground on the SL with a feedback charge integrating capacitor. The read and write functions of 2T memory bit-cell 200 are described with reference to Figs. 8-9.

[0056] Fig. 3 illustrates layout 300 of 2T memory bit-cell 200, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 3 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Fig. 3 illustrates one possible layout embodiment. However, other variations that achieve a small foot print (i.e., aspect ratio) as layout 300 are within the scope of the various embodiments. Layout 300 illustrates BL and SL being parallel to one another but on different metal layers. For example, BL is on M4 while SL is on M0. In some embodiments, the SL is formed on a metal layer 'n' and the BL is formed on metal layer "n+2," where 'n' is an integer. In some embodiments, the SL is formed on a metal layer 'n' and the BL is formed on metal layer "n+4," where 'n' is an integer.

[0057] In some embodiments, junction region 301 is provided to form transistors

MNl and MN2. The gate terminals of transistors MNl and MN2 extend perpendicular to the direction of BL and SL, in accordance with some embodiments. In some embodiments, region 302 between the gate terminals of transistors MNl and MN2 is used for forming ME SOC Device 100/120. As such, a compact layout topology is achieved for 2T memory bit- cell.

[0058] Figs. 4A-B illustrate schematic 400 and layout 420, respectively, of a row or column of 2T memory bit-cells with ME SOC Device 100/120, according to some embodiments of the disclosure. It is pointed out that those elements of Figs. 4A-B having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Schematic 400 shows 'N' 2T memory bit-cells sharing the same BL and SL. Each bit-cell has its corresponding transistors. For example, bit-cell[0] has transistors MN1 [0] and MN2[0] which are controllable by WL_r[0] and WL_w[0], respectively. Likewise, bit-cell[N] has transistors MN1 [N] and MN2[N] which are controllable by WL_r[N] and WL_W[N], respectively.

[0059] The corresponding layout is shown in Fig. 4B. In some embodiments, junction region 421 provides region for transistors MN[0], MN[0], and MN[1]. The 2T bit- cell allows shared GCN since merely one of the transistors is on at a time. The word-lines extend perpendicular to BL and SL. For example, WLr[0] and WL_w[0] extend perpendicular to BL and SL. As such, two word-lines per bit-cell control the write and read operations independently. The arrayed cell area is given by 2P x 2M0 indicating a density

configuration, where 'P' is poly pitch.

[0060] Fig. 5A illustrates plot 500 showing magnetic hysteresis during operation of

2T memory bit-cell 200 with ME SOC Device 100/120, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 5A having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Here, x-axis is Input Current (in μΑ) and y-axis is normalized magnetization M_x of FM layer 106. As input Current (i.e., Lharge (IN)) changes, the magnetization M_x of FM layer 106 changes and for some values of Lharge (IN), Mx of FM layer 106 completely switches. As such, depending on the direction of Icharge (IN) on interconnect 101a, magnetization M_x of FM layer 106 changes.

[0061] Fig. 5B illustrates plot 520 showing output read-out current relative to an input current for 2T memory bit-cell 200 with ME SOC Device 100/120, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 5B having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0062] Here, x-axis is Input Current (in μΑ) on interconnect 101a and y-axis is

Output Current (in μΑ) on interconnect 101b. In some embodiments, the Output Current is proportional to the magnetization in the x-direction (i.e., M_x) and not in the 'y' or 'z' directions. The amplitude of the Output Current depends on the size of transistor MN1 (or the read transistor) and/or size of the read pulse on BL. Plot 520 shows that Output Current (i.e., Icharge (OUT)) is a large signal current which can be used to drive another stage and/or allow for simple read circuits. In some embodiments, the magnitude of the Output Current is programmable (e.g., by adjusting the size of the read transistor and/or adjusting the pulse width and/or height of the read pulse on the BL).

[0063] Fig. 6 illustrates a 3D magnetization plot 600 showing the operation of 2T memory bit-cell 200 with ME SOC Device 100/120, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 6 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Plot 600 shows two stable magnetization states 601 and 602 along the x-axis (i.e., m_x). The two states represent logic 0 and logic 1, respectively, which are achievable by changing the direction of the Input Current (Icharge (IN)), in accordance with some embodiments.

[0064] Fig. 7 illustrates plot 700 showing the comparison of transient operating speed of a memory formed using ME switching relative to a memory formed using Spin Torque Transfer (STT) based switching, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Fig. 7 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0065] Here, x-axis is Voltage (V) and y-axis is Average Switching Time (nS). Two sets of data are shown in plot 700— data resulting in waveform 701 and data resulting in waveform 702. Waveform 701 illustrates the average switching time of a FM using STT (with noise) while waveform 702 illustrates the average switching time of a FM using ME switching (with noise). The difference in the average switching times around 0. IV is illustrated by 703. Plot 700 illustrates that high switching speed is achievable with field-like switching using MS SOC 100/120. MS SOC 100/120 also generates a large signal output. As such, fast switching and large signal output is achieved by MS SOC 100/120 which is not achievable with similar dimensions using STT.

[0066] Figs. 8A-C illustrate flowchart 800 of a method for reading a logic state from

2T memory bit-cell 200, schematic 820, and layout 830 of 2T memory bit-cell 820 during read operation, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Figs. 8A-C having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0067] Although the blocks in the flowchart with reference to Fig. 8A are shown in a particular order, the order of the actions can be modified. Thus, the illustrated embodiments can be performed in a different order, and some actions/blocks may be performed in parallel. Some of the blocks and/or operations listed in Fig. 8A are optional in accordance with certain embodiments. The numbering of the blocks presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur.

Additionally, operations from the various flows may be utilized in a variety of combinations.

[0068] At block 801, the first transistor MN1 is turned on. As such transistor M 1 electrically couples to BL. Transistor M 1 is turned on by activating WL_r (i.e., setting WLr to a logic ' 1 '). This is illustrated by the gray arrows in schematic 820 and the gray gate electrode of layout 830. At block 802, the second transistor M 2 is turned off. As such transistor M 2 electrically de-couples from BL. Transistor M 2 is turned off by deactivating WLw (i.e., setting WL_W to a logic 'Ο').

[0069] At block 803, a read current is applied to FM layer 106 via the turned on transistor M 1 and through BL. In some embodiments, the read current is applied as a pulse having a pulse width and/or height which is large enough to convert spin current in FM layer 106 to charge current Lharge (OUT) on SL. In some embodiments, SL is coupled to ground during read operation. The current passing through the magnetic element is spin polarized due to the nature of transport across ISOC layer 154. As such, at block 804, the spin current that passes vertically through ISOC layer 154 is converted to charge current due to the inverse spin orbit coupling in the read stack (i.e., ISOC layer 154). [0070] At block 805, the charge current Icharge (OUT) is collected on SL. At block

806, a sense amplifier (not shown) determines the state stored in 2T memory bit-cell 820 according to the direction of the charge current. For example, if the direction of the charge current is away from the bit-cell then the logic stored is logic 'Ο,' otherwise the logic stored is logic Ί.' The direction of input charge current Icharge (IN) is shown by the arrow on BL in layout 830 of Fig. 8C. The input charge current enters the drain terminal dl of transistor MN1. The arrow on SL is originating from the source terminal si of transistor MN1. The direction of the output charge current Icharge (OUT) is illustrated by the arrow on SL.

[0071] In some embodiments, signal level for reading is adjusted by increasing the read signal level which allows for the bit-cell to operate at a high speed generating a large signal output. Stronger read performed by various embodiments does not produce a read disturb in bit-cell 200.

[0072] Figs. 9A-C illustrate flowchart 900 of a method for writing a logic state to 2T memory bit-cell 200, schematic 920 and layout 930 of the 2T memory bit-cell during write operation, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Figs. 9A-C having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0073] Although the blocks in the flowchart with reference to Fig. 9A are shown in a particular order, the order of the actions can be modified. Thus, the illustrated embodiments can be performed in a different order, and some actions/blocks may be performed in parallel. Some of the blocks and/or operations listed in Fig. 9A are optional in accordance with certain embodiments. The numbering of the blocks presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur.

[0074] At block 901, the first transistor MN1 is turned off. As such, transistor MN1 electrically de-couples from BL. Transistor MN1 is turned on by de-activating WL_r (i.e., setting WLr to a logic 'Ο'). At block 902, the second transistor MN2 is turned on. As such, transistor MN2 electrically couples to BL. Transistor MN2 is turned on by activating WL_W (i.e., setting WL_W to a logic ' 1 '). This is illustrated by the gray arrows in schematic 920 and the gray gate electrode of layout 930

[0075] At block 903, a voltage is applied across BL and SL. For example, a voltage of about lOOmV is applied to BL relative to SL. The applied voltage difference causes current to flow from BL through transistor MN2 to ME capacitor 155. At block 904, the current (i.e., Icharge (IN)) charges ME capacitor 155. This charged ME layer 105 causes FM layer 106 to switch according to the direction of the current through transistor MN2 as indicated by block 905. The direction of current through transistor MN2 depends on the differential voltage across BL and SL. The input charge current enters the drain terminal d2 of transistor MN2. The direction of input charge current Icharge (IN) is shown by the arrow on BL in layout 930 of Fig. 9C.

[0076] Fig. 10 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with 2T memory bit-cell 200 with ME SOC Device 100/120, according to some embodiments. It is pointed out that those elements of Fig. 10 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0077] Fig. 10 illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In some embodiments, computing device 1600 represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 1600.

[0078] In some embodiments, computing device 1600 includes first processor 1610 with 2T memory bit-cell 200 with ME SOC Device 100/120, according to some embodiments discussed. Other blocks of the computing device 1600 may also include 2T memory bit-cell 200 with ME SOC Device 100/120, according to some embodiments. The various embodiments of the present disclosure may also comprise a network interface within 1670 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

[0079] In some embodiments, processor 1610 (and/or processor 1690) can include one or more physical devices, such as microprocessors, application processors,

microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor 1610 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 1600 to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

[0080] In some embodiments, computing device 1600 includes audio subsystem

1620, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1600, or connected to the computing device 1600. In one embodiment, a user interacts with the computing device 1600 by providing audio commands that are received and processed by processor 1610.

[0081] In some embodiments, computing device 1600 comprises display subsystem

1630. Display subsystem 1630 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1600. Display subsystem 1630 includes display interface 1632, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface 1632 includes logic separate from processor 1610 to perform at least some processing related to the display. In one embodiment, display subsystem 1630 includes a touch screen (or touch pad) device that provides both output and input to a user.

[0082] In some embodiments, computing device 1600 comprises I/O controller 1640.

I/O controller 1640 represents hardware devices and software components related to interaction with a user. I/O controller 1640 is operable to manage hardware that is part of audio subsystem 1620 and/or display subsystem 1630. Additionally, I/O controller 1640 illustrates a connection point for additional devices that connect to computing device 1600 through which a user might interact with the system. For example, devices that can be attached to the computing device 1600 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

[0083] As mentioned above, I/O controller 1640 can interact with audio subsystem

1620 and/or display subsystem 1630. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1600. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 1630 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 1640. There can also be additional buttons or switches on the computing device 1600 to provide I/O functions managed by I/O controller 1640.

[0084] In some embodiments, I/O controller 1640 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 1600. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

[0085] In some embodiments, computing device 1600 includes power management

1650 that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 1660 includes memory devices for storing information in computing device 1600. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 1660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1600.

[0086] Elements of embodiments are also provided as a machine-readable medium

(e.g., memory 1660) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein). The machine-readable medium (e.g., memory 1660) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer- executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

[0087] In some embodiments, computing device 1600 comprises connectivity 1670.

Connectivity 1670 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1600 to communicate with external devices. The computing device 1600 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices. [0088] Connectivity 1670 can include multiple different types of connectivity. To generalize, the computing device 1600 is illustrated with cellular connectivity 1672 and wireless connectivity 1674. Cellular connectivity 1672 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 1674 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

[0089] In some embodiments, computing device 1600 comprises peripheral connections 1680. Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 1600 could both be a peripheral device ("to" 1682) to other computing devices, as well as have peripheral devices ("from" 1684) connected to it. The computing device 1600 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 1600. Additionally, a docking connector can allow computing device 1600 to connect to certain peripherals that allow the computing device 1600 to control content output, for example, to audiovisual or other systems.

[0090] In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 1600 can make peripheral connections 1680 via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

[0091] Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

[0092] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0093] While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

[0094] In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

[0095] The following examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

[0096] For example, an apparatus is provided which comprises: a first transistor; a second transistor having a first terminal coupled to a first terminal of the first transistor; a first conductor coupled to a second terminal of the second transistor; a magnetoelectric (ME) layer coupled to the first conductor; and a ferromagnetic (FM) layer coupled to the ME layer and to a second terminal of the first transistor. In some embodiments, the apparatus comprises: an inverse spin orbit coupling (ISOC) layer coupled to the FM layer.

[0097] In some embodiments, the ISOC layer comprises a stack of: an interface layer which is coupled directly or indirectly to the FM layer; and a bulk layer coupled to the interface layer and a second conductor. In some embodiments, the interface layer is formed of at least one of: Ag, Cu, Al, or their alloys. In some embodiments, the bulk layer is formed of at least one of: Bi and Ag; Bi and Au; Bi and Cu; Pb and Ag; Pb and Au; β-Ta; β-W, Pt; Bi2Te3, or elements from 5d series, 4d series, or their alloys with 3d series.

[0098] In some embodiments, the interface layer is operable to provide interface spin orbit effect via inverse Rashba-Edelstein (IREE) for spin to charge conversion. In some embodiments, the bulk layer is operable to provide bulk material spin orbit effect via inverse spin Hall effect (ISHE) for spin to charge conversion. In some embodiments, the apparatus comprises: a bit-line (BL) coupled to the first terminals of the first and second transistors. In some embodiments, the apparatus comprises a source-line (SL) coupled to the ISOC layer. In some embodiments, the SL is formed on a metal layer 'n' and the BL is formed on metal layer "n+2," where 'n' is an integer.

[0099] In some embodiments, the SL is formed on a metal layer 'n' and the BL is formed on metal layer "n+4," where 'n' is an integer. In some embodiments, the apparatus comprises a first word-line (WL) coupled to a gate terminal of the first transistor. In some embodiments, the first WL is a read WL which is operable to turn on the first transistor during a read operation. In some embodiments, the apparatus comprises a second WL coupled to a gate terminal of the second transistor.

[00100] In some embodiments, the second WL is a write WL which is operable to turn on the second transistor during a write operation. In some embodiments, the first transistor is operable to drive stronger current than the second transistor. In some embodiments, the first transistor has an adjustable size. In some embodiments, the FM layer is formed of one of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, or a combination of them. In some embodiments, the ME layer is formed of one of: Bismuth Iron Oxide (BFO); Chromia (Cr_xO_y); or multiphase multi-ferroic material. In some embodiments, the ISOC layer comprises a bulk layer coupled to the FM layer and a second conductor. In some embodiments, the bulk layer is formed of at least one of: Bi and Ag; Bi and Au; Bi and Cu; Pb and Ag; Pb and Au; β-Ta; β- W, Pt; or Bi₂Te₃. [00101] In another example, a system is provided which comprises: a processor core; a memory coupled to the processor core, the memory having an apparatus according to the apparatus described above; and a wireless interface for allowing the processor to

communicate with another device.

[00102] In another example, a method for reading a logic state stored in a bit-cell having first and second transistors is provided. In some embodiments, the method comprises: turning on a first transistor by activating a word-line (WL), the first transistor having a first terminal coupled to a bit-line (BL); turning off a second transistor coupled to the BL;

applying read current through the BL, wherein the read current to pass through the turned on first transistor and to spin polarize a ferromagnetic (FM) layer coupled to a second terminal of the first transistor, and wherein the FM layer is coupled to a ME layer which is operable to set magnetization direction of the FM layer; converting a spin current from the spin polarized FM layer to a charge current; and collecting the charge current via a source-line (SL), wherein the charge current has a direction according to the magnetization direction set in the FM layer.

[00103] In some embodiments, the method comprises adjusting signal strength of the read current to increase read speed and the charge current. In some embodiments, converting the spin current from the spin polarized FM layer to the charge current comprises: providing an inverse Rashba-Edelstein effect (IREE) for spin to charge conversion; and providing an inverse spin Hall effect (ISHE) for spin to charge conversion. In some embodiments, wherein applying the read current through the BL comprises: applying the read current vertically through the FM layer and a stack of an inverse spin orbit coupling (ISOC) layer, wherein the stack of the ISOC layer comprises: an interface layer which is coupled to the FM layer; and a bulk layer coupled to the interface layer and the SL. In some embodiments, the method comprises determining a logic state stored in the bit-cell according to the direction of the charge current.

[00104] In another example, a method for writing a logic state stored in a bit-cell having first and second transistors is provided. In some embodiments, the method comprises: turning off the first transistor having a first terminal coupled to a bit-line (BL); turning on the second transistor by activating a word-line (WL), the second transistor having a first terminal coupled to the BL; and applying a voltage across the BL relative to a source-line (SL), the applied voltage to cause a write current to pass through the turned on second transistor, wherein a second terminal of the second transistor is coupled to a magnetoelectric (ME) layer which is operable to switch magnetization of a ferromagnetic (FM) layer coupled to the ME layer.

[00105] In some embodiments, the method comprises storing a logic state in the bit- cell by controlling a direction of the write current. In some embodiments, the method storing the logic state comprises charging the ME layer according to the write current, and wherein the charged ME layer is to switch the magnetization of the FM layer.

[00106] In another example, an apparatus for reading a logic state stored in a bit-cell having first and second transistors is provided. In some embodiments, the apparatus comprises: means for turning on a first transistor by activating a word-line (WL), the first transistor having a first terminal coupled to a bit-line (BL); means for turning off a second transistor coupled to the BL; means for applying read current through the BL, wherein the read current to pass through the turned on first transistor and to spin polarize a ferromagnetic (FM) layer coupled to a second terminal of the first transistor, and wherein the FM layer is coupled to a ME layer which is operable to set magnetization direction of the FM layer; means for converting a spin current from the spin polarized FM layer to a charge current; and means for collecting the charge current via a source-line (SL), wherein the charge current has a direction according to the magnetization direction set in the FM layer.

[00107] In some embodiments, the apparatus comprises means for adjusting signal strength of the read current to increase read speed and the charge current. In some embodiments, the means for converting the spin current from the spin polarized FM layer to the charge current comprises: means for providing an inverse Rashba-Edelstein effect (IREE) for spin to charge conversion; and means for providing an inverse spin Hall effect (ISHE) for spin to charge conversion. In some embodiments, the means for applying the read current through the BL comprises: means for applying the read current vertically through the FM layer and a stack of an inverse spin orbit coupling (ISOC) layer, wherein the stack of the ISOC layer comprises: an interface layer which is coupled to the FM layer; and a bulk layer coupled to the interface layer and the SL. In some embodiments, the apparatus means for determining a logic state stored in the bit-cell according to the direction of the charge current.

[00108] In another example, a system is provided which comprises: a processor core; a memory coupled to the processor core, the memory having an apparatus according to the apparatus described above; and a wireless interface for allowing the processor to

communicate with another device. [00109] In another example, an apparatus for writing a logic state stored in a bit-cell having first and second transistors is provided. In some embodiments, the apparatus comprises: means for turning off the first transistor having a first terminal coupled to a bit- line (BL); means for turning on the second transistor by activating a word-line (WL), the second transistor having a first terminal coupled to the BL; and means for applying a voltage across the BL relative to a source-line (SL), the applied voltage to cause a write current to pass through the turned on second transistor, wherein a second terminal of the second transistor is coupled to a magnetoelectric (ME) layer which is operable to switch

magnetization of a ferromagnetic (FM) layer coupled to the ME layer. In some

embodiments, the apparatus comprises means for storing a logic state in the bit-cell by controlling a direction of the write current. In some embodiments, the means for storing the logic state comprises charging the ME layer according to the write current, and wherein the charged ME layer is to switch the magnetization of the FM layer.

[00110] In another example, a system is provided which comprises: a processor core; a memory coupled to the processor core, the memory having an apparatus according to the apparatus described above; and a wireless interface for allowing the processor to

communicate with another device.

[00111] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

CLAIMS We claim:

1 . An apparatus comprising:

a first transistor;

a second transistor having a first terminal coupled to a first terminal of the first transistor;

a first conductor coupled to a second terminal of the second transistor;

a magnetoelectric (ME) layer coupled to the first conductor; and a ferromagnetic (FM) layer coupled to the ME layer and to a second terminal of the first transistor.

2. The apparatus of claim 1 comprises an inverse spin orbit coupling (ISOC) layer

coupled to the FM layer.

3. The apparatus of claim 2, wherein the ISOC layer comprises a stack of:

an interface layer which is coupled directly or indirectly to the FM layer; and a bulk layer coupled to the interface layer and a second conductor.

4. The apparatus of claim 3, wherein the interface layer is formed of at least one of: Ag, Cu, Al, or their alloys.

5. The apparatus of claim 3, wherein the bulk layer is formed of at least one of: Bi and Ag; Bi and Au; Bi and Cu; Pb and Ag; Pb and Au; β-Ta; β-W, Pt; Bi2Te3, or elements from 5d series, 4d series, or their alloys with 3d series.

The apparatus of claim 3, wherein the interface layer is operable to provide interface spin orbit effect via inverse Rashba-Edelstein (IREE) for spin to charge conversion.

The apparatus of claim 3, wherein the bulk layer is operable to provide bulk material spin orbit effect via inverse spin Hall effect (ISHE) for spin to charge conversion.

8. The apparatus of claim 2 comprises a bit-line (BL) coupled to the first terminals of the first and second transistors.

9. The apparatus of claim 8 comprises a source-line (SL) coupled to the ISOC layer.

10. The apparatus of claim 9, wherein the SL is formed on a metal layer 'n' and the BL is formed on metal layer "n+2," where 'n' is an integer.

1 1. The apparatus of claim 9, wherein the SL is formed on a metal layer 'n' and the BL is formed on metal layer "n+4," where 'n' is an integer.

12. The apparatus of claim 8 comprises a first word-line (WL) coupled to a gate terminal of the first transistor.

13. The apparatus of claim 12, wherein the first WL is a read WL which is operable to turn on the first transistor during a read operation.

14. The apparatus of claim 12 comprises a second WL coupled to a gate terminal of the second transistor.

15. The apparatus of claim 14, wherein the second WL is a write WL which is operable to turn on the second transistor during a write operation.

16. The apparatus of claim 1, wherein the first transistor is operable to drive stronger current than the second transistor.

17. The apparatus of claim 1, wherein the first transistor has an adjustable size.

18. The apparatus of claim 1, wherein the FM layer is formed of one of: a Heusler alloy, Co, Fe, i, Gd, B, Ge, Ga, or a combination of them.

19. The apparatus of claim 1, wherein the ME layer is formed of one of: Bismuth Iron Oxide (BFO); Chromia (Cr_xO_y); or multi-phase multi-ferroic material.

20. The apparatus of claim 2, wherein the ISOC layer comprises a bulk layer coupled to the FM layer and a second conductor.

21. The apparatus of claim 20, wherein the bulk layer is formed of at least one of: Bi and Ag; Bi and Au; Bi and Cu; Pb and Ag; Pb and Au; β-Ta; β-W, Pt; or Bi₂Te₃.

22. A system comprising:

a processor core;

a memory coupled to the processor core, the memory having an apparatus according to any one of apparatus claims 1 to 21 ; and

a wireless interface for allowing the processor to communicate with another device.

23. A method for reading a logic state stored in a bit-cell having first and second

transistors, the method comprising:

turning on a first transistor by activating a word-line (WL), the first transistor having a first terminal coupled to a bit-line (BL);

turning off a second transistor coupled to the BL;

applying read current through the BL, wherein the read current to pass through the turned on first transistor and to spin polarize a ferromagnetic (FM) layer coupled to a second terminal of the first transistor, and wherein the FM layer is coupled to a ME layer which is operable to set magnetization direction of the FM layer;

converting a spin current from the spin polarized FM layer to a charge current; and

collecting the charge current via a source-line (SL), wherein the charge current has a direction according to the magnetization direction set in the FM layer.

24. The method of claim 23 comprises adjusting signal strength of the read current to increase read speed and the charge current.

25. The method of claim 23, wherein converting the spin current from the spin polarized FM layer to the charge current comprises: providing an inverse Rashba-Edelstein effect (FREE) for spin to charge conversion; and

providing an inverse spin Hall effect (ISHE) for spin to charge conversion.

26. The method of claim 23, wherein applying the read current through the BL comprises:

applying the read current vertically through the FM layer and a stack of an inverse spin orbit coupling (ISOC) layer, wherein the stack of the ISOC layer comprises:

an interface layer which is coupled to the FM layer; and

a bulk layer coupled to the interface layer and the SL.

27. The method of claim 23 comprises determining a logic state stored in the bit-cell according to the direction of the charge current.

28. A method for writing a logic state stored in a bit-cell having first and second

transistors, the method comprising:

turning off the first transistor having a first terminal coupled to a bit-line (BL); turning on the second transistor by activating a word-line (WL), the second transistor having a first terminal coupled to the BL; and

applying a voltage across the BL relative to a source-line (SL), the applied voltage to cause a write current to pass through the turned on second transistor, wherein a second terminal of the second transistor is coupled to a magnetoelectric (ME) layer which is operable to switch magnetization of a ferromagnetic (FM) layer coupled to the ME layer.

29. The method of claim 28 comprises storing a logic state in the bit-cell by controlling a direction of the write current.

30. The method of claim 29, wherein storing the logic state comprises charging the ME layer according to the write current, and wherein the charged ME layer is to switch the magnetization of the FM layer.