WO2017034563A1

WO2017034563A1 - Dual pulse spin hall memory with perpendicular magnetic elements

Info

Publication number: WO2017034563A1
Application number: PCT/US2015/047055
Authority: WO
Inventors: Sasikanth Manipatruni; Cyrille Dray; Dmitri E. Nikonov; Yih Wang; Anurag Chaudhry; Ian A. Young
Original assignee: Intel IP Corporation
Priority date: 2015-08-26
Filing date: 2015-08-26
Publication date: 2017-03-02

Abstract

Described is an apparatus which comprises: a magnetic junction device including a fixed magnetic layer and a free magnetic layer with perpendicular magnetization anisotropy (PMA); a spin orbit coupling (SOC) layer coupled to the free magnetic layer with PMA; a first driver to drive a first in-plane pulse of charge current across the SOC layer; and a write assist driver to drive a pulse of charge current through the magnetic junction.

Description

DUAL PULSE SPIN HALL MEMORY WITH PERPENDICULAR MAGNETIC

ELEMENTS

BACKGROUND

[0001] Spintronics is the study of intrinsic spin of the electron and its associated magnetic moment in solid-state devices. Spintronic logic are integrated circuit devices that use a physical variable of magnetization or spin as a computation variable. Such variables can be non-volatile (i.e., preserving a computation state when a power to an integrated circuit is switched off). Non- volatile logic can improve the power and computational efficiency by allowing architects to put a processor to un-powered sleep states more often with less energy. Existing spintronic logic generally suffer from high energy and relatively long switching times.

[0002] For example, large write current (e.g., greater than ΙΟΟμΑ) and voltage (e.g., greater than 0.7V) are needed to switch a magnet (i.e., to write data to the magnet) in Magnetic Tunnel Junctions (MTJs). Existing Magnetic Random Access Memory (MRAM) based on MTJs also suffer from high write error rates (WERs) or low speed switching. For example, to achieve lower WERs, switching time is slowed down which degrades the performance of the MRAM. MTJ based MRAMs also suffer from reliability issues due to tunneling current in the tunneling dielectric of the MTJs.

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

[0004] Fig. 1A illustrates a typical material stack for Spin Hall Effect (SHE) in-plane

Magnetic Tunneling Junction (MTJ) device.

[0005] Fig. IB illustrates a magnetization plot showing in-plane magnetization switching due to spin current from SHE.

[0006] Fig. 1C illustrates a top view of the MTJ device of Fig. 1A.

[0007] Fig. 2A illustrates a Perpendicular Magnetization Anisotropy (PMA) compatible Spin Orbit Torque (SOT) MTJ (SOT-PMA-MTJ) device, according to some embodiments. [0008] Fig. 2B illustrates a cross-sectional view of the layer providing SOT to PMA based magnet, according to some embodiments of the disclosure.

[0009] Fig. 2C illustrates a top view of the SOT-PMA-MTJ device, according to some embodiments of the disclosure.

[0010] Fig. 2D illustrates a magnetization plot showing magnetization switching due to current from SHE using the SOT-PMA-MTJ device, according to some embodiments of the disclosure.

[0011] Fig. 2E illustrates a flowchart of a method for enhancing switching speed using the SOT-PMA-MTJ device, according to some embodiments of the disclosure.

[0012] Fig. 3 illustrates a dual source-line bit-cell formed using the SOT-PMA-MTJ device, according to some embodiments of the disclosure.

[0013] Fig. 4 illustrates a plot showing voltage and electrode resistance scaling to ensure constant resistance write operation.

[0014] Fig. 5A illustrates a plot showing write time distribution for traditional Spin

Transfer Torque (STT) PMA-MTJ (STT-PMA-MTJ) device.

[0015] Fig. 5B illustrates a plot showing write error rate for traditional the STT PMA-

MTJ.

[0016] Fig. 6A illustrates a plot showing write time distribution for SOT-PMA-MTJ device, according to some embodiments of the disclosure.

[0017] Fig. 6B illustrates a plot showing write error rate for SOT-PMA-MTJ device, according to some embodiments of the disclosure.

[0018] Fig. 7 illustrates a plot comparing switching error rates for non-volatile operation of SOT-PMA-MTJ with STT-PMA-MTJ, according to some embodiments of the disclosure.

[0019] Fig. 8 illustrates a plot showing switching operation of SOT-PMA-MTJ, according to some embodiments of the disclosure.

[0020] Fig. 9 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with SOT-PMA-MTJ and associating pulsing scheme, according to some

embodiments.

DETAILED DESCRIPTION

[0021] Anisotropy generally refers to a material property which is directionally dependent. Anisotropy for a magnet can come from the shape of the magnet and/or from the magnetic anisotropy of the magnetic material due to crystalline anisotropy or interface anisotropy in multi-layered stacks. For in-plane magnets, shape anisotropy is determined by the shape of the magnet. Magnets tend to align along the long axis of the shape. For example, an in-plane magnet which is a rectangular shaped magnet has its magnets aligning along the length of the rectangular shape.

[0022] An in-plane magnet shows shape anisotropy that primarily aligns along the length of the magnet. Materials with high magnetic anisotropy Hk (also referred to as the magnetic field) are materials with material properties that are highly directionally dependent. For in-plane magnets, magnetic field Hk produces limited anisotropy (e.g., 500-600 Oersted (Oe)). However, in-plane magnets work well for magneto-electric switching and with material exhibiting spin Hall effect (SHE). Conversely, magnets with Perpendicular Magnetic Anisotropy (PMA) have a higher magnetic field Hk (i.e., higher magnetic anisotropy) than in-plane magnets, and the anisotropy of the PMA magnet does not have a strong correlation with its shape. As such, PMA magnets can be square or round shaped (as opposed to rectangular shaped in-plane magnets) and can achieve faster switching with lower currents than in-plane magnets.

[0023] PMA, where the magnetization of the magnetic elements of a Magnetic

Random Access Memory (MRAM) is perpendicular to the plane of the wafer, has some benefits over spin transfer torque (STT) MRAM. The benefits of PMA are because of symmetric shape of the magnetic elements to ease the lithography/patterning, and access to higher magnetic anisotropy (Hk) which lowers critical currents and increases the speed of switching. Spin orbit torque (SOT) based switching has its own advantages. For example, SOT effect results in reduced write voltage for an MRAM bit-cell, reduced maximum voltages across a tunnel junction to improve reliability, and higher spin injection efficiency due to SHE enhancement.

[0024] Fig. 1A illustrates a typical material stack 100 for SHE in-plane Magnetic

Tunneling Junction (MTJ) device. SHE material converts charge current Iw (or write current) to spin current Is. Stack 100 forms a three terminal memory cell with SHE induced write mechanism and MTJ based read-out. Stack 100 comprises MTJ 121, SHE Interconnect or write electrode 122, and non-magnetic metal(s) 123a/b. In one example, MTJ 121 comprises stacked ferromagnetic layer with a tunneling dielectric and another ferromagnetic layer. One or both ends along the horizontal direction of SHE Interconnect 122 is formed of nonmagnetic metals 123a/b (e.g., Cu). In this example, the magnetizations of the two ferromagnetic layers are in-plane with reference to a wafer on which the device is formed (e.g., in x-y direction).

[0025] A wide combination of materials can be used for material stacking of MTJ

121. For example, the stack of materials include: Co_xFe_yB_z, MgO, Co_xFe_yB_z, Ru, Co_xFe_yB_z, IrMn, Ru, Ta, and Ru, where 'x,' 'y,' and 'z' are fractions of elements in the alloys. Other materials may also be used to form MTJ 121. MTJ 121 stack comprises free magnetic layer, MgO tunneling oxide, a fixed magnetic layer which is a combination of CoFe/Ru/CoFe layers referred to as Synthetic Anti-Ferromagnet (SAF) - based, and an Anti-Ferromagnet (AFM) layer. The SAF layer has the property, that the magnetizations in the two CoFe layers are opposite, and allows for cancelling the dipole fields around the free magnetic layer such that a stray dipole field will not control the free magnetic layer.

[0026] SHE Interconnect 122 (or the write electrode) is made of one or more of β-

Tantalum (β-Ta), Ta, β-Tungsten (β-W), W, Pt, Copper (Cu) doped with elements such as Iridium, Bismuth and any of the elements of 3d, 4d, 5d and 4f, 5 f periodic groups in the Periodic Table which may exhibit high spin orbit coupling. SHE Interconnect 122 transitions into high conductivity non-magnetic metal(s) 123a/b to reduce the resistance of SHE

Interconnect 122. The non-magnetic metal(s) 123a/b are formed from one or more of: Cu, Co, a-Ta, Al, CuSi, or NiSi.

[0027] In this example, the applied current I_w is converted into spin current by SHE

Interconnect 122. The spin current has a vector direction (i.e., current transport direction) orthogonal to the applied current I_w. This spin current exerts torque on the in-plane magnets of the ferromagnetic layer coupled to SHE Interconnect 122. As such, the torque switches the direction of magnetization of the in-plane free magnetic layer and thus changes the resistance of MTJ 121. To read out the state of MTJ 121, a sensing mechanism is used to sense the resistance change. The conversion of charge current to spin current is described with reference to Fig. 1C.

[0028] Fig. IB illustrates magnetization plot 120 showing in-plane magnetization switching (i.e., switching in the x-y plane) due to spin current from SHE. The

magnetization switching in this example is along the x and y directions, and not in the z- direction.

[0029] Fig. 1C illustrates top view 130 of the stack of Fig. 1A. It is pointed out that those elements of Fig. 1C having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Top view 130 shows that the in-plane magnet (having length L) is oriented along the width W_m of SHE Interconnect 122 for appropriate spin injection.

[0030] The in-plane magnetic cell is written by applying a charge current I_w (also referred to as I_c) via SHE Interconnect 122. The direction of the magnetic writing (in the free magnet layer) is decided by the direction of the applied charge current. Positive currents (i.e., currents flowing in the +y direction) produce a spin injection current with transport direction (along the +z direction) and spins pointing to the +x direction. The injected spin current in- turn produces spin torque to align the in-plane free magnet (coupled to SHE Interconnect 122) in the +x or -x direction. The injected spin current I_s generated by a charge current I_c in the write electrode is given by:

T_s = P_SHE (w, t, X_sf, 9_SHE) (z x T_c) . . . (1) where, the vector of spin current l_s = 7_†— /j, is the difference of currents with spin along and opposite to the spin direction, z is the unit vector perpendicular to the interface, P_SHE is the spin Hall injection efficiency which is the ratio of magnitude of transverse spin current to lateral charge current, w is the width of the magnet, t is the thickness of SHE Interconnect 122, X_Sf is the spin flip length in SHE Interconnect 122, 9_SHE is the spin Hall angle for SHE Interconnect 122 to free ferromagnetic layer interface. The injected spin angular momentum responsible for the spin torque given by:

[0031] The spin to charge conversion described with reference to Figs. 1A-C is based on TMR (Tunnel Magnetoresistance) effect which is highly limited in the signal strength generated. The charge current I_c (or I_w) applied to SHE Interconnect 122 is a lateral current (i.e., current that flows in the direction of the shape of SHE Interconnect 122) and generates spin current L with a transport direction orthogonal to the direction of the lateral charge current I_c.

[0032] As mentioned above, magnets with PMA have a higher magnetic field Hk than in-plane magnets, and the anisotropy of the PMA magnet does not have a strong correlation with its shape. As such, PMA magnets can be square or round shaped (as opposed to rectangular shaped in-plane magnets) and can achieve smaller size (or form factor) and faster switching with lower currents than in-plane magnets. However, magnets with PMA are not compatible with Spin Orbit Torque (SOT) because of the intrinsic in-plane nature of the spin current generated by SHE (e.g., the transport direction of spin current s is orthogonal to the direction of the lateral charge current /_c ). As such, replacing the in-plane magnets with PMA magnets for MTJ 121 may not work because of the intrinsic in-plane nature of the spin current generated by SHE Interconnect 122.

[0033] Various embodiments described here utilize spin orbit effect (or Spin Orbit

Torque (SOT)) for switching a PMA MTJ (referred to as SOT-PMA-MTJ). The operation is enabled by the use of dual switching pulses to enhance the speed of switching in the PMA magnets. In some embodiments, a pulsed excitation scheme is provided to obtain high switching speed and high reliability writing.

[0034] In some embodiments, a first in-plane pulse of charge current is sent across a write electrode formed with SOT material. For example, a charge current in a pulsed form is sent along the +y axis (i.e., the direction of the length of the write electrode). In some embodiments, a second in-plane pulse of charge current is sent across the write electrode, where the second in-plane pulse has a plurality opposite to the polarity of charge current from the first pulse. For example, a charge current in a pulsed form is sent along the -y axis. In some embodiments, a third weak write assist pulse is send via the SOT-PMA-MTJ.

[0035] For example, the third weak write assist pulse is sent along the -z axis through

SOT-PMA-MTJ. The weak write assist pulse is approximately 0. IX to 0.5X of the PMA- MTJs' switching current. This pulse may be applied during the entire operation or at the end of the first two pulses, in accordance with some embodiments. One technical effect/benefit of the dual pulsed excitation scheme along the in-plane direction is that it strongly perturbs the magnetization of the PMA free layer allowing for fast switching. Other technical effects will be evident from the various figures and embodiments.

[0036] In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

[0037] Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

[0038] Throughout the specification, and in the claims, the term "connected" means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices. The term "circuit" or "module" may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0039] The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- 10% of a target value (unless specifically specified). Unless otherwise specified the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0040] For the purposes of the present disclosure, phrases "A and/or B" and "A or B" mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0041] For purposes of the embodiments, the transistors in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include drain, source, gate, and bulk terminals. The transistors and/or the MOS transistor derivatives also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon Transistors, ferroelectric FET (FeFETs), or other devices implementing transistor functionality like carbon nanotubes or spintronic devices. MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here. A TFET device, on the other hand, has asymmetric Source and Drain terminals. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors— BJT PNP/NPN, BiCMOS, CMOS, eFET, etc., may be used without departing from the scope of the disclosure. The term "MN" indicates an n-type transistor (e.g., NMOS, NPN BJT, etc.) and the term "MP" indicates a p-type transistor (e.g., PMOS, PNP BJT, etc.).

[0042] Fig. 2A illustrates a PMA compatible SOT MTJ device 200 (also referred to as the SOT-PMA-MTJ 200), according to some embodiments. It is pointed out that those elements of Fig. 2A having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. So as not to obscure the embodiments, Fig. 2A is described with reference to Fig. 1 A. While the embodiment of Fig. 2A (and other embodiments in the disclosure) are described with reference to an MTJ, where the layer separating the two magnets is a tunneling dielectric, the embodiments are applicable to spin valves too. In a spin valve, the layer separating the two magnets is a metal layer. As such, the term magnetic junction is used to describe both MTJ and spin valve.

[0043] In some embodiments, SOT-PMA-MTJ 200 comprises a perpendicular MTJ

(pMTJ) 201 having PMA free magnet 202a, PMA fixed magnet 202b, and PMA SAF 203; SHE layer (or write electrode) 204, first driver 205, second driver 206, and write assist driver 207. In some embodiments, pMTJ 201 comprises PMA free magnet 202a and PMA fixed magnet 202b separated by tunneling dielectric (e.g., MgO). In some embodiments, the PMA of magnets 202a/b can be obtained via interface anisotropy and/or magnetic crystalline anisotropy.

[0044] In some embodiments, PMA free magnet 202a comprises multiple thin layers of metal and/or oxide to provide PMA to FM layer 202. In some embodiments, the multiple thin layers can be layers of Cobalt and Platinum (i.e., Co/Pt), for example. Other examples of the multiple thin layers include: Co and Pd; Co and Ni; MgO, CoFeB, Ta, CoFeB, and MgO; MgO, CoFeB, W, CoFeB, and MgO; MgO, CoFeB, V, CoFeB, and MgO; MgO, CoFeB, Mo, CoFeB, and MgO; Mn_xGa_y; Materials with L10 symmetry; or materials with tetragonal crystal structure. In some embodiments, PMA free magnet 202a is formed of a single layer of one or more materials instead of a stack of layers. For example, PMA free magnet 202a is formed of a layer of MnGa, FePt, or TbCoFe.

[0045] In some embodiments, PMA magnets 202a/b are made from CFGG (i.e.,

Cobalt (Co), Iron (Fe), Germanium (Ge), or Gallium (Ga) or a combination of them). In some embodiments, PMA magnets 202a/b are formed from Heusler alloys. Heusler alloys are ferromagnetic metal alloys based on a Heusler phase. Heusler phases are intermetallic with certain composition and face-centered cubic crystal structure. The ferromagnetic property of the Heusler alloys are a result of a double-exchange mechanism between neighboring magnetic ions. In some embodiments, PMA magnetic layer 202a is a Heusler alloy lattice matched to Ag (i.e., the Heusler alloy is engineered to have a lattice constant close (e.g., within 3%) to that of Ag) for either a direct lattice match or a lattice matching when the crystal structure is rotated by a specific angle (e.g., 45 degrees).

[0046] In some embodiments, Heusler alloys that form input and/or output magnets

202a and 203, respectively, are one of: Cu₂MnAl, Cu₂MnIn, Cu₂MnSn, Ni₂MnAl, Ni₂MnIn, Ni₂MnSn, Ni₂MnSb, Ni₂MnGa Co₂MnAl, Co₂MnSi, Co₂MnGa, Co₂MnGe, Pd₂MnAl, Pd₂MnIn, Pd₂MnSn, Pd₂MnSb, Co₂FeSi, Co₂FeAl, Fe₂VAl, Mn₂VGa, Co₂FeGe, MnGa, or MnGaRu.

[0047] In this embodiment, the magnetization direction of PMA magnet(s) 202a/b are perpendicular to the x-y plane. For example, magnetizations of PMA magnet 202a/b point out of the plane of the wafer along the z-direction. This is in contrast to the directions of magnetizations of the free and fixed magnets of MTJ 121 which are in-plane relative to the wafer on which they are formed.

[0048] The thickness of PMA magnets 202a/b may determine its magnetization direction, in accordance with some embodiments. For example, when the thickness of the PMA magnets 202a/b are below a certain threshold (depending on the material of the magnet), then the ferromagnetic layers exhibit magnetization direction which is perpendicular to the plane of the magnetic layer.

[0049] Other factors may also determine the direction of magnetization. For example, factors such as surface anisotropy (depending on the adjacent layers or a multi-layer composition of the ferromagnetic layer) and/or crystalline anisotropy (depending on stress and the crystal lattice structure modification such as FCC, BCC, or LlO-type of crystals, where L 10 is a type of crystal class which exhibits perpendicular magnetizations), can also determine the direction of magnetization.

[0050] In some embodiments, PMA fixed magnetic layer 202b is a combination of

CoFe/Ru/CoFe layers referred to as PMA SAF 203 and an Anti-Ferromagnet (AFM) layer. In some embodiments, PMA SAF 203 has the property, that the magnetizations in the two CoFe layers are opposite, and allows for cancelling the dipole fields around PMA free magnetic layer 202a such that a stray dipole field will not control the PMA free magnetic layer 202a. [0051] In some embodiments, write electrode 204 (also referred to as the spin orbit electrode) comprises a material that exhibits SHE. In some embodiments, write electrode 204 comprises the same material as SHE Interconnect 122. For example, write electrode 204 comprises of: β-Ta, Ta, β-W, W, Pt, Cu doped with elements such as Ir, Bi, and any of the elements of 3d, 4d, 5d and 4f, 5f periodic groups in the Periodic Table which may exhibit high spin orbit coupling. In some embodiments, write electrode 204 is formed of one or more of: Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg or their alloys with other transition elements. In some embodiments, doping with Bi and/or Pb is done to enhance the SHE effect.

[0052] In some embodiments, write electrode 204 comprises a field-like torque exerting/enhancing material. In some embodiments, field-like torque is achieved by engineering an interface of write electrode 204. In some embodiments, field-like torque generates Rashba effect, which is described with reference to Fig. 2B. Referring back to Fig. 2A, in some embodiments, this engineered interface couples to PMA free magnet layer 202a. In some embodiments, write electrode 204 provides two types of torques to PMA free magnet layer 202a— spin transfer torque (STT) and field-like torque (FLT). These two torques together switch magnetization of PMA free magnet layer 202a in an efficient and fast manner compared to STT based switching only in Fig. 1A. FLT originating from a spin current/spin phenomenon exerts a dynamic torque on the magnet, however, it has the phenomenology of a real magnetic field.

[0053] An embodiment of write electrode 204 is shown in Fig. 2B as cross-sectional view 220 of write electrode 204, according to some embodiments of the disclosure. Cross- sectional view 220 illustrates an interface region 221 and a bulk region 222. In some embodiments, the interface region 221 couples to PMA free magnet 202a. In some embodiments, bulk region 222 is coupled to a ground terminal.

[0054] In some embodiments, the field-like torque exerting/enhancing material comprises interface region 221 formed by Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, or their alloys with other transition elements. In some embodiments, interface region 221 is surface alloy which is one of: Bi-Ag, Antimony-Bismuth (Sb-Bi), Sb-Ag, or Lead-Nickel (Pb-Ni), etc. In some embodiments, bulk region 222 comprises a metal which is a noble metal (e.g., Ag, Cu, or Au) doped with other elements from group 4d and/or 5d of the Periodic Table. In some embodiments, one of the metals of the surface alloy is an alloy of heavy metal or of materials with high Spin Orbit Coupling (SOC) strength, where the SOC strength is proportional to the fourth power of the atomic number of the metal. [0055] In some embodiments, interface region 221 is a surface alloy of BiAg2/PbAg2 which comprises of a high density two dimensional (2D) electron gas with high Rashba SOC. The spin orbit mechanism responsible for spin-to-charge conversion is described by Rashba effect in 2D electron gases. In some embodiments, 2D electron gases are formed between Bi and Ag, and when current flows through the 2D electron gases, it becomes a 2D spin gas because as charge flows, electrons get polarized.

[0056] The Hamiltonian energy HR of the SOC electrons in the 2D electron gas corresponding to the Rashba effect is expressed as:

H_R = ^U _R <- X ^ζ). σ . . . (3)

where a_Ris the Rashba coefficient , 'k' is the operator of momentum of electrons, z is a unit vector perpendicular to the 2D electron gas, and σ is the operator of spin of electrons.

[0057] The spin polarized electrons with direction of polarization in-plane (in the xy- plane) experience an effective magnetic field dependent on the spin direction which is given as:

_B(_k = ^ ( z) . . . (4)

where ^_Bis the Bohr magneton.

[0058] This results in the generation of a charge current in the interconnect proportional to the spin current I_s. The spin orbit interaction at the Ag/Bi interface (i.e., the Inverse Rashba-Edelstein Effect (IREE)) produces a charge current l_c in the horizontal direction which is expressed as:

j = hSMMk . . . ₍₅₎

w_m

where w_m is width of the magnet, and _IREE is the IREE constant (with units of length) proportional to a_R.

[0059] The IREE effect produces spin-to-charge current conversion around 0.1 with existing materials at lOnm magnet width. For scaled nanomagnets (e.g., 5nm width) and exploratory SHE materials such as Bi2Se3, the spin-to-charge conversion efficiency can be between 1 and 2.5, in accordance with some embodiments. The net conversion of the drive charge current I_dto magnetization dependent charge current is:

j _± ¾ _{. . . (6)}

w_m

where P is the spin polarization.

[0060] Referring back to Fig. 2A, in some embodiments, write electrode 204 (i.e., the spin orbit electrode) is limited in length and width (i.e., limited in pitch size). Fig. 2C illustrates a top view 230 of SOT-PMA-MTJ 200 with the dimensions of write electrode 204, according to some embodiments of the disclosure. Here, the length and width of write electrode 204 Leiectrode and 'W, respectively, are selected for optimal SHE operation. In some embodiments, the dimensions of write electrode 204 ensures that the write resistance of write electrode 204 is maintained to be constant even as the magnetic element diameter is scaled (e.g., from 50 nm to 10 nm). For example, the ratio of the Leiectrode to width of the electrode is constant.

[0061] The criterion for choosing the length is set by a) layout and density of the magnetic memory, b) length to allow the spin hall/SOC material to operate as intended (i.e., overcome the edge effects, and/or c) electro-migration constraints. In general, the length of the SOC element is minimized to allow for lowest possible write resistance. Width of the electrode is chosen to cover the entire width of the magnet (i.e., dimensions perpendicular to the length of the SHE/SOC electrode).

[0062] Referring back to Fig. 2A, in some embodiments, first driver 205 is operable to send a first pulse of charge current across write electrode 204. For example, a first pulse of charge current is sent across +y direction. The spins inside the spin current are polarized along +x direction. The generated spin current (comprising of the +x polarized electrons) flows in the +z direction, in accordance with some embodiments. In some embodiments, first driver 205 comprises a transistor which is operable by word-line (WL). In this example, an n-type transistor MN1 is shown coupled to metal terminal 123a and a first source line 1 (SL1). In other embodiments, a p-type transistor can be used instead and/or in combination of the n-type transistor MN1. In some embodiments, the first pulse is provided over SL1 and sent to write electrode 204 via transistor MN1.

[0063] In some embodiments, second driver 206 is provided which is operable to send a second pulse of charge current across write electrode 204. The second pulse is of opposite polarity of charge current than the polarity of the first pulse, in accordance to some embodiments. For example, a second pulse of charge current is sent across the -y direction while the first pulse of charge current is send across +y direction. One reason for reversing the polarity of the pulses (i.e., second pulse polarity compared to the polarity of the first pulse) for writing opposite sign of magnetization to the magnetic element.

[0064] In some embodiments, second driver 206 comprises a transistor which is operable by WL. In this example, an n-type transistor MN2 is shown coupled to metal terminal 123b and a second source line 2 (SL2). In other embodiments, a p-type transistor can be used instead and/or in combination of the n-type transistor MN2. In some

embodiments, the second pulse is provided over SL2 and sent to write electrode 204 via transistor MN2. In some embodiments, the WL for controlling transistor MNl is separate than the WL for controlling transistor MN2. For example, transistor M l can be controlled independent of transistor MN2.

[0065] In some embodiments, a third weak assist pulse is sent via PMA-MTJ 201. In some embodiments, the weak write assist pulse is approximately 0. IX to 0.5X of the PMA MTJs' switching current. In some embodiments, the third weak assist pulse is applied during the entire operation (i.e., during application(s) of the first and/or second pulses). In some embodiments, the third weak pulse is provided at the end of the first pulse. In some embodiments, the third weak pulse is provided at the end of the first two pulses. In some embodiments, the third weak pulse is applied by write assist driver 207 that drives the weak pulse over Bitline (BL) to PMA-MTJ 201.

[0066] While the embodiments are described with reference to applying first, second, and third pulses by respective drivers, other writing schemes can also be employed for applying the pulses to write electrode 204 and through PMA-MTJ 201, in accordance with some embodiments. For example, one of the assist pulses can be shortened in length or may be eliminated according to the requirement of Write Error Rate (WER) requirements.

[0067] In some embodiments, to read from SOT-PMA-MTJ 200, charge current is passed through the BL into SOT-PMA-MTJ 200 and both transistors (MNl and/or MN2) are turned on by their respective WLs and currents flow through SL1 and SL2. In some embodiments, the currents through MTJ, and SL1 and SL2 are sensed by a sense amplifier with a programmable bias at BL to determine the effective resistance of SOT-PMA-MTJ 200. Depending on the effective resistance of SOT-PMA-MTJ 200, the logic state of the device is determined.

[0068] Fig. 2D illustrates magnetization plot 240 showing magnetization switching in

SOT-PMA-MTJ 201 (also referred to as pMTJ 201) due to spin current from write electrode 204, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 2D having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0069] In this example, a first pulse is provided in the +x direction. This pulse of charge current gives momentum to the switching activity so that the spin orbits towards the +x direction as shown by arrow 241. The switching activity in the +x direction is shown by magnetization m_x. In some embodiments, a weak pulse is applied, after applying the first pulse, to SOT-PMA-MTJ 201 in the direction of the MTJ stack (i.e., in -z direction) to switch the magnetization of PMA free magnetic layer 202a as shown by the dotted arrow 243. The switching activity in the -z direction is shown by magnetization m_z.

[0070] In some embodiments, after applying the first pulse, a second pulse of charge current of opposite polarity than the first pulse is applied. In this example, the second pulse is provided in the -x direction. The second pulse of charge current gives momentum to the switching activity so that the spin now orbits towards the -x direction as shown by the arrow 242. The switching activity in the -x direction is shown by magnetization -m_x. In some embodiments, the weak pulse is applied, after applying the first and second pulses, to SOT- PMA-MTJ 201 in the direction of the MTJ stack (i.e., in -z direction) to switch the magnetization of PMA free magnetic layer 202a as illustrated by the dotted arrow 243 of magnetization plot 240.

[0071] Fig. 2E illustrates flowchart 250 of a method for enhancing switching speed of a SOT PMA-MTJ device 200, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 2E having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0072] Although the blocks in the flowchart with reference to Fig. 2E are shown in a particular order, the order of the actions can be modified. Thus, the illustrated embodiments can be performed in a different order, and some actions/blocks may be performed in parallel. Some of the blocks and/or operations listed in Fig. 2E are optional in accordance with certain embodiments. The numbering of the blocks presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur.

Additionally, operations from the various flows may be utilized in a variety of combinations.

[0073] At block 251, a first in-plane pulse of charge current is applied across write electrode 204 formed with SHE material. In some embodiments, first driver 205 is operable to send a first pulse of charge current across write electrode 204. For example, a first pulse of charge current is sent across +y direction. In some embodiments, first driver 205 comprises a transistor which is operable by WL. In some embodiments, the first pulse is provided over SL1 and sent to write electrode 204 via transistor M 1.

[0074] At block 252, a second in-plane pulse of charge current of opposite charge current polarity is applied across write electrode 204. In some embodiments, second driver 206 is provided which is operable to send a second pulse of charge current across write electrode 204. The second pulse is of opposite polarity of charge current than the polarity of the first pulse, in accordance to some embodiments. For example, a second pulse of charge current is sent across -y direction while the first pulse of charge current is send across +y direction. One reason for reversing the polarity of the pulses (i.e., second pulse polarity compared to the polarity of the first pulse) for writing opposite sign of magnetization to the magnetic element. In some embodiments, the second pulse is provided over SL2 and sent to write electrode 204 via transistor MN2.

[0075] At block 253, a third weak pulse of PMA current is applied through PMA-

MTJ 201. In some embodiments, a third weak assist pulse is sent via PMA-MTJ 201. In some embodiments, the weak write assist pulse is approximately 0. IX to 0.5X of the PMA MTJs' switching current. In some embodiments, the third weak assist pulse is applied during blocks 251 and 252 (i.e., during application(s) of the first and/or second pulses). In some embodiments, the third weak pulse is provided at the end of the first pulse. For example, block 253 is performed after block 251. In one such embodiment, block 252 is not performed. In some embodiments, the third weak pulse is provided at the end of the first two pulses. In some embodiments, the third weak pulse is applied by write assist driver 207 that drives the weak pulse over BL to PMA-MTJ 201.

[0076] Fig. 3 illustrates a dual SL bit-cell 300 formed using SOT-PMA-MTJ device

200, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 3 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Fig. 3 is described with reference to Fig. 2A.

[0077] In some embodiments, bit-cell 300 comprises first access transistor MN1, second access transistor M 2, write electrode 204 made from SHE material, SL1, SL2, BL, and WL. The operations of WL and BL are well known. For example, to select a bit-cell from a memory array (for reading or writing), a WL is selected from a plurality of word-lines and then a BL is selected from a plurality of bit-lines. As such, the bit-cell of interest is selected. In some embodiments, SL1 provides the first pulse while SL2 provides the second pulse. In some embodiments, BL is used to provide the third pulse. The application of the first, second, and third pulses allows for switching the PMA magnets of pMTJ 201. By switching free magnetic layer 202a of pMTJ 201, resistance of pMTJ 201 changes which defines the data stored in pMTJ 201, in accordance with some embodiments. [0078] In some embodiments, during the read operation, transistors MN1 and MN2 are turned on. In some embodiments, during read operation both SL1 and SL2 are biased at ground. In some embodiments, during read operation BL is biased by the sense ampfilier and the current flowing through pMTJ 20 lis sensed to determine the logic state of pMTJ 201.

[0079] Fig. 4 illustrates plot 400 showing voltage and electrode resistance scaling of

SOT-PMA-MTJ compared to STT-PMA-MTJ. It is pointed out that those elements of Fig. 4 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Here, x-axis is MTJ Diameter and y-axis is Write Resistance in KOhm.

[0080] Plot 400 shows four curves. Plot 400 shows the scaling of the electrode resistance as a function of the critical dimension of the MTJ. Plot 400 shows that SOT-PMA- MTJ 200 shows a favorable scaling in write voltage and resistance compared to a STT-PMA- MTJ. The resistance of STT-PMA-MTJ (as shown by curves 401, 402, 403, and 404) increases as a function of reducing magnetic bit dimensions (L and W). The scaling of STT- PMA-MTJ is either parabolic (i.e., proportional to the 1/d²) or linear (i.e., proportional to 1/d) depending on the material and stack choices. In contrast, the resistance of write electrode 204 for SOT-PMA-MTJ 200 is constant and a low value to ensure high speed write operation as shown by flat lines 405 and 406.

[0081] Fig. 5A illustrates plot 500 showing write time distribution for traditional

STT-PMA-MTJ device for three different energy barrier levels— 75kT as distribution 501, 65kT as distribution 502, 50kT as distribution 503. Here, x-axis is Write Time Distribution and y-axis is Probability Density. Fig. 5B illustrates plot 520 showing write error rate (WER) for traditional the STT-PMA-MTJ. The WER is illustrated for three different energy barrier levels— 75kT as WER 521, 65kT as WER 522, and 50kT as WER 523. Here, x-axis is time and y-axis is WER.

[0082] Fig. 6A illustrates plot 600 showing write time distribution for SOT-PMA-

MTJ device 200 for four different energy barrier levels— 90kT as distribution 601, 75kT as distribution 602, 65kT as distribution 603, 50kT as distribution 604, according to some embodiments of the disclosure. Fig. 6B illustrates a plot showing WER for SOT-PMA-MTJ device 200, according to some embodiments of the disclosure. The WER is illustrated for four different energy barrier levels— 90kT as WER 621, 75kT as WER 622, 65kT as WER 623, and 50kT as WER 624. [0083] In some embodiments, the variations in write speed (i.e., write time distribution) of SOT-PMA-MTJ 200 (see Fig. 6A) compare favorably with the variations observed in traditional STT switching (see, Fig. 5A). The dynamic variations (i.e., variation in switching times to due to thermal transient noise) are shown in Fig. 5A and Fig. 6A.

[0084] The nature of the switching time variations shown by distributions 501, 502, and 503 of Fig. 5A exhibit a long tail for STT-PMA-MTJ (e.g., 75kT distribution 501 of STT-PMA-MTJ 200). In some embodiments, the nature of the switching time variations for SOT-PMA-MTJ 200 using the dual pulsing scheme is either a symmetric distribution function or a distribution with a shorter tail to the long time duration switching events (90kT, SOT-PMA-MTJ) as shown in Fig. 6A

[0085] The write error rates of the SOT-PMA-MTJ 200 (see Fig. 6B) when compared with traditional STT-PMA-MTJ (see Fig. 5B) show improvement. For example, 3 IX speed up is observed at 75kT barrier which corresponds to 2 hour life time at 110 degrees Celsius for SOT-PMA-MTJ 200 compared to traditional STT-PMA-MTJ. At 88kT barrier, the speed up is greater than 3 orders of magnitude (compare Fig. 6B with Fig. 5B) showing the potential for non-volatile embedded MRAM.

[0086] Fig. 7 illustrates plot 700 comparing switching error rates for non- volatile operation of SOT-PMA-MTJ 200 with traditional STT-PMA-MTJ, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 7 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0087] Here, x-axis is time and y-axis is WER. Plot 700 shows four waveforms.

Waveform 701 is the WER at 75kT thermal barrier for traditional STT-PMA-MTJ, waveform 702 is the WER at 75kT thermal barrier for SOT-PMA-MTJ 200, waveform 703 is the WER at 90kT thermal barrier for traditional STT-PMA-MTJ, and waveform 704 is the WER at 90kT thermal barrier for SOT-PMA-MTJ 200. Plot 700 shows a stark drop in WER for SOT- PMA-MTJ 200 compared to the WER for traditional STT-PMA-MTJ.

[0088] Fig. 8 illustrates plot 800 showing switching operation of operation of SOT-

PMA-MTJ 200, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 8 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Here, x-axis is time and y-axis is spin projections. The magnetization plot 240 corresponds to plot 800. Here, waveform 801 is the magnetization in the 'x' direction while waveforms 802 and 803 are magnetization in 'y' and 'z' directions, respectively.

[0089] Fig. 9 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with SOT-PMA-MTJ and associating pulsing scheme, according to some

embodiments. It is pointed out that those elements of Fig. 9 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0090] Fig. 9 illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In some embodiments, computing device 1600 represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 1600.

[0091] In some embodiments, computing device 1600 includes first processor 1610 with SOT-PMA-MTJ and associating pulsing scheme, according to some embodiments discussed. Other blocks of the computing device 1600 may also include SOT-PMA-MTJ and associating pulsing scheme, according to some embodiments. The various embodiments of the present disclosure may also comprise a network interface within 1670 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

[0092] In some embodiments, processor 1610 (and/or processor 1690) can include one or more physical devices, such as microprocessors, application processors,

microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor 1610 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 1600 to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

[0093] In some embodiments, computing device 1600 includes audio subsystem

1620, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1600, or connected to the computing device 1600. In one embodiment, a user interacts with the computing device 1600 by providing audio commands that are received and processed by processor 1610.

[0094] In some embodiments, computing device 1600 comprises display subsystem

1630. Display subsystem 1630 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1600. Display subsystem 1630 includes display interface 1632, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface 1632 includes logic separate from processor 1610 to perform at least some processing related to the display. In one embodiment, display subsystem 1630 includes a touch screen (or touch pad) device that provides both output and input to a user.

[0095] In some embodiments, computing device 1600 comprises I/O controller 1640.

I O controller 1640 represents hardware devices and software components related to interaction with a user. I/O controller 1640 is operable to manage hardware that is part of audio subsystem 1620 and/or display subsystem 1630. Additionally, I O controller 1640 illustrates a connection point for additional devices that connect to computing device 1600 through which a user might interact with the system. For example, devices that can be attached to the computing device 1600 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

[0096] As mentioned above, I/O controller 1640 can interact with audio subsystem

1620 and/or display subsystem 1630. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1600. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 1630 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 1640. There can also be additional buttons or switches on the computing device 1600 to provide I/O functions managed by I/O controller 1640.

[0097] In some embodiments, I/O controller 1640 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 1600. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

[0098] In some embodiments, computing device 1600 includes power management

1650 that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 1660 includes memory devices for storing information in computing device 1600. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 1660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1600.

[0099] Elements of embodiments are also provided as a machine-readable medium

(e.g., memory 1660) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein). The machine-readable medium (e.g., memory 1660) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer- executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

[00100] In some embodiments, computing device 1600 comprises connectivity 1670.

Connectivity 1670 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1600 to communicate with external devices. The computing device 1600 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

[00101] Connectivity 1670 can include multiple different types of connectivity. To generalize, the computing device 1600 is illustrated with cellular connectivity 1672 and wireless connectivity 1674. Cellular connectivity 1672 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 1674 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

[00102] In some embodiments, computing device 1600 comprises peripheral connections 1680. Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 1600 could both be a peripheral device ("to" 1682) to other computing devices, as well as have peripheral devices ("from" 1684) connected to it. The computing device 1600 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 1600. Additionally, a docking connector can allow computing device 1600 to connect to certain peripherals that allow the computing device 1600 to control content output, for example, to audiovisual or other systems.

[00103] In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 1600 can make peripheral connections 1680 via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

[00104] Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element. [00105] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[00106] While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

[00107] In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

[00108] The following examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

[00109] For example, an apparatus which comprises: a magnetic junction device including a fixed magnetic layer and a free magnetic layer with perpendicular magnetization anisotropy (PMA); a spin orbit coupling (SOC) layer coupled to the free magnetic layer with PMA; and a first driver to drive a first in-plane pulse of charge current across the SOC layer. In some embodiments, the apparatus further comprises a write assist driver to drive a pulse of charge current through the magnetic junction.

[00110] In some embodiments, the apparatus comprises a second driver to drive a second in-plane pulse of charge current across the SOC layer, wherein the second in-plane pulse of charge current has a polarity opposite of polarity of the first in-plane pulse of charge current. In some embodiments, the write assist driver is to drive the pulse of charge current after the second driver drives the second in-plane pulse current. In some embodiments, the pulse of charge current driven by the write assist driver is weaker in strength than the first and second in-plane pulses of charge currents.

[00111] In some embodiments, the second driver is operable to adjust a pulse width of the second in-plane pulse of charge current. In some embodiments, the first driver comprises a transistor controllable by a wordline (WL) and coupled to a first source-line (SL), and wherein the second driver comprises a transistor controllable by the WL and coupled to a second SL. In some embodiments, during a read operation, both the first and second drivers are turned on, both the first and second SLs are biased at ground, a BL coupled to the magnetic junction device is biased by a sense amplifier, and current flowing through the magnetic junction device is sensed to determine a logic state of the magnetic junction device.

[00112] In some embodiments, the pulse of charge current driven by the write assist driver is weaker in strength than the first in-plane pulse of charge current. In some embodiments, the first driver is operable to adjust pulse width of the first in-plane pulse of charge current. In some embodiments, the write assist driver is operable to adjust a pulse width of the pulse of charge current through the magnetic junction.

[00113] In some embodiments, the fixed and free magnet layers are formed of one of: a Heusler alloy, Co, Fe, Ge, Ga, or a combination of them. In some embodiments, the free magnetic layer with PMA is formed of a layer which is one of: MnGa, FePt, or TbCoFe. In some embodiments, the free magnetic layer with PMA is formed of a stack of layers, wherein each stack is one of: Co and Pt; Co and Pd; Co and Ni; MgO, CoFeB, Ta, CoFeB, and MgO; MgO, CoFeB, W, CoFeB, and MgO; MgO, CoFeB, V, CoFeB, and MgO; MgO, CoFeB, Mo, CoFeB, and MgO; Mn_xGa_y; Materials with L10 symmetry; or materials with tetragonal crystal structure. In some embodiments, the SOC layer is formed of one or more of: β-Ta, β- W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups.

[00114] In some embodiments, the first SOC layer comprises: an interface layer coupled to the fixed magnetic layer; and a bulk layer coupled to the interface layer. In some embodiments, the interface layer is formed of at least one of: Bi and Ag; Bi and Cu; or Pb and Ag. In some embodiments, the bulk layer is formed of at least one of: Ag, Cu, or Au. In some embodiments, the fixed and free magnetic layers are separated by a metal, and wherein the magnetic junction is a spin valve. [00115] In some embodiments, the fixed and free magnetic layers are separated by a tunneling dielectric, and wherein the magnetic junction is a magnetic tunneling junction (MTJ). In some embodiments, the tunneling dielectric is formed of MgO.

[00116] In another example, a system is provided which comprises: a processor core; a memory coupled to the processor core, the memory having an apparatus according to the apparatus described above; and a wireless interface for allowing the processor to

communicate with another device.

[00117] In another example, a method is provided which comprises: driving a first in- plane pulse of charge current across an Spin Orbit Coupling (SOC) layer; driving a second in- plane pulse of charge current across the SOC layer, wherein the second in-plane pulse of charge current has a polarity opposite of polarity of the first in-plane pulse of charge current; and driving a third pulse of charge current through a magnetic junction having a fixed magnet with perpendicular magnetization anisotropy (PMA), wherein the fixed magnet is coupled to the SOC layer. In some embodiments, the first pulse is applied before the second pulse, and wherein the second pulse is applied before the third pulse. In some embodiments, the third pulse of charge current is driven after the second in-plane pulse current is driven.

[00118] In some embodiments, the third pulse of charge current is weaker in strength than the first and second in-plane pulses of charge currents. In some embodiments, the first and second in-plane pulses of charge currents have substantially a same magnitude. In some embodiments, the SOC layer is formed of one or more of: β-Ta, β-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups. In some embodiments, the first SOC layer comprises: an interface layer coupled to the fixed magnet; and a bulk layer coupled to the interface layer. In some embodiments, the interface layer is formed of at least one of: Bi and Ag; Bi and Cu; or Pb and Ag. In some embodiments, the bulk layer is formed of at least one of: Ag, Cu, or Au.

[00119] In another example, a method is provided which comprises: driving a first in- plane pulse of charge current across an Spin Orbit Coupling (SOC) layer; and driving a second in-plane pulse of charge current across the SOC layer, wherein the second in-plane pulse of charge current has a polarity opposite of polarity of the first in-plane pulse of charge current, wherein a third pulse of charge current is present through a magnetic junction having a fixed magnet with perpendicular magnetization anisotropy (PMA), and wherein the fixed magnet is coupled to the SOC layer. In some embodiments, the first pulse is applied before the second pulse, and wherein the third pulse is present before the first pulse is driven. In some embodiments, the third pulse of charge current is provided via a current source.

[00120] In another example, an apparatus is provided which comprises: means for driving a first in-plane pulse of charge current across an Spin Orbit Coupling (SOC) layer; means for driving a second in-plane pulse of charge current across the SOC layer, wherein the second in-plane pulse of charge current has a polarity opposite of polarity of the first in- plane pulse of charge current; and means for driving a third pulse of charge current through a magnetic junction having a fixed magnet with perpendicular magnetization anisotropy (PMA), wherein the fixed magnet is coupled to the SOC layer.

[00121] In some embodiments, the first pulse is applied before the second pulse, and wherein the second pulse is applied before the third pulse. In some embodiments, the third pulse of charge current is driven after the second in-plane pulse current is driven. In some embodiments, the third pulse of charge current is weaker in strength than the first and second in-plane pulses of charge currents. In some embodiments, the first and second in-plane pulses of charge currents have substantially a same magnitude. In some embodiments, the SOC layer is formed of one or more of: β-Ta, β-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups. In some embodiments, the first SOC layer comprises: an interface layer coupled to the fixed magnet; and a bulk layer coupled to the interface layer. In some embodiments, the interface layer is formed of at least one of: Bi and Ag; Bi and Cu; or Pb and Ag. In some

embodiments, the bulk layer is formed of at least one of: Ag, Cu, or Au.

[00122] In another example, a system is provided which comprises: a processor core; a memory coupled to the processor core, the memory having an apparatus according to the apparatus described above; and a wireless interface for allowing the processor to

communicate with another device.

[00123] In another example, an apparatus is provided which comprises: means for driving a first in-plane pulse of charge current across an Spin Orbit Coupling (SOC) layer; and means for driving a second in-plane pulse of charge current across the SOC layer, wherein the second in-plane pulse of charge current has a polarity opposite of polarity of the first in-plane pulse of charge current, wherein a third pulse of charge current is present through a magnetic junction having a fixed magnet with perpendicular magnetization anisotropy (PMA), and wherein the fixed magnet is coupled to the SOC layer. In some embodiments, the first pulse is applied before the second pulse, and wherein the third pulse is present before the first pulse is driven. In some embodiments, the third pulse of charge current is provided via a current source.

[00124] In another example, a system is provided which comprises: a processor core; a memory coupled to the processor core, the memory having an apparatus according to the apparatus described above; and a wireless interface for allowing the processor to

communicate with another device.

[00125] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

CLAIMS We claim:

1. An apparatus comprising:

a magnetic junction device including a fixed magnetic layer and a free magnetic layer with perpendicular magnetization anisotropy (PMA);

a spin orbit coupling (SOC) layer coupled to the free magnetic layer with PMA; and a first driver to drive a first in-plane pulse of charge current across the SOC layer.

2. The apparatus of claim 1 further comprises a write assist driver to drive a pulse of charge current through the magnetic junction.

3. The apparatus of claim 2 comprises a second driver to drive a second in-plane pulse of charge current across the SOC layer, wherein the second in-plane pulse of charge current has a polarity opposite of polarity of the first in-plane pulse of charge current.

4. The apparatus of claim 3, wherein the write assist driver is to drive the pulse of charge current after the second driver drives the second in-plane pulse current.

5. The apparatus of claim 4, wherein the pulse of charge current driven by the write assist driver is weaker in strength than the first and second in-plane pulses of charge currents.

6. The apparatus of claim 3, wherein the second driver is operable to adjust a pulse width of the second in-plane pulse of charge current.

7. The apparatus of claim 3, wherein the first driver comprises a transistor controllable by a wordline (WL) and coupled to a first source-line (SL), and wherein the second driver comprises a transistor controllable by the WL and coupled to a second SL.

8. The apparatus of claim 7, wherein during a read operation, both the first and second drivers are turned on, both the first and second SLs are biased at ground, a BL coupled to the magnetic junction device is biased by a sense amplifier, and current flowing through the magnetic junction device is sensed to determine a logic state of the magnetic junction device.

9. The apparatus of claim 1 , wherein the pulse of charge current driven by the write assist driver is weaker in strength than the first in-plane pulse of charge current.

10. The apparatus of claim 1, wherein the first driver is operable to adjust pulse width of the first in-plane pulse of charge current.

1 1. The apparatus of claim 1, wherein the write assist driver is operable to adjust a pulse width of the pulse of charge current through the magnetic junction.

12. The apparatus of claim 1, wherein the fixed and free magnet layers are formed of one of: a Heusler alloy, Co, Fe, Ge, Ga, or a combination of them.

13. The apparatus of claim 1 , wherein the free magnetic layer with PMA is formed of a layer which is one of: MnGa, FePt, or TbCoFe.

14. The apparatus of claim 1, wherein the free magnetic layer with PMA is formed of a stack of layers, wherein each stack is one of:

Co and Pt;

Co and Pd;

Co and Ni;

MgO, CoFeB, Ta, CoFeB, and MgO;

MgO, CoFeB, W, CoFeB, and MgO;

MgO, CoFeB, V, CoFeB, and MgO;

MgO, CoFeB, Mo, CoFeB, and MgO;

Mn_xGa_y;

Materials with L10 symmetry; or

materials with tetragonal crystal structure.

15. The apparatus of claim 1, wherein the SOC layer is formed of one or more of: β-Ta, β-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups.

16. The apparatus of claim 1, wherein the first SOC layer comprises:

an interface layer coupled to the fixed magnetic layer; and

a bulk layer coupled to the interface layer.

17. The apparatus of claim 16, wherein the interface layer is formed of at least one of: Bi and Ag; Bi and Cu; or Pb and Ag.

18. The apparatus of claim 16, wherein the bulk layer is formed of at least one of: Ag, Cu, or Au.

19. The apparatus of claim 1, wherein the fixed and free magnetic layers are separated by a metal, and wherein the magnetic junction is a spin valve.

20. The apparatus of claim 1, wherein the fixed and free magnetic layers are separated by a tunneling dielectric, and wherein the magnetic junction is a magnetic tunneling junction (MTJ).

21. The apparatus of claim 20, wherein the tunneling dielectric is formed of MgO.

22. A system comprising:

a processor core;

a memory coupled to the processor core, the memory having an apparatus according to any one of apparatus claims 1 to 21 ; and

a wireless interface for allowing the processor to communicate with another device.

23. A method comprising:

driving a first in-plane pulse of charge current across an Spin Orbit Coupling (SOC) layer;

driving a second in-plane pulse of charge current across the SOC layer, wherein the second in-plane pulse of charge current has a polarity opposite of polarity of the first in- plane pulse of charge current; and driving a third pulse of charge current through a magnetic junction having a fixed magnet with perpendicular magnetization anisotropy (PMA), wherein the fixed magnet is coupled to the SOC layer.

24. The method of claim 23, wherein the first pulse is applied before the second pulse, and wherein the second pulse is applied before the third pulse.

25. The method of claim 23, wherein the third pulse of charge current is driven after the

second in-plane pulse current is driven.

26. The method of claim 23, wherein the third pulse of charge current is weaker in strength than the first and second in-plane pulses of charge currents.

27. The method of claim 23, wherein the first and second in-plane pulses of charge currents have substantially a same magnitude.

28. The method of claim 23, wherein the SOC layer is formed of one or more of: β-Ta, β-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups.

29. The method of claim 23, wherein the SOC layer comprises:

an interface layer coupled to the fixed magnet; and

a bulk layer coupled to the interface layer.

30. The method of claim 29, wherein the interface layer is formed of at least one of: Bi and Ag; Bi and Cu; or Pb and Ag.

31. The method of claim 29, wherein the bulk layer is formed of at least one of: Ag, Cu, or Au.

32. A method comprising:

driving a first in-plane pulse of charge current across an Spin Orbit Coupling (SOC) layer; and driving a second in-plane pulse of charge current across the SOC layer, wherein the second in-plane pulse of charge current has a polarity opposite of polarity of the first in- plane pulse of charge current, wherein a third pulse of charge current is present through a magnetic junction having a fixed magnet with perpendicular magnetization anisotropy (PMA), and wherein the fixed magnet is coupled to the SOC layer.

33. The method of claim 32, wherein the first pulse is applied before the second pulse, and wherein the third pulse is present before the first pulse is driven.

34. The method of claim 32, wherein the third pulse of charge current is provided via a current source.