WO2017044132A1

WO2017044132A1 - Ultra high magnetic anisotropy planar magnetization with spacer processing

Info

Publication number: WO2017044132A1
Application number: PCT/US2015/049812
Authority: WO
Inventors: Sasikanth Manipatruni; Dmitri E. Nikonov; Jasmeet S. Chawla; Anurag Chaudhry; Ian A. Young
Original assignee: Intel Corporation
Priority date: 2015-09-11
Filing date: 2015-09-11
Publication date: 2017-03-16
Also published as: TW201719946A

Abstract

Described is an apparatus which comprises: a substrate; and a magnet formed with one or more materials or a stack of materials with perpendicular magnetic anisotropy (PMA), wherein a magnetic moment of the magnet points mainly in a plane of the substrate. Described is a method comprising: defining a pitch grating pattern; transferring the pitch grating pattern into a backbone layer to form a patterned backbone layer; and depositing a layer of magnetic spacer, formed of one or more materials or a stack of materials of different metals or oxides, on the patterned backbone layer.

Description

ULTRA HIGH MAGNETIC ANISOTROPY PLANAR MAGNETIZATION WITH

SPACER PROCESSING

BACKGROUND

[0001] Spintronics is the study of intrinsic spin of the electron and its associated magnetic moment in solid-state devices. Spintronic logic are integrated circuit devices that use a physical variable of magnetization or spin as a computation variable. Such variables can be non-volatile (i.e., preserving a computation state when a power to an integrated circuit is switched off). Non- volatile logic can improve the power and computational efficiency by allowing architects to put a processor to un-powered sleep states more often with less energy. Spin logic and magnetic memory can enable a new class of logic devices and architectures for beyond CMOS (Complementary Metal Oxide Semiconductor) computing.

[0002] The traditional scaling path in magnetic memory and spin torque devices have assumed a natural progression from in-plane magnetization with associated shape anisotropy of devices towards out-of-plane magnetization enabled by material-related Perpendicular Magnetic Anisotropy (PMA) to achieve fast switching with low critical currents. However, in-plane magnetization remains an important building block for spin logic due to its suitability for magneto-electric switching to reduce critical switching energy. In-plane magnetization is also suitable for spin Hall effect switching. Despite the benefits of traditional in-plane magnetization, traditional in-plane magnetization suffer from scalability issues due to limited anisotropy that can be achieved, and from limitations to the aspect ratio of the magnet.

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

[0004] Fig. 1 illustrates an in-plane magnet with shape anisotropy.

[0005] Fig. 2 illustrates a Magnetic Tunnel Junction (MTJ) device with a

perpendicular magnetic layer formed with multiple magnetic layers.

[0006] Figs. 3A-D illustrate a fabrication process flow for forming side-wall deposited ultra-high anisotropy planar Perpendicular Magnetic Anisotropy (PMA) magnetization, according to some embodiments of the disclosure. [0007] Figs. 4A-F illustrate a fabrication process flow for forming pitch quartered side-wall deposited ultra-high anisotropy planar PMA magnetization, according to some embodiments of the disclosure.

[0008] Fig. 5 illustrates a plot showing spin torque switching with a magnetic stack or one or more materials comprising an ultra-high planar PMA magnet, according to some embodiments of the disclosure.

[0009] Fig. 6 illustrates magneto-electric switching with a stack or one or more materials comprising the ultra-high planar PMA magnet, according to some embodiments of the disclosure.

[0010] Fig. 7 illustrates a MTJ device with ultra-high planar PMA magnet coupled to a spin orbit coupling (SOC) layer, according to some embodiments of the disclosure.

[0011] Fig. 8 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with a device having ultra-high anisotropy planar PMA magnetization, according to some embodiments.

DETAILED DESCRIPTION

[0012] Anisotropy generally refers to a material property which is directionally dependent. Anisotropy for a magnet can come from the shape of the magnet and/or from the magnetic anisotropy of the magnetic material due to crystalline anisotropy or interface anisotropy in multi-layered stacks. Fig. 1 illustrates an in-plane magnet 101 with shape anisotropy. For in-plane magnets, shape anisotropy is determined by the shape of the magnet. Magnets tend to align along the long axis of the shape. In-plane magnet 101 is a rectangular shaped magnet. In-plane magnet 102 shows the pattern of magnetization direction which primarily aligns along the length of the magnet. Anisotropy is characterized by the associated effective magnetic field Hk. Materials with high magnetic field Hk are materials with material properties that are highly directionally dependent. For in-plane magnets, shape anisotropy typically corresponds to modest values of Hk, for example, 500- 600 Oersted (Oe).

[0013] However, in-plane magnets work well for magneto-electric switching and with material(s) exhibiting spin Hall effect (SHE). Conversely, out-of-plane magnets with Perpendicular Magnetic Anisotropy (PMA) have a higher magnetic field Hk than in-plane magnets, and the anisotropy of the PMA magnet does not have a strong correlation with its shape. As such, PMA magnets can be square or round shaped (as opposed to rectangular shaped in-plane magnets) and can achieve faster switching with lower currents than in-plane magnets.

[0014] Fig. 2 illustrates a Magnetic Tunnel Junction (MTJ) device 200 with a perpendicular magnetic layer formed with multiple magnetic layers. MJT device 200 includes fixed ferromagnet (FM) 201 (e.g., formed of CoFeB), a tunneling dielectric 202 (e.g., MgO), and a free perpendicular FM layer 203 formed from multiple layers, where tunneling dielectric 202 separates free FM layer 203 from fixed FM 201. The multiple thin layers of metal and/or oxide (shown as layers of patterns and clear regions) provide PMA to FM layer 203. As such, PMA in FM layer 203 is achieved by interface anisotropy as opposed to shape anisotropy.

[0015] The multiple thin layers can be layers of Cobalt and Platinum (i.e., Co/Pt), for example. Other examples of the multiple thin layers include: Co and Pd; Co and Ni; MgO, CoFeB, Ta, CoFeB, and MgO; MgO, CoFeB, W, CoFeB, and MgO; MgO, CoFeB, V, CoFeB, and MgO; MgO, CoFeB, Mo, CoFeB, MgO; Mn_xGa_y; Materials with L10 crystal symmetry; or materials with tetragonal crystal structure.

[0016] FM 203 with PMA, however, cannot be coupled with a layer of material(s) providing Inverse Spin Hall Effect (ISHE) or Inverse Rashba effect (IREE). ISHE/IREE provide an efficient mechanism for converting spin current to charge current. FM 203 with PMA is also not suitable for coupling with a layer of material(s) providing SHE (a type of spin orbit coupling effect). SHE provides an efficient mechanism for converting charge current to spin current. Since, FM 203 with PMA offers high switching using lower currents than in-plane magnets, FM 203 with PMA is not suitable for magneto-electric switching.

[0017] Various embodiments described here enable the use of multi-layer interfacial anisotropy for in-plane oriented magnets. In some embodiments, the in-plane anisotropy in PMA magnet is obtained by depositing the magnetic stack (formed of multiple layers of metals) on a sacrificial backbone (BB). In some embodiments, the sacrificial BB is removed to leave the sidewall comprising of the multi-layered/single-layered magnetic material. As such, a traditional interfacial PMA is achieved that produces an in-plane free magnet pointing in the plane of the wafer. For single layered PMA materials, the orientation of the crystal is such that the magnetization points in-plane of the wafer. In some embodiments, the density of the in-plane free magnets (i.e., magnetic elements per unit area) is increased by pitch quartering. [0018] The high magnetic anisotropy achieved in an in-plane free magnet with PMA magnetization of various embodiments, compared to Spin Torque Transfer (SST) devices, reduces critical current for a given magnetic thermal barrier. The PMA with an in-plane free magnet of the various embodiments improves stability for a given footprint (i.e., layout pitch of the magnet). PMA with an in-plane free magnet of the various embodiments is suitable for use with materials exhibiting SHE, ISHE, and magneto-electric switching effect. Other technical effects will be evident from the various embodiments and figures.

[0019] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

[0020] Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

[0021] Throughout the specification, and in the claims, the term "connected" means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices. The term "circuit" or "module" may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0022] The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- 10% of a target value (unless specifically specified). Unless otherwise specified the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0023] For the purposes of the present disclosure, phrases "A and/or B" and "A or B" mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0024] For purposes of the embodiments, the transistors in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include drain, source, gate, and bulk terminals. The transistors and/or the MOS transistor derivatives also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon Transistors, ferroelectric FET (FeFETs), or other devices implementing transistor functionality like carbon nanotubes or spintronic devices. MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here. A TFET device, on the other hand, has asymmetric Source and Drain terminals. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors— BJT PNP/NPN, BiCMOS, CMOS, eFET, etc., may be used without departing from the scope of the disclosure.

[0025] Figs. 3A-D illustrate fabrication process flow (300, 320, 330, and 340) for forming side-wall deposited ultra-high anisotropy planar PMA magnetization, according to some embodiments of the disclosure. It is pointed out that those elements of Figs. 3A-D having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0026] The following fabrication process or method is described with a starting stack of layer of spacer or backbone (BB) 301, Anti-reflective Coating (ARC) layer 302, BB layer 303, dielectric 304, and edge stop layer 305. Here, etch stop layer 305 is provided to ensure that the etching does not go beyond etch stop layer 305. In some embodiments, the flow starts by defining a 2x pitching grating pattern using spacer 301 or backbone 301 as shown in fabrication process step 300 of Fig. 3A.

[0027] In some embodiments, spacer 301 is any conformal material such as Atomic

Layer Deposition (ALD) layer or Chemical Vapor Deposition (CVD) layer. For example, ALD or CVD layers of Silicon oxide, metal oxides (Titanium oxide, Zr oxide, Al oxide), silicon nitride, and mixture of any of these can be used as spacer 301. In some embodiments, BB 301 is made of any sacrificial material that can be easily etched. For example, S1O2, carbon based material, etc. can be used as BB 301. In some embodiments, immersion lithography process is used to define the 2x pitching grating pattern.

[0028] The grating pattern (or BB 301 pattern) is then transferred into BB 303 by removing ARC 302 and then etching BB 303 to form pattern BB 321, in accordance with some embodiments. For example, directed plasma etch process may be used to transfer grating pattern 301 into BB 303. This process is illustrated by fabrication process step 320 of Fig. 3B, in accordance with some embodiments. ARC 302 can be made of any suitable known ARC material.

[0029] In some embodiments, magnetic spacer 331 is deposited over BB pattern 321 as shown by fabrication process step 330 in Fig. 3C. In some embodiments, magnetic spacer 331 is formed of multiple layers of different metals (e.g., a stack) such as multi-layer 203 described with reference to Fig. 2. In some embodiments, the magnetic spacer is formed from a single layer. For example, a layer of MnGa can be used as the magnetic spacer.

[0030] Referring back to Fig. 3C, magnetic spacer 331 is "wrapped" around from three sides on BB pattern 321 such that sidewalls, perpendicular to dielectric 304, are formed coupled to the vertical walls of BB pattern 321, in accordance with some embodiments. In some embodiments, magnetic spacer 321 which is parallel to the planar surface of dielectric 304 (i.e., the planar surface of dielectric 304 that has BB pattern 321 formed on top of it) form the out-of-plane PMA magnet. In some embodiments, magnetic spacer 321 in the form of sidewalls are in-plane PMA magnets.

[0031] In some embodiments, magnetic spacers 321 are selectively etched to remove all parallel portions of magnetic spacer 321 leaving behind magnetic spacer 341 in the form of sidewalls as shown by fabrication process step 340 of Fig. 3D. As such, magnetic spacers based grating 341 are yielded. These magnetic spacers based grating 341 have in-plane anisotropy with some residual magnetic anisotropy perpendicular to the wafer plane (i.e., perpendicular to the planar surface of dielectric 304). As such, in-plane PMA magnets 341 are formed.

[0032] Figs. 4A-F illustrate a fabrication process flow (400, 420, 430, 440, 450, and

460) for forming pitch quartered side-wall deposited ultra-high anisotropy planar PMA magnetization, according to some embodiments of the disclosure. It is pointed out that those elements of Figs. 4A-F having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0033] The following fabrication process or method is described with a starting stack of BB patterned layer 401 (or first BB layer), ARC layer 302, BB layer 303 (or second BB layer), dielectric 304, and edge stop layer 305. In some embodiments, the flow starts by defining a first BB (or BB 1) grating pattern 401 as shown in fabrication process step 400 of Fig. 4A. First BB patterned layer 401 is made of any sacrificial material that can be easily etched, in accordance with some embodiments. For example, SiC , carbon based material, etc. can be used as first BB patterned layer 401. In some embodiments, immersion lithography process is used to define the first BB patterned layer 401.

[0034] In some embodiments, spacer 421 is deposited over first BB patterned layer

401 as shown by fabricating process step 420 of Fig. 4B. In some embodiments, a nonmagnetic spacer 421 is deposited by any known methods over first BB patterned layer 401. In some embodiments, spacer 401 is any conformal material such as ALD layer or CVD layer. For example, ALD or CVD layers of Silicon oxide, metal oxides (Titanium oxide, Zr oxide, Al oxide), silicon nitride, and mixture of any of these can be used as spacer 401.

[0035] In some embodiments, spacer 431 is etched to form etched spacer 421 on either sides of first BB patterned layer 401 as illustrated by fabrication process step 430 of Fig. 4C. As such, first BB patterned layer 401 is etched and spacer 421 is selectively etched to form spacer pattern 431 which is a pitch-halved grating pattern.

[0036] In some embodiments, spacer pattern 431 is transferred to BB layer 303 to form BB pattern 441 as illustrated by processing step 440 of Fig. 4D. In some embodiments, a directed plasma etch process is used to transfer to BB layer 303 to form BB pattern 441. In some embodiments, plasma etch process is followed by removal of all materials selective to BB layer 303 and underlying hard mask (HM).

[0037] In some embodiments, magnetic spacer 451 is deposited over BB pattern 441 as shown by fabrication process step 450 in Fig. 4E. In some embodiments, magnetic spacer 451 is formed of multiple layers of different metals or oxides such as multi-layer 203 (or a stack) described with reference to Fig. 2. Referring back to Fig. 4E, in some embodiments, magnetic spacer 451 is formed from a single layer. For example, a layer of MnGa can be used as the magnetic spacer 451. In some embodiments, magnetic spacer 451 is "wrapped" around BB pattern 441 along three sides such that sidewalls, perpendicular to dielectric 304, are formed coupled to the vertical walls of BB pattern 441, in accordance with some embodiments. In some embodiments, magnetic spacer 451 which is parallel to the planar surface of dielectric 304 (i.e., the planar surface of dielectric 304 that has BB pattern 441 formed on top of it) form the out-of-plane PMA magnet. In some embodiments, magnetic spacer 451 in the form of sidewalls are in-plane PMA magnets.

[0038] In some embodiments, magnetic spacers 451 are selectively etched to remove all parallel portions of magnetic spacer 451 leaving behind magnetic spacer in the form of sidewalls. As such, magnetic spacers based grating 461 is yielded. These magnetic spacers based grating 461 have in-plane anisotropy with some residual magnetic anisotropy perpendicular to the wafer plane (i.e., perpendicular to the planar surface of dielectric 304), in accordance with some embodiments.

[0039] Fig. 5 illustrates plot 500 showing spin torque switching with a multi-layer magnetic stack (or one or more materials of a single stack) comprising an ultra-high planar PMA magnet, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 5 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Here, x-axis is write current (e.g., current to switch a FM) and y-axis is switching time.

[0040] Plot 500 shows data 501 for switching dynamics for an in-plane single layer

FM device based on shape anisotropy due to high aspect ratio. Data 502 for nominal planar PMA device and data 503 for optimized planar PMA devices are formed by fabricating processes described with reference to Figs. 3-4, in accordance with some embodiments. Referring back to Fig. 5, nominal planar device has magnetic saturation M_s typical of single layer PMA FM and moderate value of magnetic field Hk. Magnetic saturation M_s is generally the state reached when an increase in applied external magnetic field H cannot increase the magnetization of the material (i.e., total magnetic flux density B substantially levels off). Optimized planar PMA device has magnetic saturation M_s which is 4 times lower and magnetic field Hk which is 4 times higher.

[0041] In some embodiments, optimized PMA device (shown by data 503) shows improvement in switching speed at the same value of current (e.g., 3X improvement of ΙΟΟμΑ comparing to the high aspect ratio in-place data 501 in view of nominal planar PMA data 502). The optimized PMA device (i.e., in-plane anisotropy PMA device) of the various embodiments shows significant improvement in write-bit-error rate (WER) with the reduction in the scatter of the switching time. [0042] Fig. 6 illustrates magneto-electric switching with stack 601 comprising the ultra-high planar PMA magnet, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 6 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Here, x-axis is magnetic field in Oe and y-axis is switching speed (1/ns).

[0043] Stack 601 is a magneto-electric device with FM layer 601a coupled to ferroelectric (FE) layer 601b. In some embodiments, FM layer 601a is formed of the planar anisotropy PMA magnet such as those formed by processing flows described with reference to Figs. 3-4. Referring back to Fig. 6, when electric field E is applied to FE layer 601b, magnetization of FM 601a switches, where B_me is the magneto-electric field. In some embodiments, FM layer 601b is formed of at least one of: BaTi03 or PbTi03.

[0044] Plot 602 illustrates the switching speed of FM 601a which is formed of PMA magnet 203, while plot 603 shows the switching speed of FM 601a which is formed of in- plane PMA magnet of various embodiments. The magnetic switching from traditional PMA is slow (e.g., Ins) while the magnetic switching from in-plane PMA magnetization of various embodiments can be as low as 250ps (e.g., 4x faster).

[0045] Fig. 7 illustrates MTJ device 700 with ultra-high planar PMA magnet coupled to a spin orbit coupling (SOC) layer, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 7 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Here, axis is write current (e.g., current to switch a FM) and y-axis is switching time.

[0046] In some embodiments, the stack of layers having MTJ 700 is coupled to an electrode formed of Spin Hall Effect (SHE) material (which is an example of an SOC layer), where the SHE material converts charge current Iw (or write current) to spin current Is. Stack 700 forms a three terminal memory cell with SHE induced write mechanism and MTJ based read-out.

[0047] In some embodiments, stack 700 comprises MTJ 701, SHE Interconnect or write electrode 702, and non-magnetic metal(s) 703 a/b. In one example, MTJ 701 comprises stacked ferromagnetic layer with a tunneling dielectric and another ferromagnetic layer. One or both ends along the horizontal direction of SHE Interconnect 702 is formed of nonmagnetic metals 703 a/b. [0048] A wide combination of materials can be used for material stacking of MTJ

701. For example, the stack of materials include: Co_xFe_yB_z, MgO, Co_xFe_yB_z, Ru, Co_xFe_yB_z, IrMn, Ru, Ta, and Ru, where 'x,' 'y,' and 'z' are fractions of elements in the alloys. Other materials may also be used to form MTJ 701. MTJ 701 stack comprises free magnetic layer formed in-plane anisotropy PMA magnet, MgO tunneling oxide, and a fixed magnetic layer which is a combination of CoFe, Ru, and CoFe layers referred to as Synthetic Anti- Ferromagnet (SAF) - based, and an Anti-Ferromagnet (AFM) layer. The SAF layer has the property, that the magnetizations in the two CoFe layers are opposite, and allows for cancelling the dipole fields around the free magnetic layer such that a stray dipole field will not control the free magnetic layer.

[0049] In some embodiments, SHE Interconnect 702 (or the write electrode) is made of one or more of β-Tantalum (β-Ta), Ta, β-Tungsten (β-W), W, Pt, Copper (Cu) doped with elements such as Iridium, Bismuth and any of the elements of 3d, 4d, 5d and 4f, 5f periodic groups in the Periodic Table which may exhibit high spin orbit coupling. In some embodiments, SHE Interconnect 702 transitions into high conductivity non-magnetic metal(s) 703a/b to reduce the resistance of SHE Interconnect 702. The non-magnetic metal(s) 703a/b are formed from one or more of: Cu, Co, a-Ta, Al, CuSi, or NiSi.

[0050] In one case, the magnetization direction of the fixed magnetic layer is perpendicular relative to the magnetization direction of the free magnetic layer (i.e., magnetization directions of the free and fixed magnetic layers are not parallel, rather they are orthogonal). For example, magnetization direction of the free magnetic layer is in-plane but with PMA while the magnetization direction of the fixed magnetic layer is perpendicular to the plane.

[0051] In this example, the applied current I_w is converted into orthogonal spin current by SHE Interconnect 702. This spin current exerts torque on the free ultra-high planar PMA magnet layer and switches the direction of magnetization of the free ultra-high planar PMA magnet layer and thus changes the resistance of MTJ 701. However, to read out the state of MTJ 701, a sensing mechanism is needed to sense the resistance change, in accordance with some embodiments.

[0052] The magnetic cell is written by applying a charge current via SHE

Interconnect 702. The direction of the magnetic writing (in the free magnet layer) is decided by the direction of the applied charge current. Positive currents (i.e., currents flowing in the +y direction) produce a spin injection current with transport direction (along the +z direction) and spins pointing to the +x direction. The injected spin current in-turn produces spin torque to align the free magnet (coupled to the SHE material) in the +x or -x direction. The injected spin current I_s generated by a charge current l_c in the write electrode is given by:

T_s = P_SHE (w, t, X_sf, 9_SHE)(z x T_c) . . . (1) where, the vector of spin current l_s = 7_†— /_j, is the difference of currents with spin along and opposite to the spin direction, z is the unit vector perpendicular to the interface, P_SHE is the spin Hall injection efficiency which is the ratio of magnitude of transverse spin current to lateral charge current, w is the width of the magnet, t is the thickness of the SHE

Interconnect 702, X_Sf is the spin flip length in SHE Interconnect 702, 9_SHE is the spin Hall angle for SHE Interconnect 702 to free ferromagnetic layer interface. The injected spin angular momentum responsible for the spin torque given by:

[0053] In some embodiments, Spin Orbit Coupling (e.g., spin Hall effect) is used for transduction from both magnet state to current and back. Spin Orbit Coupling is more efficient switching mechanism for transduction from the magnetization direction to current and for switching magnetization. In some embodiments, charge current via a non-magnetic interconnect carries the signal between input and output magnets rather than spin-polarized current. In some embodiments, the sign of the charge current is determined by the direction of magnetization in the input magnet.

[0054] In some embodiments, spin-to-charge conversion is achieved via spin orbit interaction in metallic interfaces (i.e., using Inverse Rashba-Edelstein Effect, Inverse Spin Orbit Coupling (ISOC), and/or Inverse SHE (ISHE), where a spin current injected from an input magnet produces a charge current.

[0055] Table 1 summarizes transduction mechanisms for converting spin current to charge current and charge current to spin current for bulk materials and interfaces.

Table 1: Transduction mechanisms for Spin to Charge and Charge to Spin Conversion based on SOC.

[0056] In some embodiments, in-plane PMA magnet of the various embodiments is coupled to a spin orbit coupling (SOC) layer (e.g., a layer exhibiting SHE). In some embodiments, SOC layer 702 is a super-lattice stack which is functionally equivalent to a material which provides spin Hall effect. In some embodiments, super-lattice stack of SHE layer 702 comprises layers of metals, such as Copper (Cu), Silver (Ag), Gold (Au), and layers of a surface alloy, e.g. Bismuth (Bi) on Ag. In some embodiments, 'N' number of layers of surface alloy (e.g., interface layer) and metal (e.g., bulk layer) are stacked in alternating fashion, where 'N' is an integer, for form super-lattice stack 702. In one example, N=10 which is sufficient to convert input spin current to corresponding charge current with efficiency of one or higher. In other examples, other number of layers may be used to trade off conversion efficiency versus area of the stack.

[0057] In some embodiments, super-lattice of SHE layer 702 comprises an interface layer, (i.e., surface alloy) coupled to in-plane PMA magnet, and bulk layer (e.g., layer(s) of metal) coupled to the interface layer. In some embodiments, super-lattice of SHE layer 702 comprises an interface layer, (i.e., surface alloy) and bulk layer (e.g., layer(s) of metal) coupled to the interface layer.

[0058] In some embodiments, the surface alloy is one of: Bi-Ag, Antimony-Bismuth

(Sb-Bi), Sb-Ag, or Lead-Nickel (Pb-Ni), etc. In some embodiments, the metal of the bulk layer is a noble metal (e.g., Ag, Cu, and Au) doped with other elements for group 4d and/or 5d of the Periodic Table. In some embodiments, one of the metals of the surface alloy is an alloy of heavy metal or of materials with high SOC strength, where the SOC strength is directly proportional to the fourth power of the atomic number of the metal.

[0059] In some embodiments, all metal layers in the stack of SHE layer 702 are of the same type of metal. For example, all metal layers of the stack SHE layer 702 are formed of Ag. In other embodiments, different metal layers may be used in the same stack for the metal portion of the layers. For example, some metal layers of the stack of SHE layer 702 are formed of Ag and others are formed of Cu.

[0060] In some embodiments, an atomic structure of the stack of SHE layer 702 shows non-uniform patterns of Ag and Bi atoms of the surface alloy sandwiched between layers of Cu or other metals. Here, the crystals of Ag and Bi have lattice mismatch, (i.e., the distance between neighboring atoms of Ag and Bi is different). In some embodiments, the surface alloy (i.e., the interface layer) is formed with surface corrugation resulting from the lattice mismatch (i.e., the positions of Bi atoms are offset by varying distance from a plane parallel to a crystal plane of the underlying metal). The surface alloy is a structure not symmetric relative to the mirror inversion defined by a crystal plane. This inversion asymmetry leads to spin-orbit coupling in electrons near the surface (also referred to as the Rashba effect).

[0061] Here, sufficiently matched atomistic crystalline layers refer to matching of the lattice constant 'a' within a threshold level above which atoms exhibit dislocation which is harmful to the device (i.e., the number and character of dislocations lead to a significant (e.g., greater than 10%) probability of spin flip while an electron traverses the interface layer). For example, the threshold level is within 5% (i.e., threshold levels in the range of 0% to 5% of the relative difference of the lattice constants).

[0062] In some embodiments, the interface surface alloy of BiAg2/PbAg2 comprises of a high density two dimensional (2D) electron gas with high Rashba SOC. The spin orbit mechanism responsible for spin-to-charge conversion is described by Rashba effect in 2D electron gases. In some embodiments, 2D electron gases are formed between Bi and Ag, and when current flows through the 2D electron gases, it becomes a 2D spin gas because as charge flows, electrons get polarized.

[0063] The Hamiltonian energy HR of the SOC electrons in the 2D electron gas corresponding to the Rashba effect is expressed as:

H_R = _R(k x z). d . . . (3)

where i½is the Rashba coefficient , 'k' is the operator of momentum of electrons, z is a unit vector perpendicular to the 2D electron gas, and σ is the operator of spin of electrons.

[0064] The spin polarized electrons with direction of polarization in-plane (in the xy- plane) experience an effective magnetic field dependent on the spin direction which is given as:

B(k)= ^ (* x 2) . . . (4)

where ju_Bis the Bohr magneton.

[0065] This results in the generation of a charge current in the SHE layer 702 proportional to the spin current I_s. The spin orbit interaction at the Ag/Bi interface (i.e., the Inverse Rashba-Edelstein Effect (IREE)) produces a charge current l_c in the horizontal direction which is expressed as:

j₌ REE ₍₅₎

W_m

where w_m is width of the magnet, and λ_]ΚΕΕ is the IREE constant (with units of length) proportional to _R.

[0066] The IREE effect produces spin-to-charge current conversion around 0.1 with existing materials at lOnm magnet width. For scaled nanomagnets (e.g., 5nm width) and exploratory SHE materials such as Bi2Se3, the spin-to-charge conversion efficiency can be between 1 and 2.5, in accordance with some embodiments. The net conversion of the drive charge current I_dto magnetization dependent charge current is: w_m

where P is the spin polarization.

[0067] In some embodiments, SOC layer 702 is formed of one or more of: β-Ta, β-W,

W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups. In some embodiments, in-plane PMA magnet of various embodiments is coupled to an inverse spin orbit coupling layer (e.g., a layer exhibiting ISHE). In some embodiments, the layer exhibiting Inverse Spin Orbit Coupling comprises: an interface layer coupled to the in-plane anisotropic magnet; and a bulk layer coupled to the interface layer and another non-magnetic metal. In some embodiments, the interface layer is formed of at least one of: Bi and Ag; Bi and Cu; or Pb and Ag, and wherein the bulk layer is formed of at least one of: Ag, Cu, or Au.

[0068] Fig. 8 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with a device having ultra-high anisotropy planar PMA magnetization (e.g., that formed of by Figs. 3-4), according to some embodiments. It is pointed out that those elements of Fig. 8 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0069] Fig. 8 illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In some embodiments, computing device 1600 represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 1600.

[0070] In some embodiments, computing device 1600 includes first processor 1610 with a device having ultra-high anisotropy planar PMA magnetization, according to some embodiments discussed. Other blocks of the computing device 1600 may also include a device having ultra-high anisotropy planar PMA magnetization, according to some embodiments. The various embodiments of the present disclosure may also comprise a network interface within 1670 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant. [0071] In some embodiments, processor 1610 (and/or processor 1690) can include one or more physical devices, such as microprocessors, application processors,

microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor 1610 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 1600 to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

[0072] In some embodiments, computing device 1600 includes audio subsystem

1620, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1600, or connected to the computing device 1600. In one embodiment, a user interacts with the computing device 1600 by providing audio commands that are received and processed by processor 1610.

[0073] In some embodiments, computing device 1600 comprises display subsystem

1630. Display subsystem 1630 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1600. Display subsystem 1630 includes display interface 1632, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface 1632 includes logic separate from processor 1610 to perform at least some processing related to the display. In one embodiment, display subsystem 1630 includes a touch screen (or touch pad) device that provides both output and input to a user.

[0074] In some embodiments, computing device 1600 comprises I/O controller 1640.

I/O controller 1640 represents hardware devices and software components related to interaction with a user. I/O controller 1640 is operable to manage hardware that is part of audio subsystem 1620 and/or display subsystem 1630. Additionally, I/O controller 1640 illustrates a connection point for additional devices that connect to computing device 1600 through which a user might interact with the system. For example, devices that can be attached to the computing device 1600 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

[0075] As mentioned above, I O controller 1640 can interact with audio subsystem

1620 and/or display subsystem 1630. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1600. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 1630 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I O controller 1640. There can also be additional buttons or switches on the computing device 1600 to provide I/O functions managed by I/O controller 1640.

[0076] In some embodiments, I/O controller 1640 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 1600. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

[0077] In some embodiments, computing device 1600 includes power management

1650 that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 1660 includes memory devices for storing information in computing device 1600. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 1660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1600.

[0078] Elements of embodiments are also provided as a machine-readable medium

(e.g., memory 1660) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein). The machine-readable medium (e.g., memory 1660) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer- executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

[0079] In some embodiments, computing device 1600 comprises connectivity 1670.

Connectivity 1670 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1600 to communicate with external devices. The computing device 1600 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

[0080] Connectivity 1670 can include multiple different types of connectivity. To generalize, the computing device 1600 is illustrated with cellular connectivity 1672 and wireless connectivity 1674. Cellular connectivity 1672 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 1674 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

[0081] In some embodiments, computing device 1600 comprises peripheral connections 1680. Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 1600 could both be a peripheral device ("to" 1682) to other computing devices, as well as have peripheral devices ("from" 1684) connected to it. The computing device 1600 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 1600. Additionally, a docking connector can allow computing device 1600 to connect to certain peripherals that allow the computing device 1600 to control content output, for example, to audiovisual or other systems.

[0082] In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 1600 can make peripheral connections 1680 via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

[0083] Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

[0084] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0085] While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

[0086] In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

[0087] The following examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

[0088] For example, an apparatus is provided which comprises: a spin orbit coupling

(SOC) layer; and a free magnet with a planar perpendicular magnetic anisotropy (PMA) coupled to the SOC layer. In some embodiments, the wherein a magnetic moment of the free magnet points mainly in a plane of a substrate. In some embodiments, the SOC layer is formed of one or more of: β-Ta, β-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups.

[0089] In some embodiments, the free magnet is formed of a stack of materials, wherein the stack is at least one of: Co and Pt; Co and Pd; Co and Ni; MgO, CoFeB, Ta, CoFeB, and MgO; MgO, CoFeB, W, CoFeB, and MgO; MgO, CoFeB, V, CoFeB, and MgO; MgO, CoFeB, Mo, CoFeB, and MgO; Mn_xGa_y; Materials with L10 symmetry; or materials with tetragonal crystal structure. In some embodiments, the free magnet is formed of a single layer of one or more materials. In some embodiments, the single layer is formed of MnGa.

[0090] In another example, a system is provided which comprises: a memory; a processor coupled to the memory, the processor having an apparatus according to the apparatus described above; and a wireless device for allowing the processor to communicate with another device.

[0091] In another example, an apparatus is provided which comprises: a substrate; and a magnet formed with one or more materials or a stack of materials with perpendicular magnetic anisotropy (PMA), wherein a magnetic moment of the magnet points mainly in a plane of the substrate. In some embodiments, the stack of materials are at least one of: Co and Pt; Co and Pd; Co and Ni; MgO, CoFeB, Ta, CoFeB, and MgO; MgO, CoFeB, W, CoFeB, and MgO; MgO, CoFeB, V, CoFeB, and MgO; MgO, CoFeB, Mo, CoFeB, and MgO; Mn_xGa_y; Materials with L10 symmetry; or materials with tetragonal crystal structure.

[0092] In some embodiments, the one or more materials is a single layer of MnGa. In some embodiments, the apparatus comprises a ferroelectric layer coupled to the magnet to form a magneto-electric device. In some embodiments, the ferroelectric layer is formed of at least one of: BaTi03 or PbTi03. In some embodiments, the apparatus comprises a spin orbit coupling (SOC) layer, wherein the SOC layer is coupled to the magnet. In some embodiments, the SOC layer is formed of one or more of: β-Ta, β-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups. In some embodiments, the apparatus comprises an inverse SOC (ISOC) layer coupled to the magnet. In some embodiments, wherein the ISOC layer comprises: an interface layer coupled to the magnet; and a bulk layer coupled to the interface layer and another non-magnetic metal. In some embodiments, the interface layer is formed of at least one of: Bi and Ag; Bi and Cu; or Pb and Ag, and wherein the bulk layer is formed of at least one of: Ag, Cu, or Au.

[0093] In another example, a system is provided which comprises: a memory; a processor coupled to the memory, the processor having an apparatus according to the apparatus described above; and a wireless device for allowing the processor to communicate with another device.

[0094] In another example, a method is provided which comprises: defining a pitch grating pattern; transferring the pitch grating pattern into a backbone layer to form a patterned backbone layer; and depositing a layer of magnetic spacer, formed of one or more materials or a stack of materials of different metals or oxides, on the patterned backbone layer. In some embodiments, the method comprises: selectively etching the magnetic spacers such that the patterned backbone layer is etched to leave behind side walls of the patterned backbone layer, wherein the sidewalls are formed of the one or more materials or stack of materials of different metals or oxides.

[0095] In some embodiments, the stack of materials of different metals or oxides are at least one of: Co and Pt; Co and Pd; Co and Ni; MgO, CoFeB, Ta, CoFeB, and MgO; MgO, CoFeB, W, CoFeB, and MgO; MgO, CoFeB, V, CoFeB, and MgO; MgO, CoFeB, Mo, CoFeB, and MgO; Mn_xGa_y; Materials with L10 symmetry; or materials with tetragonal crystal structure. In some embodiments, the one or more materials is a single layer of MnGa.

[0096] In another example, a method comprises: defining a first backbone grating pattern; depositing a first spacer on the first backbone grating pattern such that the first spacer is on either sides of the first backbone grating pattern; selectively etching the first backbone grating pattern leaving behind sidewalls of the first spacer that were deposited on either sides of the first backbone grating pattern; transferring the selectively etched first backbone grating pattern to a second backbone layer to form a patterned second backbone layer; and depositing a layer of magnetic spacer, formed of one or more materials or a stack of materials of different metals or oxides, on the patterned second backbone layer. [0097] In some embodiments, the method comprises: selectively etching the layer of magnetic spacers such that the patterned second backbone layer is etched to leave behind side walls of the patterned second backbone layer, wherein the sidewalls are formed of the one or more materials or the stack of materials of different metals or oxides. In some embodiments, the stack of materials of different metals or oxides is at least one of: Co and Pt; Co and Pd; Co and Ni; MgO, CoFeB, Ta, CoFeB, and MgO; MgO, CoFeB, W, CoFeB, and MgO; MgO, CoFeB, V, CoFeB, and MgO; MgO, CoFeB, Mo, CoFeB, and MgO; Mn_xGa_y; Materials with L10 symmetry; or materials with tetragonal crystal structure.

[0098] In another example, an apparatus is provided which comprises: means for defining for a first backbone grating pattern; means for depositing for a first spacer on the first backbone grating pattern such that the first spacer is on either sides of the first backbone grating pattern; means for selectively etching the first backbone grating pattern leaving behind sidewalls of the first spacer that were deposited on either sides of the first backbone grating pattern; means for transferring the selectively etched first backbone grating pattern to a second backbone layer to form a patterned second backbone layer; and means for depositing a layer of magnetic spacer, formed of one or more materials or a stack of materials of different metals or oxides, on the patterned second backbone layer.

[0099] In some embodiments, the apparatus comprises: means for selectively etching the layer of magnetic spacers such that the patterned second backbone layer is etched to leave behind side walls of the patterned second backbone layer, wherein the sidewalls are formed of the one or more materials or the stack of materials of different metals or oxides. In some embodiments, the apparatus comprises: the stack of materials of different metals or oxides is at least one of: Co and Pt; Co and Pd; Co and Ni; MgO, CoFeB, Ta, CoFeB, and MgO; MgO, CoFeB, W, CoFeB, and MgO; MgO, CoFeB, V, CoFeB, and MgO; MgO, CoFeB, Mo, CoFeB, and MgO; Mn_xGa_y; Materials with L10 symmetry; or materials with tetragonal crystal structure.

[00100] In another example, a system is provided which comprises: a memory; a processor coupled to the memory, the processor having an apparatus according to the apparatus described above; and a wireless device for allowing the processor to communicate with another device.

[00101] In another example, an apparatus is provided which comprises: means for defining a pitch grating pattern; means for transferring the pitch grating pattern into a backbone layer to form a patterned backbone layer; and means for depositing a layer of magnetic spacer, formed of one or more materials or a stack of materials of different metals or oxides, on the patterned backbone layer. In some embodiments, the apparatus comprises: means for selectively etching the magnetic spacers such that the patterned backbone layer is etched to leave behind side walls of the patterned backbone layer, wherein the sidewalls are formed of the one or more materials or stack of materials of different metals or oxides. In some embodiments, the stack of materials of different metals or oxides are at least one of: Co and Pt; Co and Pd; Co and Ni; MgO, CoFeB, Ta, CoFeB, and MgO; MgO, CoFeB, W, CoFeB, and MgO; MgO, CoFeB, V, CoFeB, and MgO; MgO, CoFeB, Mo, CoFeB, and MgO; Mn_xGa_y; Materials with L10 symmetry; or materials with tetragonal crystal structure. In some embodiments, the one or more materials is a single layer of MnGa.

[00102] In another example, a system is provided which comprises: a memory; a processor coupled to the memory, the processor having an apparatus according to the apparatus described above; and a wireless device for allowing the processor to communicate with another device.

[00103] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

CLAIMS We claim:

1. An apparatus comprising:

a spin orbit coupling (SOC) layer; and

a free magnet with a planar perpendicular magnetic anisotropy (PMA) coupled to the SOC layer.

2. The apparatus of claim 1, wherein the wherein a magnetic moment of the free magnet points mainly in a plane of a substrate.

3. The apparatus of claim 1 , wherein the SOC layer is formed of one or more of: β-Ta, β-W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups.

4. The apparatus of claim 1, wherein the free magnet is formed of a stack of materials, wherein the stack is at least one of:

Co and Pt;

Co and Pd;

Co and Ni;

MgO, CoFeB, Ta, CoFeB, and MgO;

MgO, CoFeB, W, CoFeB, and MgO;

MgO, CoFeB, V, CoFeB, and MgO;

MgO, CoFeB, Mo, CoFeB, and MgO;

Mn_xGa_y;

Materials with L10 symmetry; or

materials with tetragonal crystal structure.

5. The apparatus of claim 1, wherein the free magnet is formed of a single layer of one or more materials.

6. The apparatus of claim 5, wherein the single layer is formed of MnGa.

7. An apparatus comprising: a substrate; and

a magnet formed with one or more materials or a stack of materials with perpendicular magnetic anisotropy (PMA), wherein a magnetic moment of the magnet points mainly in a plane of the substrate.

8. The apparatus of claim 7, wherein the stack of materials are at least one of:

Co and Pt;

Co and Pd;

Co and Ni;

MgO, CoFeB, Ta, CoFeB, and MgO;

MgO, CoFeB, W, CoFeB, and MgO;

MgO, CoFeB, V, CoFeB, and MgO;

MgO, CoFeB, Mo, CoFeB, and MgO;

Mn_xGa_y;

Materials with L10 symmetry; or

materials with tetragonal crystal structure.

9. The apparatus of claim 7, wherein the one or more materials is a single layer of MnGa.

10. The apparatus of claim 7 comprises a ferroelectric layer coupled to the magnet to form a magneto-electric device.

1 1. The apparatus of claim 10, wherein the ferroelectric layer is formed of at least one of:

BaTiOs or PbTiOs.

12. The apparatus of claim 7 comprises a spin orbit coupling (SOC) layer, wherein the SOC layer is coupled to the magnet.

13. The apparatus of claim 12, wherein the SOC layer is formed of one or more of: β-Ta, β- W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups.

14. The apparatus of claim 7 comprises an inverse SOC (ISOC) layer coupled to the magnet.

15. The apparatus of claim 14, wherein the ISOC layer comprises:

an interface layer coupled to the magnet; and

a bulk layer coupled to the interface layer and another non-magnetic metal.

16. The apparatus of claim 15, wherein the interface layer is formed of at least one of: Bi and Ag; Bi and Cu; or Pb and Ag, and wherein the bulk layer is formed of at least one of: Ag, Cu, or Au.

17. A method comprising:

defining a pitch grating pattern;

transferring the pitch grating pattern into a backbone layer to form a patterned backbone layer; and

depositing a layer of magnetic spacer, formed of one or more materials or a stack of materials of different metals or oxides, on the patterned backbone layer.

18. The method of claim 17 comprises:

selectively etching the magnetic spacers such that the patterned backbone layer is etched to leave behind side walls of the patterned backbone layer, wherein the sidewalls are formed of the one or more materials or stack of materials of different metals or oxides.

19. The method of claim 18, wherein the stack of materials of different metals or oxides are at least one of:

Co and Pt;

Co and Pd;

Co and Ni;

MgO, CoFeB, Ta, CoFeB, and MgO;

MgO, CoFeB, W, CoFeB, and MgO;

MgO, CoFeB, V, CoFeB, and MgO;

MgO, CoFeB, Mo, CoFeB, and MgO;

Mn_xGa_y;

Materials with L10 symmetry; or materials with tetragonal crystal structure.

20. The method of claim 17, wherein the one or more materials is a single layer of MnGa.

21. A method comprising:

defining a first backbone grating pattern;

depositing a first spacer on the first backbone grating pattern such that the first spacer is on either sides of the first backbone grating pattern;

selectively etching the first backbone grating pattern leaving behind sidewalls of the first spacer that were deposited on either sides of the first backbone grating pattern; transferring the selectively etched first backbone grating pattern to a second backbone layer to form a patterned second backbone layer; and

depositing a layer of magnetic spacer, formed of one or more materials or a stack of materials of different metals or oxides, on the patterned second backbone layer.

22. The method of claim 21 further comprises:

selectively etching the layer of magnetic spacers such that the patterned second backbone layer is etched to leave behind side walls of the patterned second backbone layer, wherein the sidewalls are formed of the one or more materials or the stack of materials of different metals or oxides.

23. The method of claim 22, wherein the stack of materials of different metals or oxides is at least one of:

Co and Pt;

Co and Pd;

Co and Ni;

MgO, CoFeB, Ta, CoFeB, and MgO;

MgO, CoFeB, W, CoFeB, and MgO;

MgO, CoFeB, V, CoFeB, and MgO;

MgO, CoFeB, Mo, CoFeB, and MgO;

Mn_xGa_y;

Materials with L10 symmetry; or

materials with tetragonal crystal structure.

24. A system comprising:

a memory;

a processor coupled to the memory, the processor having an apparatus according to any one of claims 1 through 6; and

a wireless device for allowing the processor to communicate with another device.

25. A system comprising:

a memory;

a processor coupled to the memory, the processor having an apparatus according to any one of claims 7 through 16; and