CN110047911B - 一种半导体晶圆、键合结构及其键合方法 - Google Patents

一种半导体晶圆、键合结构及其键合方法 Download PDF

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CN110047911B
CN110047911B CN201910324533.8A CN201910324533A CN110047911B CN 110047911 B CN110047911 B CN 110047911B CN 201910324533 A CN201910324533 A CN 201910324533A CN 110047911 B CN110047911 B CN 110047911B
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bonding
wafer
pattern
alignment
layer
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CN110047911A (zh
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周云鹏
郭万里
胡杏
黄宇恒
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Wuhan Xinxin Integrated Circuit Co ltd
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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Abstract

本发明提供一种半导体晶圆、键合结构及其键合方法，该半导体晶圆将与其他晶圆进行晶圆级键合，在该晶圆中，在顶层覆盖层中形成有与互连结构电连接的键合垫，同时，在该顶层覆盖层中形成有键合对准图形，该键合对准图形的图案由设置于顶层覆盖层中的点阵组成。这样，由于键合对准图形设置于顶层覆盖层中，顶层覆盖层之上将不再覆盖其他的材料层，提升键合设备对键合对准图形的识别能力，增大了键合制程工艺对准窗口，同时，键合对准图形的图案由点阵组成，更易于键合孔工艺集成，且避免制造工艺中碟陷等缺陷的产生。

Description

一种半导体晶圆、键合结构及其键合方法
技术领域
本发明涉及半导体器件及其制造领域，特别涉及一种半导体晶圆、键合结构及其键合方法。
背景技术
随着半导体技术的不断发展，晶圆键合技术得到了广泛的应用，晶圆键合是通过键合技术将两片晶圆粘合在一起，实现两片晶圆的垂直互联。
在键合过程中，要使得两片晶圆上的键合孔对准，以保证两片晶圆之间的连接不出现偏差。目前，在进行晶圆键合对准时，主要采用间接对准的方式，其是利用形成键合孔时的光刻对准图形来进行键合对准，而该光刻对准图形形成于顶层金属层，键合时顶层金属层之上已经覆盖有其他的材料层，键合设备对该光刻对准图形的识别存在不稳定性，而且间接对准的方式不利于键合的精确对准。
发明内容
有鉴于此，本发明的目的在于提供一种半导体晶圆、键合结构及其键合方法，提高键合对准图形的识别能力的同时，满足工艺需求。
为实现上述目的，本发明有如下技术方案：
一种半导体晶圆，包括：
半导体衬底；
衬底上的器件结构，以及所述器件结构的互连结构；
覆盖所述互连结构的顶层覆盖层；
设置于所述顶层覆盖层中且与所述互连结构接触连接的键合垫；
设置于所述顶层覆盖层中的键合对准图形，所述键合对准图形的图案由设置于顶层覆盖层中的点阵组成。
可选地，所述键合对准图形的图案由多个子图形组成，且所述键合对准图形为中心对称图形。
可选地，多个所述子图形中的一部分构成环绕图案，另一部分构成内置图案，所述内置图案设置于环绕图案中。
可选地，所述环绕图案为一个多边形的子图形。
可选地，所述环绕图案为多个条形子图形构成的多边形图案。
可选地，所述键合对准图形包括多个区域，相邻区域中的子图形具有不同的延伸方向。
可选地，所述晶圆包括阵列排布的芯片区，所述器件结构形成于所述芯片区，所述键合对准图形形成于所述芯片区之间的切割道上。
可选地，所述点阵中的各点为圆形柱、椭圆形柱或方形柱。
一种键合结构，包括多个晶圆，所述多个晶圆沿垂直于晶圆方向键合在一起，所述多个晶圆中的至少一个上述的晶圆。
一种晶圆的键合方法，包括：
提供待键合晶圆，所述待键合晶圆为上述任一的半导体晶圆；
利用所述待键合晶圆中的键合对准图形进行对准；
进行待键合晶圆与另一晶圆的键合。
本发明实施例提供的半导体晶圆、键合结构及其键合方法，该半导体晶圆将与其他晶圆进行晶圆级键合，在该晶圆中，在顶层覆盖层中形成有与互连结构电连接的键合垫，同时，在该顶层覆盖层中形成有键合对准图形，该键合对准图形的图案由设置于顶层覆盖层中的点阵组成。这样，由于键合对准图形设置于顶层覆盖层中，顶层覆盖层之上将不再覆盖其他的材料层，提升键合设备对对准图形的识别能力，增大了键合制程工艺对准窗口，同时，键合对准图形的图案由点阵组成，更易于键合孔工艺集成，且避免制造工艺中碟陷等缺陷的产生。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1示出了根据本发明实施例的半导体晶圆的剖面结构示意图；
图2示出了根据本发明实施例的半导体晶圆中键合对准图形的俯视结构示意图；
图3示出了本发明实施例的半导体晶圆中键合对准图形的局部放大俯视结构示意图；
图4示出了根据本发明实施例的键合结构的剖面结构示意图。
具体实施方式
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。
在下面的描述中阐述了很多具体细节以便于充分理解本发明，但是本发明还可以采用其它不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本发明内涵的情况下做类似推广，因此本发明不受下面公开的具体实施例的限制。
其次，本发明结合示意图进行详细描述，在详述本发明实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本发明保护的范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
正如背景技术中的描述，在晶圆键合过程中，要使得两片晶圆上的键合孔对准，以保证两片晶圆之间的连接不出现偏差。目前，在进行晶圆键合对准时，主要采用间接对准的方式，其是利用形成键合孔时的光刻对准图形来进行键合对准，而该光刻对准图形形成于顶层金属层，键合时顶层金属层之上已经覆盖有其他的材料层，键合设备对该光刻对准图形的识别存在不稳定性，而且间接对准的方式不利于键合的精确对准。
基于此，本申请提出了一种半导体晶圆，在顶层覆盖层中形成有与互连结构电连接的键合垫，同时，在该顶层覆盖层中形成有键合对准图形，该键合对准图形的图案由设置于顶层覆盖层中的点阵组成。这样，由于键合对准图形设置于顶层覆盖层中，顶层覆盖层之上将不再覆盖其他的材料层，提升键合设备对键合对准图形的识别能力，增大了键合制程工艺对准窗口，同时，键合对准图形的图案由点阵组成，更易于键合孔工艺集成，且避免制造工艺中碟陷等缺陷的产生。
为了更好地理解本申请的技术方案和技术效果，以下将结合具体的实施例进行详细的说明，参考图1所示，该半导体晶圆包括：
半导体衬底100；
衬底100上的器件结构110，以及所述器件结构110的互连结构120；
覆盖所述互连结构120的顶层覆盖层140；
设置于所述顶层覆盖层140中且与所述互连结构120接触连接的键合垫150；
设置于所述顶层覆盖层140中的键合对准图形160，所述键合对准图形160的图案由设置于顶层覆盖层140中的点阵162形成。
在本申请实施例中，衬底100为半导体衬底，例如可以为Si衬底、Ge衬底、SiGe衬底、SOI(绝缘体上硅，Silicon On Insulator)或GOI(绝缘体上锗，Germanium OnInsulator)等。在其他实施例中，衬底100还可以为包括其他元素半导体或化合物半导体的衬底，例如GaAs、InP或SiC等，还可以为叠层结构，例如Si/SiGe等，还可以为其他外延结构，例如SGOI(绝缘体上锗硅)等。在本实施例中，该衬底100可以为硅衬底。
在该衬底100上已经形成有器件结构110以及电连接器件结构110的互连结构120。其中，器件结构的器件类型可以包括MOS场效应晶体管器件、存储器件和/其他无源器件，存储器件可以包括非易失性存储器或随机存储器等，非易失性存储器例如可以包括NOR型闪存、NAND型闪存等浮栅场效应晶体管或者铁电存储器、相变存储器等，器件结构可以为平面型器件或立体器件，立体器件例如可以为FIN-FET(鳍式场效应晶体管)、三维存储器等。在一个具体的示例中，器件结构可以为MOS场效应晶体管器件，MOS场效应晶体管器件至少包括栅介质层、栅极以及栅极两侧衬底中的源区、漏区。在另一个具体的示例中，器件结构可以为浮栅场效应晶体管，浮栅场效应晶体管至少包括栅极以及源区、漏区，其中，栅极包括浮栅和控制栅，浮栅和控制栅之间通过介质材料隔离。
互连结构120形成于介质层130、132中，互连结构120用于器件结构110的电引出，互连结构120可以为多层结构，互连结构120包括接触塞、连线层以及过孔，其中，互连结构120的最顶层为顶层连线层124，该顶层连线层124上将形成键合垫150，互连结构120可以由金属材料形成，例如可以为钨、铝、铜等。可以理解的是，在不同的设计和应用中，根据不同的需要，可以根据需要形成所需层数的连接层和过孔的层数。
同样地，介质层130、132也可以为多层结构，可以包括覆盖器件结构110的层间介质层以及层间介质层之上隔离互连层的内金属介电层，介质层的材料例如可以为未掺杂的氧化硅(SiO2)、掺杂的氧化硅(如硼硅玻璃、硼磷硅玻璃等)、氮化硅(Si3N4)或其他低k介质材料中的一种或多种。
覆盖层140覆盖于上述的衬底之上，在覆盖层140中形成有与互连结构120接触连接的键合垫150，键合垫150将互连结构120引出，且通过该键合垫150进一步与另一晶圆上对应的键合部件进行键合。覆盖层140可以具有多层结构的介质材料形成，在具体的实施例中，该覆盖层140可以包括键合用的粘合层以及粘合层上的保护层，该覆盖层140一方面作为用于与其他晶片键合时的键合材料层，同时，作为键合垫中金属材料的隔离层。
在一个具体的实施例中，覆盖层140可以包括由下至上依次层叠的第一粘合层146、第二粘合层148以及保护层149，第一粘合层146下还可以形成有扩散阻挡层142。其中，该第一粘合层146和第二粘合层148可以为不同的键合(bonding)材料，第二粘合层148可以选用性能更优的键合材料，本实施例中，第一粘合层146可以为键合用氧化硅(bondingoxide)，第二粘合层148可以为NDC(Nitrogen doped Silicon Carbide，掺氮碳化硅)，保护层149用于粘合层的保护，该保护层可以为氧化硅，扩散阻挡层142可以避免工艺过程中金属材料的溅射以及扩散，扩散阻挡层142的材料可以为氮化硅。
键合垫150形成在覆盖层140中，键合垫150为晶圆最表层的电连接层，将用于与其他晶圆之间的对准键合。键合垫150为导电材料，通常为金属材料，例如可以为铜等。键合垫150可以包括位于顶层金属层124上的过孔以及过孔上的沟槽，在本实施例中，过孔贯穿第一粘合层146以及其下的扩散阻挡层142至顶层金属层124，与顶层金属层124接触连接，沟槽位于过孔之上且贯穿第二粘合层148以及保护层149。
在本申请中，键合对准图形160同样形成于顶层覆盖层140中，至少与顶层覆盖层140中的表层具有不同的材料，可以在形成键合垫150的工艺中一并形成该键合对准图形，该键合对准图形160的图案由设置于顶层覆盖层140中的点阵162组成。其中，键合对准图形160为用于键合对准时的图形，构成图形的图案是由点阵162组成，点阵162为阵列排布，阵列中的各点可以为柱状，例如可以为圆形柱、椭圆形柱或方形柱等，方形柱包括长方形柱或正方形柱，点阵162可以贯通整个顶层覆盖层140或者贯穿部分厚度的顶层覆盖层140，点阵162可以具有与键合垫150相同的材料。
在形成键合对准图形160时，需要先在顶层覆盖层140中刻蚀出键合对准图形160的图案，而后，进行填充材料的沉积，而后，通过平坦化工艺去除多余的填充材料，键合对准图形160的图案采用点阵，即通过相互间隔且阵列排布的孔形成图案，这样，在平坦化工艺中，可以避免由于大片图案而导致的碟陷(dishing)的缺陷，同时，点阵容易与键合孔的工艺一并集成，提高工艺的可实现性以及集成度，无需增加制造成本。
在具体的实施例中，参见图2所示，键合对准图形160的图案可以由多个子图形组成，键合对准图形160可以为中心对称图形，这样，有利于对准时算法的计算，提高对准的效率和准确度，其中，子图形是由设置于顶层覆盖层140中的点阵162组成，子图形之间具有一定的间隔，该间隔远大于点阵内各点之间的间距。
具体的，在一些应用中，参见图2中(A)所示，多个所述子图形中的一部分构成环绕图案1601，另一部分构成内置图案1602，所述内置图案1602设置于环绕图案1601中，该环绕图案1601可以为多个条形子图形构成的多边形图案，例如可以为四边形，该具体的示例中，内置图案1602由沿四边形对角线延伸的交叉条形子图形以及四个三角形的子图形构成，四个三角形的子图形分别设置于交叉条形子图形构成的四个区域内，该键合对准图形160的尺寸例如可以为5*14μm。
在另一些应用中，参见图2中(B)和(C)所示，环绕图案1601为一个多边形的子图形，例如可以为八边形，该具体的示例中，多边形的子图形的各条边依次凹、凸设置，内置图案1602的子图形包括中心图案以及沿中心图案延伸的延伸图案组成，延伸图案与多边形的子图形的凹部对应设置，如图(B)和(C)所示，子图形的中心图案可以为空心或实心图案，其尺寸例如可以分别为7*16μm、20*20μm。
在又一些应用中，参见图2中(D)所示，键合对准图形160可以包括多个区域160-1、160-2、160-3、160-4，而相邻区域中的子图形具有不同的延伸方向，该图形具有好的辨识度，且更易于工艺加工。在具体的示例中，如图2中(D)所示，键合对准图形160可以包括分别位于上、下、左、右、四个方位的区域160-1、160-2、160-3、160-4，相邻区域中，一个区域中的子图形沿一个方向延伸，另一个区域中的子图形沿另一个方向延伸，这两个延伸方向可以为正交的方向，该键合对准图形160的尺寸例如可以为10*27μm。
为了便于理解键合对准图形的图案的组成，以一个具体示例俯视的局部放大图进行说明，参考图3所示，其中(A)为键合对准图形160的图案，(B)为图(A)中部分图案的局部放大，图(C)为图(B)中部分图案的局部放大，可以看到图案是由点阵组成，点阵中的各点的尺寸可以与各点之间的间隔具有基本相同的尺寸，该点阵162形成于顶层覆盖层140中，各点由顶层覆盖层140包围。
对于上述的键合对准图形160可以形成于晶圆的切割道区域上，晶圆包括阵列排布的芯片区，芯片区用于形成器件结构，芯片区之间的区域为切割道，切割道用于将晶圆上的各芯片区分割为独立的芯片。
以上对本申请实施例的半导体晶圆的结构进行了详细的描述，该半导体晶圆将与其他晶圆进行晶圆级键合，由于键合对准图形设置于顶层覆盖层中，顶层覆盖层之上将不再覆盖其他的材料层，提升键合设备对光刻对准图形的识别能力，增大了键合制程工艺对准窗口，同时，键合对准图形的图案由点阵组成，更易于键合孔工艺集成，且避免制造工艺中碟陷等缺陷的产生。
此外，本申请还提供了一种键合结构，参考图4所示，包括多个晶圆10、20，在沿垂直于晶圆方向上多个晶圆10、20键合在一起，垂直于晶圆方向也即垂直于衬底方向，多个晶圆10、20中的至少一个晶圆为上述实施例中的半导体晶圆。
此外，本申请还提供了一种晶圆的键合方法，利用上述的半导体晶圆进行键合，该方法包括：
在步骤S01，提供待键合晶圆，待键合晶圆为上述实施例中的半导体晶圆。
该待键合晶圆为已完成所有器件加工工艺后的晶圆，该待键合晶圆为上述实施例中的半导体晶圆，在顶层覆盖层中设置有键合对准图形，且键合对准图形的图案由设置于顶层覆盖层中的点阵组成，待键合晶圆提供至键合设备，以供与另一晶圆进行键合。
在步骤S02，利用所述待键合晶圆中的键合对准图形进行对准。
由于该待键合晶圆的顶层覆盖层中设置有键合对准图形，键合设备可以通过该键合对准图形将待键合晶圆进行对准，间接实现与另一晶圆的对准。由于键合对准图形设置于顶层覆盖层中，顶层覆盖层之上将不再覆盖其他的材料层，提升键合设备对光刻对准图形的识别能力，增大了键合制程工艺对准窗口。
在步骤S03，进行待键合晶圆与另一晶圆的键合。
该另一晶圆可以在键合设备中已完成对准，该另一晶圆也可以为上述实施例中的半导体晶圆，在顶层覆盖层中设置有键合对准图形，且键合对准图形的图案由设置于顶层覆盖层中的点阵组成，也可以是通过键合对准图形完成对准。
这样，在对准之后，待键合晶圆在设备中的相对位置已确定，与另一晶圆的相对位置也已确定，进而，进行键合工艺，可以实现两晶圆的精确对准，提高形成的键合结构的良率。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其它实施例的不同之处。尤其，对于存储器件实施例而言，由于其基本相似于方法实施例，所以描述得比较简单，相关之处参见方法实施例的部分说明即可。
以上所述仅是本发明的优选实施方式，虽然本发明已以较佳实施例披露如上，然而并非用以限定本发明。任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭示的方法和技术内容对本发明技术方案做出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何的简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。

Claims (5)

1.一种半导体晶圆，其特征在于，包括：
半导体衬底；
衬底上的器件结构，以及所述器件结构的互连结构；
覆盖所述互连结构的顶层覆盖层；
设置于所述顶层覆盖层中且与所述互连结构接触连接的键合垫；
设置于所述顶层覆盖层中的键合对准图形，所述键合对准图形的图案由多个子图形组成，所述子图形由设置于顶层覆盖层中的点阵组成，所述键合对准图形包括多个区域，相邻区域中的子图形具有不同的延伸方向；
其中所述点阵为相互间隔且阵列排布的孔，所述点阵中的各点的尺寸与各点之间的间隔具有基本相同的尺寸。
2.根据权利要求1所述的晶圆，其特征在于，所述晶圆包括阵列排布的芯片区，所述器件结构形成于所述芯片区，所述键合对准图形形成于所述芯片区之间的切割道上。
3.根据权利要求1所述的晶圆，其特征在于，所述点阵中的各点为圆形柱、椭圆形柱或方形柱。
4.一种键合结构，其特征在于，包括多个晶圆，所述多个晶圆沿垂直于晶圆方向键合在一起，所述多个晶圆中的至少一个为权利要求1-3中任一项所述的晶圆。
5.一种晶圆的键合方法，其特征在于，包括：
提供待键合晶圆，所述待键合晶圆为如权利要求1-3中任一项所述的半导体晶圆；
利用所述待键合晶圆中的键合对准图形进行对准；
进行待键合晶圆与另一晶圆的键合。
CN201910324533.8A 2019-04-22 2019-04-22 一种半导体晶圆、键合结构及其键合方法 Active CN110047911B (zh)

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