CN113314488A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN113314488A
CN113314488A CN202110047544.3A CN202110047544A CN113314488A CN 113314488 A CN113314488 A CN 113314488A CN 202110047544 A CN202110047544 A CN 202110047544A CN 113314488 A CN113314488 A CN 113314488A
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semiconductor device
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荒井伸也
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Kioxia Corp
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Kioxia Corp
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Abstract

实施方式提供一种可抑制嵌埋有垫的绝缘膜内的缺陷的半导体装置及其制造方法。根据一实施方式，半导体装置包含第1芯片、及与所述第1芯片贴合的第2芯片。所述第1芯片包含：衬底；逻辑电路，设置于所述衬底上；及多个第1虚设垫，配置于所述逻辑电路的上方，设置于所述第1芯片与所述第2芯片贴合而成的第1贴合面，且不与所述逻辑电路电连接。所述第2芯片包含：多个第2虚设垫，设置于所述多个第1虚设垫上；及存储单元阵列，设置于所述多个第2虚设垫的上方。所述第1贴合面中的所述第1虚设垫的被覆率在所述第1芯片的与第1端边分离的第1区域和配置于所述第1端边与所述第1区域之间的第2区域中不同。

Description

半导体装置及其制造方法
[相关申请案]
本申请案享有以日本专利申请案2020-30950号(申请日：2020年2月26日)为基础申请案的优先权。本申请案通过参照该基础申请案而包含基础申请案的全部内容。
技术领域
本发明的实施方式涉及一种半导体装置及其制造方法。
背景技术
当贴合多个晶圆的金属垫(metal pad)来制造半导体装置时，在嵌埋有金属垫的层间绝缘膜内可能产生空隙(void)等缺陷。
发明内容
实施方式提供一种可抑制嵌埋有垫的绝缘膜内的缺陷的半导体装置及其制造方法。
根据一实施方式，半导体装置包含第1芯片、及与所述第1芯片贴合的第2芯片。所述第1芯片包含：衬底；逻辑电路，设置于所述衬底上；及多个第1虚设垫，配置于所述逻辑电路的上方，设置于所述第1芯片与所述第2芯片贴合而成的第1贴合面，且不与所述逻辑电路电连接。所述第2芯片包含：多个第2虚设垫，设置于所述多个第1虚设垫上；及存储单元阵列，设置于所述多个第2虚设垫的上方。所述第1贴合面中的所述第1虚设垫的被覆率在所述第1芯片的与第1端边分离的第1区域和配置于所述第1端边与所述第1区域之间的第2区域中不同。
根据实施方式，能够提供一种可抑制嵌埋有垫的绝缘膜内的缺陷的半导体装置及其制造方法。
附图说明
图1是表示第1实施方式的半导体装置的结构的剖视图。
图2是表示第1实施方式的柱状部CL的结构的剖视图。
图3、图4是表示第1实施方式的半导体装置的制造方法的剖视图。
图5是示意性地表示第1实施方式的电路晶圆W2的结构的俯视图。
图6(a)、(b)是用于说明第1实施方式的电路晶圆W2的问题的剖视图。
图7是表示第1实施方式的电路晶圆W2的结构的俯视图。
图8是表示第1实施方式的有源区域R1a与虚设区域R1b的结构的俯视图。
图9是表示第1实施方式的虚设区域R1c的结构的俯视图。
图10是表示第1实施方式的虚设区域R1d的结构的俯视图。
图11是表示第1实施方式的虚设区域R1b与虚设区域R1c的边界附近的结构的俯视图。
图12是表示第1实施方式的虚设区域R1c与虚设区域R1d的边界附近的结构的俯视图。
图13是表示第1实施方式的虚设区域R1d与切割区域R2的边界附近的结构的俯视图。
图14(a)、(b)是用于说明第1实施方式的电路晶圆W2的作用的剖视图。
具体实施方式
以下，参照附图说明本发明的实施方式。图1至图14中，对相同构成附上相同符号，并省略重复的说明。
(第1实施方式)
图1是表示第1实施方式的半导体装置的结构的剖视图。图1的半导体装置是贴合有阵列芯片1与电路芯片2的三维存储器。电路芯片2是第1芯片的示例，阵列芯片1是第2芯片的示例。
阵列芯片1包含含有多个存储单元的存储单元阵列11、存储单元阵列11上的绝缘膜12、及存储单元阵列11下的层间绝缘膜13。绝缘膜12例如是氧化硅膜或氮化硅膜。层间绝缘膜13例如是氧化硅膜或包含氧化硅膜与其它绝缘膜的积层膜。
电路芯片2设置于阵列芯片1下。符号S表示阵列芯片1与电路芯片2的贴合面。贴合面S是第1贴合面的示例。电路芯片2包含层间绝缘膜14、及层间绝缘膜14下的衬底15。层间绝缘膜14例如是氧化硅膜或包含氧化硅膜与其它绝缘膜的积层膜。衬底15例如是硅衬底等半导体衬底。
图1示出与衬底15的表面平行且相互垂直的X方向及Y方向、以及与衬底15的表面垂直的Z方向。本说明书中，将+Z方向视作上方向，-Z方向视作下方向。-Z方向可与重力方向一致也可不一致。
阵列芯片1包含多条字线WL、源极线SL作为存储单元阵列11内的电极层。图1示出存储单元阵列11的阶梯结构部21。各字线WL经由接触插塞22而与字配线层23电连接。贯通多条字线WL的各柱状部CL经由介层插塞(via plug)24而与位线BL电连接，且与源极线SL电连接。源极线SL包含作为半导体层的第1层SL1及作为金属层的第2层SL2。
电路芯片2包含多个晶体管31。各晶体管31包含：栅极电极32，隔着栅极绝缘膜设置于衬底15上；以及未图示的源极扩散层及漏极扩散层，设置于衬底15内。而且，电路芯片2包含：多个接触插塞33，设置于这些晶体管31的栅极电极32、源极扩散层或漏极扩散层上；配线层34，设置于这些接触插塞33上且包含多条配线；及配线层35，设置于配线层34上且包含多条配线。
电路芯片2还包含：配线层36，设置于配线层35上且包含多条配线；多个介层插塞37，设置于配线层36上；及多个金属垫38，设置于这些介层插塞37上。金属垫38例如是Cu(铜)层或Al(铝)层。金属垫38是第1垫(第1有源垫及第1虚设垫)的示例。关于金属垫38的详情将在下文叙述。电路芯片2作为控制阵列芯片1的动作的控制电路(逻辑电路)发挥功能。该控制电路由晶体管31等构成，且与金属垫38电连接。
阵列芯片1包含设置于金属垫38上的多个金属垫41、及设置于金属垫41上的多个介层插塞42。而且，阵列芯片1包含：配线层43，设置于这些介层插塞42上且包含多条配线；及配线层44，设置于配线层43上且包含多条配线。金属垫41例如是Cu层或Al层。金属垫41是第2垫(第2有源垫及第2虚设垫)的示例。关于金属垫41的详情将在下文叙述。
阵列芯片1还包含设置于配线层44上的多个介层插塞45、设置于这些介层插塞45上及绝缘膜12上的金属垫46、以及设置于金属垫46上及绝缘膜12上的钝化膜47。金属垫46例如是Cu层或Al层，并作为图1的半导体装置的外部连接垫(接合垫(bonding pad))发挥功能。钝化膜47例如是氧化硅膜等绝缘膜，且具有使金属垫46的上表面露出的开口部P。金属垫46能够经由该开口部P并通过接合线、焊球、金属凸块等连接至安装衬底或其它装置。
图2是表示第1实施方式的柱状部CL的结构的剖视图。
如图2所示，存储单元阵列11包含交替地积层于层间绝缘膜13(图1)上的多条字线WL及多个绝缘层51。字线WL例如是W(钨)层。绝缘层51例如是氧化硅膜。
柱状部CL依次包含阻挡绝缘膜52、电荷蓄积层53、隧道绝缘膜54、信道半导体层55及芯绝缘膜56。电荷蓄积层53例如是氮化硅膜，隔着阻挡绝缘膜52形成于字线WL及绝缘层51的侧面。电荷蓄积层53可以是多晶硅层等半导体层。信道半导体层55例如是多晶硅层，隔着隧道绝缘膜54形成于电荷蓄积层53的侧面。阻挡绝缘膜52、隧道绝缘膜54及芯绝缘膜56例如是氧化硅膜或金属绝缘膜。
图3及图4是表示第1实施方式的半导体装置的制造方法的剖视图。
图3示出包含多个阵列芯片1的阵列晶圆W1及包含多个电路芯片2的电路晶圆W2。阵列晶圆W1也被称为“存储器晶圆”，电路晶圆W2也被称为“CMOS(complementary metaloxide semiconductor，互补金属氧化物半导体)晶圆”。电路晶圆W2是第1晶圆的示例，阵列晶圆W1是第2晶圆的示例。
注意，图3的阵列晶圆W1的取向与图1的阵列芯片1的取向相反。本实施方式中，通过将阵列晶圆W1与电路晶圆W2贴合来制造半导体装置。图3示出为了进行贴合而反转取向前的阵列晶圆W1，图1示出为了进行贴合而反转取向并进行贴合及切割后的阵列芯片1。
图3中，符号S1表示阵列晶圆W1的上表面，符号S2表示电路晶圆W2的上表面。注意，阵列晶圆W1包含设置于绝缘膜12下的衬底16。衬底16例如是硅衬底等半导体衬底。衬底15是第1衬底的示例，衬底16是第2衬底的示例。
本实施方式中，首先，如图3所示，在阵列晶圆W1的衬底16上形成存储单元阵列11、绝缘膜12、层间绝缘膜13、阶梯结构部21、金属垫41等，在电路晶圆W2的衬底15上形成层间绝缘膜14、晶体管31、金属垫38等。例如，在衬底16上依次形成介层插塞45、配线层44、配线层43、介层插塞42及金属垫41。而且，在衬底15上依次形成接触插塞33、配线层34、配线层35、配线层36、介层插塞37及金属垫38。接下来，如图4所示，利用机械压力将阵列晶圆W1与电路晶圆W2贴合。由此，层间绝缘膜13与层间绝缘膜14粘附。接下来，将阵列晶圆W1及电路晶圆W2以400℃退火。由此，金属垫41与金属垫38接合。
然后，利用CMP(Chemical Mechanical Polishing，化学机械研磨)将衬底15薄膜化，利用CMP去除衬底16后，将阵列晶圆W1及电路晶圆W2切断为多个芯片。以此方式，制造出图1的半导体装置。图1示出包含金属垫38的电路芯片2、包含配置于金属垫38上的金属垫41的阵列芯片1。另外，金属垫46与钝化膜47例如在衬底15薄膜化及衬底16去除之后，形成于绝缘膜12上。
另外，本实施方式中是将阵列晶圆W1与电路晶圆W2贴合，也可取代之，将阵列晶圆W1彼此贴合。参照图1至图4前述的内容或参照图5至图14后述的内容，也可适用于阵列晶圆W1彼此的贴合。
而且，图1示出层间绝缘膜13与层间绝缘膜14的边界面及金属垫41与金属垫38的边界面，一般来说，所述退火后无法再观察到这些边界面。然而，这些边界面所处的位置能够通过例如检测金属垫41的侧面或金属垫38的侧面的斜率、或金属垫41的侧面与金属垫38的位移来推断。
另外，本实施方式的半导体装置可在切断为多个芯片后的图1的状态下成为交易的对象，也可在切断为多个芯片前的图4的状态下成为交易的对象。图1示出芯片状态的半导体装置，图4示出晶圆状态的半导体装置。本实施方式中，由一个晶圆状的半导体装置(图4)制造出多个芯片状的半导体装置(图1)。
以下，参照图5至图14来说明本实施方式的电路晶圆W2的详情，具体地说明本实施方式的金属垫38的配置的详情。以下的说明也适用于本实施方式的阵列晶圆W1或本实施方式的金属垫41的配置。
图5是示意性地表示第1实施方式的电路晶圆W2的结构的俯视图。
如图5所示，本实施方式的电路晶圆W2包含配置成二维阵列状的多个芯片区域R1、及包围这些芯片区域R1的切割区域R2。切割区域R2具有如下形状，即，该形状包含在X方向延伸的多条切割线及在Y方向延伸的多条切割线。图5还示出芯片区域R1与切割区域R2的边界线(边界面)E。
本实施方式的电路晶圆W2在与阵列晶圆W1贴合后被切断为多个芯片。此时，通过用切割刀切断切割区域R2而加工出电路晶圆W2。通过切断而获得的各芯片包含电路晶圆R2的一个芯片区域R1及阵列晶圆R1的相同的一个芯片区域。该情况下，所述边界面E成为各芯片的端面(端边)。各芯片的端面包含衬底15的侧面及层间绝缘膜14的侧面。该端边是第1端边的示例。
图6是用于说明第1实施方式的电路晶圆W2的问题的剖视图。
图6(a)示出电路晶圆W2的芯片区域R1及切割区域R2的截面。本实施方式中，在层间绝缘膜14内嵌埋金属垫38后，通过CMP使金属垫38的表面平坦化。此时，当将金属垫38与层间绝缘膜14的大抛光速率比(polishing rate)(Cu/SiO2)的浆料用于CMP时，担心产生金属垫38的表面凹进的凹陷(dishing)或芯片区域R1的表面倾斜(参照图6(a))。
图6(b)也示出了电路晶圆W2的芯片区域R1及切割区域R2的截面。所述凹陷或倾斜能够通过将金属垫38与层间绝缘膜14的小抛光速率比(Cu/SiO2)的浆料用于CMP中而抑制。然而，该情况下，因层间绝缘膜14更容易削除，所以担心在金属垫38的密度低的区域中，在层间绝缘膜14产生空隙。图6(b)示了出未配置金属垫38的切割区域R2中产生的空隙V。理想的是抑制这种空隙V的产生。
图7是表示第1实施方式的电路晶圆W2的结构的俯视图。图7示出穿过电路晶圆W2内的金属垫38的XY截面，例如，示出阵列晶圆W1与电路晶圆W2的贴合面S的XY截面。
图7示出一个芯片区域R1及包围该芯片区域R1的切割区域R2。如图7所示，本实施方式的芯片区域R1包含多个有源区域R1a、及多个虚设区域R1b、R1c、R1d。
有源区域R1a包含被称作有源垫的多个金属垫38。另一方面，虚设区域R1b、R1c、R1d包含被称作虚设垫的多个金属垫38。有源垫是用于传输信号或电力以使半导体装置动作的垫，虚设垫是不用于传输信号或电力以使半导体装置动作的垫。有源垫与半导体装置内的电路元件(例如存储单元阵列11或晶体管31)电连接，但虚设垫不与半导体装置内的电路元件电连接。虚设垫例如是为了调整贴合面S中的金属垫38的密度而配置的。
本实施方式的虚设区域R1b、R1c、R1d包含：虚设区域R1b，配置于有源区域R1a的周围；虚设区域R1c，配置于芯片区域R1内的中心部；及虚设区域R1d，配置于芯片区域R1内的周边部。这些虚设区域R1b、R1c、R1d如后述那样彼此以不同的密度包含金属垫38。
接下来，对图7所示的XY截面中的金属垫38的被覆率进行说明。例如芯片区域R1内的金属垫38的被覆率是芯片区域R1内的金属垫38的总面积(Sa)相对于芯片区域R1的总面积(Sb)的百分比(％)，由Sa÷Sb×100表示。金属垫38的被覆率是与各区域内的金属垫38的密度相当的值。
本实施方式的有源区域R1a及虚设区域R1b、R1c、R1d具有特定的被覆率。具体来说，有源区域R1a内的金属垫38的被覆率为10～40％，例如为25％。而且，虚设区域R1b内的金属垫38的被覆率为10～40％，例如为25％。而且，虚设区域R1c内的金属垫38的被覆率为10～40％，例如约为20％。而且，虚设区域R1d内的金属垫38的被覆率为5～20％，例如约为10％。
本实施方式的虚设区域R1d具有包围有源区域R1a及虚设区域R1b、R1c的环状形状，且与切割区域R2相邻。另一方面，本实施方式的有源区域R1a及虚设区域R1b、R1c由虚设区域R1d包围，且与切割区域R2分离。换句话说，虚设区域R1d与边界线E相邻，有源区域R1a及虚设区域R1b、R1c与边界线E分离。
此外，本实施方式的虚设区域R1d内的金属垫38的被覆率与有源区域R1a及虚设区域R1b、R1c内的金属垫38的被覆率不同，更详细来说，低于有源区域R1a及虚设区域R1b、R1c内的金属垫38的被覆率。由此，例如，能够减小切割区域R2内产生的空隙V的深度(参照图6)。原因在于，通过降低虚设区域R1d内的金属垫38的被覆率，能够减小虚设区域R1d与切割区域R2之间的被覆率之差，能够减少边界线E附近处的金属垫38的密度变化。另外，本实施方式的切割区域R2包含由金属形成的对准标记，但不包含金属垫38，切割区域R2内的金属垫38的被覆率为0％。虚设区域R1b、R1c是第1区域的示例，虚设区域R1d是第2区域的示例，有源区域R1a是第3区域的示例。
这样，本实施方式的虚设区域R1d内的金属垫38的被覆率低于有源区域R1a及虚设区域R1b、R1c内的金属垫38的被覆率。由此，能够减小切割区域R2内产生的空隙V的深度。为了有效地减小空隙V的深度，虚设区域R1c内的被覆率与虚设区域R1d内的被覆率之比理想的是设定在3：2与3：1之间。关于这一点，虚设区域R1b内的被覆率与虚设区域R1d内的被覆率之比或有源区域R1a内的被覆率与虚设区域R1d内的被覆率之比也是相同的。此外，理想的是有源区域R1a及虚设区域R1b、R1c内的平均被覆率与虚设区域R1d内的被覆率之比也设定在3：2与3：1之间。
此外，本实施方式中，虚设区域R1b内的被覆率及虚设区域R1c内的被覆率为有源区域R1a内的被覆率以下。详细来说，与有源区域R1a相邻的虚设区域R1b内的被覆率与有源区域R1a内的被覆率相同，与有源区域R1a分离的虚设区域R1c内的被覆率小于有源区域R1a内的被覆率。由此，例如，能够使被覆率从有源区域R1a到虚设区域R1d逐渐减小。虚设区域R1b是第1被覆率区域的示例，虚设区域R1c是第2被覆率区域的示例。
各区域内的被覆率例如通过使金属垫38的尺寸发生变化或使金属垫38间的间距发生变化而改变。稍后将对本实施方式的有源区域R1a及虚设区域R1b、R1c内的金属垫38的配置进行叙述。
图7还示出了虚设区域R1b与切割区域R2之间的最短距离T。最短距离T例如为5μm以上。另一方面，具有环状形状的虚设区域R1d的环宽度例如通常为100μm。图7中，许多个虚设区域R1b被虚设区域R1c包围，但部分虚设区域R1b从虚设区域R1c突出且与虚设区域R1d相邻。因此，所述最短距离T可比虚设区域R1d的环宽度短。如果从另一个角度来看，则虚设区域R1d的环宽度通常为100μm，但在所述部分虚设区域R1b的附近要比100μm短。
图8是表示第1实施方式的有源区域R1a与虚设区域R1b的结构的俯视图。
图8示出有源区域R1a内的金属垫38及虚设区域R1b内的金属垫38。图8中，这些金属垫38配置成正方形或长方形的格子状，有源区域R1a内的被覆率与虚设区域R1b内的被覆率均设定为25％。符号U表示所述格子的单位区域。一个单位区域U的面积是一个金属垫38面积的4倍，结果，有源区域R1a及虚设区域R1b内的被覆率为25％。
图8还关于有源区域R1a及虚设区域R1b内的金属垫38示出了各金属垫38的X方向的尺寸Ax、各金属垫38的Y方向的尺寸Ay、金属垫38间的X方向的间距Bx、金属垫38间的Y方向的间距By。本实施方式中，它们的关系设定为Ax＝Ay、Bx＝By。
图9是表示第1实施方式的虚设区域R1c的结构的俯视图。
图9示出虚设区域R1c内的金属垫38。图9中，这些金属垫38配置成三角形(或平行四边形)的格子状，虚设区域R1c内的被覆率约设定为20％。虚设区域R1c内的金属垫38配置于与直线M1平行的多条第1直线和与直线M2平行的多条第2直线的交点处。第1直线相对于X方向倾斜，第2直线相对于Y方向倾斜。
图9还关于虚设区域R1c内的金属垫38示出了各金属垫38的X方向的尺寸Cx、各金属垫38的Y方向的尺寸Cy、金属垫38间的X方向的间距Dx、金属垫38间的Y方向的间距Dy、金属垫38间的X方向的位移量Ex、金属垫38间的Y方向的位移量Ey。本实施方式中，它们的关系设定为Cx＝Cy、Dy＝Dz、Ex＝Ey。此外，本实施方式中，将尺寸设定为Ax＝Cx，间距设定为Bx≠Dx。
这样，在虚设区域R1b与虚设区域R1c之间，金属垫38的尺寸无论在X方向上还是在Y方向上均彼此相同，金属垫38间的间距彼此不同。结果，金属垫38的被覆率在虚设区域R1b与虚设区域R1c之间彼此不同。另外，在虚设区域R1b与虚设区域R1c之间，金属垫38的尺寸可彼此不同，金属垫38间的间距可彼此相同，由此，彼此的被覆率可不同。
本实施方式中，在有源区域R1a与虚设区域R1c之间设置有虚设区域R1b。因此，芯片区域R1内的被覆率在有源区域R1a与虚设区域R1b之间未降低，在虚设区域R1b与虚设区域R1c之间降低。由此，能够抑制在有源区域R1a的端部产生空隙。另一方面，虽在虚设区域R1b与虚设区域R1c的边界附近可能产生空隙，但虚设区域R1b与虚设区域R1c的边界附近配置有虚设垫而未配置有有源垫。由此，能够抑制空隙对有源垫造成不良影响而妨碍半导体装置的动作。一般来说，虚设垫不会对半导体装置的动作造成影响。
以下，对决定本实施方式的虚设区域R1c内的金属垫38的配置的方法的示例进行说明。
本实施方式中，当决定虚设区域R1c内的金属垫38的配置时，固定Cx(＝Cy)的值后，使Ex(＝Ey)的值变动为各种值。由此，因被覆率变动，所以算出获得所需被覆率的Ex的值。此时，当使被覆率变动时，直线M1及M2延伸的方向发生变化。被覆率越大，也就是Ex越小，直线M1相对于X轴的角度越大，直线M2相对于Y轴的角度也越大。结果，直线M1与直线M2间的锐角θ1的角度减小。
用所述方法来决定虚设区域R1c内的金属垫38的配置的原因在于，理想的是将直线M1及M2延伸的方向设为与X方向及Y方向不同的方向。换句话说，将虚设区域R1c内的金属垫38排列的方向与有源区域R1a及虚设区域R1b内的金属垫38排列的方向错开，以避免在半导体装置内金属垫38在相同的方向上连续排列。结果，在虚设区域R1b与虚设区域R1c之间，金属垫38排列的方向是不连续的。关于这一点，虚设区域R1b与虚设区域R1c之间也是相同的。原因在于，图9的直线M1及M2延伸的方向与图10的直线N1及N2(后述)延伸的方向不同。例如，直线N1与直线N2之间的锐角θ2(后述)的角度和直线M1与直线M2之间的锐角θ1的角度不同。
而且，避免在半导体装置内金属垫38在相同的方向上连续排列的原因为如下所示。
当贴合阵列晶圆W1与电路晶圆W2时，晶圆彼此的贴合(进行贴合)从各晶圆的中心部进行到端部。这里，晶圆的进行贴合的速度依存于金属垫38、41的排列(排列方式)。
一般来说，在贴合时金属垫38、41的表面相对于层间绝缘膜14、13的表面凹进，且晶圆彼此的贴合在不存在金属垫38、41的方向上进行得更快(进行贴合的速度更大)。这是因为在该方向上几乎不存在金属垫38、41的表面，且存在许多层间绝缘膜14、13的表面。另外，通过利用贴合后的退火处理使金属垫38、41膨胀来贴合(接合)金属垫38与金属垫41。
由此，如果在半导体装置内金属垫38在相同的方向上连续排列，则该方向上的进行贴合的速度小于其它方向上的进行贴合的速度，晶圆间进行贴合的速度不均匀。如果晶圆间进行贴合的速度不均匀，则已贴合的区域会折入未贴合的区域的前端部分，结果，在晶圆间形成空隙。由于空隙阻碍金属垫38彼此的接合，因此，如果在空隙的附近存在有源区域R1a，则半导体装置会产生缺陷不良。
以上是避免在半导体装置内金属垫38在相同的方向上连续排列的原因。根据本实施方式，通过将虚设区域R1c内的金属垫38排列的方向与有源区域R1a及虚设区域R1b内的金属垫38排列的方向错开，能够避免在半导体装置内金属垫38在相同的方向上连续排列。
图10是表示第1实施方式的虚设区域R1d的结构的俯视图。
图10示出虚设区域R1d内的金属垫38。图10中，这些金属垫38配置成三角形(或平行四边形)的格子状，虚设区域R1d内的被覆率约设定为10％。虚设区域Rd内的金属垫38配置于与直线N1平行的多条第1直线和与直线N2平行的多条第2直线的交点处。第1直线相对于X方向倾斜，第2直线相对于Y方向倾斜。
图10还关于虚设区域R1d内的金属垫38示出了各金属垫38的X方向的尺寸Fx、各金属垫38的Y方向的尺寸Fy、金属垫38间的X方向的间距Gx、金属垫38间的Y方向的间距Gy、金属垫38间的X方向的位移量Hx、金属垫38间的Y方向的位移量Hy。本实施方式中，它们的关系设定为Fx＝Fy、Gx＝Gy、Hx＝Hy。此外，本实施方式中，将尺寸设定为Cx＝Fx，间距设定为Dx≠Gx。
这样，在虚设区域R1c与虚设区域R1d之间，金属垫38的尺寸无论在X方向上还是在Y方向上均彼此相同，金属垫38间的间距彼此不同。结果，金属垫38的被覆率在虚设区域R1c与虚设区域R1d之间彼此不同。另外，在虚设区域R1c与虚设区域R1d之间，金属垫38的尺寸可彼此不同，金属垫38间的间距可彼此相同，由此，彼此的被覆率可不同。
另外，当制造本实施方式的半导体装置时，为了实现所述被覆率而在层间绝缘膜14内形成金属垫38(参照图3)。由此，有源区域R1a、虚设区域R1b、虚设区域R1c、虚设区域R1d内的被覆率分别设定为25％、25％、约20％、约10％。
作为决定本实施方式的虚设区域R1d内的金属垫38的配置的方法，可采用例如与虚设区域R1c的情况相同的方法。然而，因虚设区域R1c与虚设区域R1d中被覆率不同，所以图9的直线M1及M2延伸的方向与图10的直线N1及N2延伸的方向不同。根据本实施方式，通过将虚设区域R1d内的金属垫38排列的方向与虚设区域R1c内的金属垫38排列的方向错开，能够避免在半导体装置内金属垫38在相同的方向上连续排列。
图11是表示第1实施方式的虚设区域R1b与虚设区域R1c的边界附近的结构的俯视图。
如图11所示，在虚设区域R1b与虚设区域R1c的边界附近，金属垫38的布局发生变化。结果，金属垫38的被覆率在虚设区域R1b与虚设区域R1c之间发生变化。
图12是表示第1实施方式的虚设区域R1c与虚设区域R1d的边界附近的结构的俯视图。
本实施方式的电路晶圆W2包含沿着虚设区域R1c与虚设区域R1d的边界线(边界面)L配置成线状的多个金属垫38。由此，例如，能够抑制在虚设区域R1c与虚设区域R1d之间产生未配置有金属垫38的较大空间。通过抑制这种空间的产生，能够抑制在虚设区域R1c与虚设区域R1d之间产生空隙。
图13是表示第1实施方式的虚设区域R1d与切割区域R2的边界附近的结构的俯视图。
如图13所示，虚设区域R1d包含金属垫38，但切割区域R2不包含金属垫38。然而，虚设区域R1d内的被覆率设定得比有源区域R1a、虚设区域R1b及虚设区域R1c的被覆率低。由此，根据本实施方式，能够减小切割区域R2内产生的空隙V的深度。
图14是用于说明第1实施方式的电路晶圆W2的作用的剖视图。
图14(a)示出虚设区域R1d内的被覆率设定为25％时的空隙V。图14(b)示出虚设区域R1d内的被覆率约设定为10％时的空隙V。根据本实施方式，通过将虚设区域R1d内的被覆率设定得低，能够减小切割区域R2内产生的空隙V的深度。
如以上那样，本实施方式的金属垫38的被覆率在与切割区域R2分离的有源区域R1a、虚设区域R1b及虚设区域R1c和与切割区域R2相邻的虚设区域R1d中不同。例如，虚设区域R1d内的被覆率低于有源区域R1a、虚设区域R1b及虚设区域R1c内的被覆率。由此，根据本实施方式，能够抑制在嵌埋有金属垫38的层间绝缘膜14内产生大的空隙V等缺陷。关于这一点，阵列晶圆W1内的金属垫41及层间绝缘膜13也是相同的。
以上，对本发明的若干实施方式进行了说明，但这些实施方式仅作为例子而提出，并不意图限定发明的范围。本说明书中说明的新颖的装置及方法能够以其它多种方式实施。而且，可以在不脱离发明主旨的范围内对本说明书中说明的装置及方法的方式进行各种省略、置换、变更。随附的权利要求的范围及与其均等的范围旨在包括发明的范围或主旨中所包含的方式或变化例。
[符号的说明]
1 阵列芯片
2 电路芯片
11 存储单元阵列
12 绝缘膜
13 层间绝缘膜
14 层间绝缘膜
15 衬底
16 衬底
21 阶梯结构部
22 接触插塞
23 字配线层
24 介层插塞
31 晶体管
32 栅极电极
33 接触插塞
34 配线层
35 配线层
36 配线层
37 介层插塞
38 金属垫
41 金属垫
42 介层插塞
43 配线层
44 配线层
45 介层插塞
46 金属垫
47 钝化膜
51 绝缘层
52 阻挡绝缘膜
53 电荷蓄积层
54 隧道绝缘膜
55 信道半导体层
56 芯绝缘膜。

Claims (15)

1.一种半导体装置，包含：
第1芯片；及
第2芯片，与所述第1芯片贴合；
所述第1芯片包含：
衬底；
逻辑电路，设置于所述衬底上；及
多个第1虚设垫，配置于所述逻辑电路的上方，设置于所述第1芯片与所述第2芯片贴合而成的第1贴合面，且不与所述逻辑电路电连接；
所述第2芯片包含：
多个第2虚设垫，设置于所述多个第1虚设垫上；及
存储单元阵列，设置于所述多个第2虚设垫的上方；
所述第1贴合面中的所述第1虚设垫的被覆率在所述第1芯片的与第1端边分离的第1区域和配置于所述第1端边与所述第1区域之间的第2区域中不同。
2.一种半导体装置，包含：
第1晶圆；及
第2晶圆，与所述第1晶圆贴合；
所述第1晶圆包含：
第1衬底；
逻辑电路，设置于所述第1衬底上；及
多个第1虚设垫，配置于所述逻辑电路的上方，设置于所述第1晶圆与所述第2晶圆贴合而成的第1贴合面，且不与所述逻辑电路电连接；
所述第2晶圆包含：
多个第2虚设垫，设置于所述多个第1虚设垫上；及
存储单元阵列，设置于所述多个第2虚设垫的上方；
所述第1贴合面中的所述第1虚设垫的被覆率在所述第1晶圆的与切割区域分离的第1区域和配置于所述切割区域与所述第1区域之间的第2区域中不同。
3.根据权利要求2所述的半导体装置，其中
所述切割区域在所述第1贴合面中不包含所述第1虚设垫。
4.根据权利要求1至3中任一项所述的半导体装置，其中
所述第1区域内的所述被覆率为10～40％。
5.根据权利要求1至3中任一项所述的半导体装置，其中
所述第2区域内的所述被覆率为5～20％。
6.根据权利要求1至3中任一项所述的半导体装置，其中
所述第1区域内的所述被覆率与所述第2区域内的所述被覆率之比处于3：2与3：1之间。
7.根据权利要求1至3中任一项所述的半导体装置，其中
所述第2区域具有包围所述第1区域的环状形状。
8.根据权利要求1至3中任一项所述的半导体装置，其中
所述第1芯片或所述第1晶圆还包含：
多个第1有源垫，配置于所述逻辑电路的上方，设置于所述第1贴合面，且与所述逻辑电路电连接；
所述第2芯片或所述第2晶圆还包含：
多个第2有源垫，设置于所述多个第1有源垫上；
所述第1贴合面中的所述第1有源垫的被覆率在第3区域内为所述第1区域内的所述第1虚设垫的所述被覆率以上。
9.根据权利要求8所述的半导体装置，其中
所述第1区域包含：第1被覆率区域，具有与所述第3区域内的所述第1有源垫的所述被覆率相同的所述第1虚设垫的所述被覆率；及第2被覆率区域，具有小于所述第3区域内的所述第1有源垫的所述被覆率的所述第1虚设垫的所述被覆率。
10.根据权利要求9所述的半导体装置，其中
所述第1虚设垫包含沿着所述第1被覆率区域与所述第2被覆率区域的边界线配置成线状的多个虚设垫。
11.根据权利要求1至3中任一项所述的半导体装置，其中
所述第1区域内的所述第1虚设垫的尺寸与所述第2区域内的所述第1虚设垫的尺寸相同。
12.根据权利要求11所述的半导体装置，其中
所述第1区域内的所述第1虚设垫间的间距与所述第2区域内的所述第1虚设垫间的间距不同。
13.根据权利要求1至3中任一项所述的半导体装置，其中
所述第1区域内的所述第1虚设垫间的间距与所述第2区域内的所述第1虚设垫间的间距相同。
14.根据权利要求13所述的半导体装置，其中
所述第1区域内的所述第1虚设垫的尺寸与所述第2区域内的所述第1虚设垫的尺寸不同。
15.一种半导体装置的制造方法，包含：
在第1衬底上形成逻辑电路；
在所述逻辑电路的上方，形成不与所述逻辑电路电连接的多个第1虚设垫；
在第2衬底上形成存储单元阵列；
在所述存储单元阵列的上方形成多个第2虚设垫；及
通过将形成于所述第1衬底上的所述多个第1虚设垫与形成于所述第2衬底上的所述多个第2虚设垫贴合，在所述多个第1虚设垫上配置所述多个第2虚设垫；
所述多个第1虚设垫设置于包含所述第1衬底的第1晶圆与包含所述第2衬底的第2晶圆贴合而成的第1贴合面，
所述第1贴合面中的所述第1虚设垫的被覆率设定为在所述第1晶圆的与切割区域分离的第1区域和配置于所述切割区域与所述第1区域之间的第2区域中不同。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114326338A (zh) * 2021-12-31 2022-04-12 长江存储科技有限责任公司 半导体结构及其制备方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022041052A (ja) * 2020-08-31 2022-03-11 キオクシア株式会社 半導体装置およびその製造方法
EP4254470A1 (en) * 2022-03-24 2023-10-04 Micledi Microdisplays BV Semiconductor product and method for manufacturing a semiconductor product
WO2023179994A1 (en) * 2022-03-24 2023-09-28 Micledi Microdisplays Bv Semiconductor product and method for manufacturing a semiconductor product

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005072403A (ja) * 2003-08-27 2005-03-17 Sony Corp 半導体装置および半導体装置の製造方法
JP4338614B2 (ja) * 2004-09-29 2009-10-07 シャープ株式会社 半導体装置およびその製造方法
JP2006108541A (ja) * 2004-10-08 2006-04-20 Ricoh Co Ltd 半導体集積回路装置
JP5376916B2 (ja) 2008-11-26 2013-12-25 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
CN105938825B (zh) * 2011-05-24 2019-04-05 索尼公司 半导体图像接收装置
JP5919653B2 (ja) * 2011-06-09 2016-05-18 ソニー株式会社 半導体装置
TWI676279B (zh) * 2013-10-04 2019-11-01 新力股份有限公司 半導體裝置及固體攝像元件
US9281254B2 (en) * 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
JP6506536B2 (ja) * 2014-11-11 2019-04-24 キヤノン株式会社 半導体装置及びその製造方法、ならびにカメラ
US10050018B2 (en) * 2016-02-26 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC structure and methods of forming
JP2018148071A (ja) * 2017-03-07 2018-09-20 東芝メモリ株式会社 記憶装置
US10276481B2 (en) * 2017-06-26 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure having a plurality of conductive balls having narrow width for the ball waist
US10312201B1 (en) 2017-11-30 2019-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. Seal ring for hybrid-bond
US10727215B1 (en) * 2019-01-30 2020-07-28 Sandisk Technologies Llc Three-dimensional memory device with logic signal routing through a memory die and methods of making the same
JP2020150037A (ja) * 2019-03-11 2020-09-17 キオクシア株式会社 半導体装置およびその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114326338A (zh) * 2021-12-31 2022-04-12 长江存储科技有限责任公司 半导体结构及其制备方法
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