TWI429055B - 堆疊式封裝結構及其製造方法 - Google Patents

堆疊式封裝結構及其製造方法 Download PDF

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Publication number
TWI429055B
TWI429055B TW099134142A TW99134142A TWI429055B TW I429055 B TWI429055 B TW I429055B TW 099134142 A TW099134142 A TW 099134142A TW 99134142 A TW99134142 A TW 99134142A TW I429055 B TWI429055 B TW I429055B
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Taiwan
Prior art keywords
die
bumps
protective layer
substrate
wafer
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TW099134142A
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English (en)
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TW201216440A (en
Inventor
Jen Chuan Chen
Hui Shan Chang
You Cheng Lai
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Advanced Semiconductor Eng
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Priority to TW099134142A priority Critical patent/TWI429055B/zh
Priority to US13/253,816 priority patent/US20120086120A1/en
Publication of TW201216440A publication Critical patent/TW201216440A/zh
Application granted granted Critical
Publication of TWI429055B publication Critical patent/TWI429055B/zh

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Description

堆疊式封裝結構及其製造方法
本發明係關於一種封裝結構及其製造方法，詳言之，係關於一種堆疊式封裝結構及其製造方法。
堆疊式封裝結構係將二顆晶粒(下晶粒及上晶粒)堆疊在一基板上以形成之三維封裝結構，其中位於下方之下晶粒會具有複數個連通柱(Through Silicon Via,TSV)結構，該等連通柱會突出於該下晶粒之一表面，而且該下晶粒另一表面會具有複數個凸塊結構。因此，製造該堆疊式封裝結構之製程中會遭遇如下問題。
首先，在製程中，利用接合頭(Bonding Head)吸附該下晶粒時會傷害該等連通柱結構或該等凸塊結構。再者，目前該上晶粒及該下晶粒係為超薄，因此，如何吸附該等薄晶粒並且進行薄晶粒的覆晶堆疊是一項重大之挑戰。最後，由於該接合頭係在高溫環境下進行熱壓，因此該等連通柱結構或該等凸塊結構可能會因受熱軟化而沾黏到該接合頭。
因此，有必要提供一種堆疊式封裝結構及其製造方法，以解決上述問題。
本發明提供一種堆疊式封裝結構之製造方法，其包括以下步驟：(a)提供一第一晶圓，該第一晶圓包括一第一晶圓本體、複數個第一連通柱(Through Silicon Via,TSV)及複數個第一凸塊，該第一晶圓本體包括一第一表面及一第二表面，該等第一連通柱係突出於該第一表面，該等第一凸塊係鄰接於該第二表面且電性連接該等第一連通柱；(b)形成且固化一第一保護層於該等第一凸塊上，以覆蓋該等第一凸塊；(c)切割該第一晶圓，以形成複數個第一晶粒；(d)提供一第二晶圓，該第二晶圓包括一第二晶圓本體及複數個第二凸塊，該第二晶圓本體包括一第三表面及一第四表面，該等第二凸塊係鄰接於該第三表面，且該第四表面係相對於該第三表面；(e)形成一第二保護層於該等第二凸塊上，以覆蓋該等第二凸塊；(f)利用一接合頭(Bonding Head)透過該第一保護層吸附該等第一晶粒，且將該等第一晶粒接合於該第二晶圓上，其中該等第一連通柱係電性連接該等第二凸塊；(g)移除該接合頭，且移除部分該第一保護層以顯露該等第一凸塊；(h)切割該第二晶圓，以形成複數個第二晶粒；(i)提供一基板，該基板具有一上表面；(j)形成一第三保護層於該基板上表面；及(k)將該第一晶粒及該第二晶粒接合於該基板上表面，其中該等第一凸塊係電性連接該基板上表面。
本發明另提供一種堆疊式封裝結構之製造方法，其包括以下步驟：(a)提供一第一晶圓，該第一晶圓包括一第一晶圓本體、複數個第一連通柱及複數個第一凸塊，該第一晶圓本體包括一第一表面及一第二表面，該等第一連通柱係突出於該第一表面，該等第一凸塊係鄰接於該第二表面且電性連接該等第一連通柱；(b)形成且固化一第一保護層於該等第一連通柱上，以覆蓋該等第一連通柱；(c)切割該第一晶圓，以形成複數個第一晶粒；(d)提供一基板，該基板具有一上表面；(e)形成一第三保護層於該基板上表面；(f)利用一接合頭透過該第一保護層吸附該第一晶粒，且將該第一晶粒接合於該基板上，其中該第一凸塊係電性連接該基板上表面；(g)移除該接合頭，且移除部分該第一保護層以顯露該等第一連通柱；(h)提供一第二晶粒及一第二保護層，該第二晶粒包括一第二晶粒本體及複數個第二凸塊，該第二晶粒本體包括一第三表面及一第四表面，該等第二凸塊係鄰接於該第三表面，該第二保護層係位於該等第二凸塊上，以覆蓋該等第二凸塊；及(i)將該第二晶粒接合於該第一晶粒上，其中該等第二凸塊係電性連接該等第一連通柱。
藉此，該第一保護層可以保護該等第一凸塊或該等第一連通柱，而且該第一保護層還具有增加厚度及平坦化之作用，以利後續第一晶粒之吸附。
本發明另提供由上述方法所製得之封裝結構。
參考圖1至14，顯示本發明堆疊式封裝結構之製造方法之第一實施例之示意圖。參考圖1，提供一第一晶圓1及一膠帶(Tape)18。該第一晶圓1包括一第一晶圓本體10、複數個第一連通柱(Through Silicon Via,TSV)12及複數個第一凸塊13。該第一晶圓本體10包括一第一表面101及一第二表面102。該等第一連通柱12係貫穿該第一晶圓本體10，且該等第一連通柱12之一端121係突出於該第一表面101。該等第一凸塊13係鄰接於該第二表面102且電性連接該等第一連通柱12，在本實施例中，該等第一凸塊13係為銅柱(Copper Pillar)及焊料(Solder)之堆疊結構。在其他實施例中，該等第一凸塊13可僅為銅柱亦或是焊料。該膠帶18係鄰接該第一表面101以覆蓋且保護該等第一連通柱12之一端121。
較佳地，該第一晶圓1係為一處理器晶圓(Processor Wafer)，其更包括一絕緣層(Passivation Layer)14、一重佈層(RDL)15、一表面處理層(Surface Finish Layer)16及複數個第一銲墊17。該絕緣層14係位於該第一表面101，其材質例如苯環丁烯(Benzocyclobutene,BCB)、聚醯亞胺(polyimide，PI)等高分子材料；亦或是無機絕緣層，如：二氧化矽(SiO2 )。該重佈層15係位於該第二表面102。該等第一銲墊17係位於該重佈層15上，且該等第一凸塊13係位於該等第一銲墊17上。該表面處理層16係位於該等第一連通柱12突出之一端121。
參考圖2，形成且固化一第一保護層19於該等第一凸塊13上，以覆蓋且保護該等第一凸塊13。在本實施例中，該第一保護層19係為一非導電膜(Non Conductive Film,NCF)，其係為B階段材料(B-stage material)。該非導電膜在低溫下是硬的，在B階段溫度(B-stage temperature)時會變軟，而在超過B階段溫度後會固化(curing)。因此，該第一保護層19(此時該該第一保護層19係為一片材)係先貼附於該第一晶圓本體10第二表面102，之後加熱至B階段溫度使得該第一保護層19軟化而完全包覆住該等第一凸塊13，再持續加熱使得該第一保護層19固化。藉此，該第一保護層19除了可以保護該等第一凸塊13，而且該第一保護層19還具有增加厚度及平坦化之作用，以利後續之吸附。
參考圖3，切割該第一晶圓1，以形成複數個第一晶粒11。每一第一晶粒11包括一第一晶粒本體20、該等第一連通柱12及該等第一凸塊13。該第一晶粒本體20包括一第一表面201及一第二表面202。此時，該第一保護層19係一起被切割，而切割後之該第一晶粒11及該第一保護層19仍附著於該膠帶18上。
參考圖4，提供一第二晶圓2及一載體3。該第二晶圓2包括一第二晶圓本體21及複數個第二凸塊23。該第二晶圓本體21包括一第三表面211及一第四表面212。該等第二凸塊23係鄰接於該第三表面211，且該第四表面212係貼附該載體3。在本實施例中，該第二晶圓2係為一記憶體晶圓(Memory Wafer)，該等第二凸塊23係為銲料(Solder)。此外，該第二晶圓本體21更包括複數個第二銲墊22，其鄰接於該第三表面211，且該等第二凸塊23係位於該等第二銲墊22上。該第四表面212係利用一黏膠層31貼附於該載體3上。
參考圖5，形成一第二保護層32於該等第二凸塊23上，以覆蓋該等第二凸塊23。在本實施例中，該第二保護層32係為一非導電膜或一底膠(Underfill)。
參考圖6，利用一接合頭24吸附該第一晶粒11，由於該第一晶粒11上有該第一保護層19，因此該接合頭24係透過該第一保護層19吸附該第一晶粒11，而且該等第一凸塊13係被該第一保護層19保護住而不會直接接觸到該接合頭24。
參考圖7，將該等第一晶粒11接合於該第二晶圓2上，其中該等第一連通柱12係接觸且電性連接該等第二凸塊23。之後，移除該接合頭24，且移除部分該第一保護層19以顯露該等第一凸塊13。在本實施例中，係以灰化(Ashing)方式移除部分該第一保護層19，使得該第一保護層19變薄並顯露該等第一凸塊13。
參考圖8，移除該載體3及該黏膠層31。參考圖9，切割該第二晶圓2，以形成複數個第二晶粒25。該第二晶粒25包括一第二晶粒本體26及該等第二凸塊23。該第二晶粒本體26包括一第三表面261及一第四表面262，該等第二凸塊23係鄰接於該第三表面261。
參考圖10，提供一基板4，例如一有機基板(Organic Substrate)。該基板4具有一上表面41。之後，形成一第三保護層42於該基板4上表面41。在本實施例中，該第三保護層42係為一非導電膜或一底膠(Underfill)。
參考圖11，將圖9中已堆疊之該第一晶粒11及該第二晶粒25再接合於該基板4上表面41，其中該等第一凸塊13係接觸且電性連接該基板4上表面41。
在其他實施例中，亦可先將已堆疊之該第一晶粒11及該第二晶粒25接合於該基板4上表面41後再形成一第三保護層42於該基板4及該第一晶粒11間。
接著，切割該基板4以形成複數個堆疊式封裝結構5。或者，如圖12所示，可先形成一封膠材料51於該基板4上表面41以包覆該第一晶粒11及該第二晶粒25，之後再切割該基板4以形成複數個堆疊式封裝結構5。
參考圖13，其顯示當圖4之該第二晶圓2為複數個時，最終堆疊式封裝結構6之示意圖，其中每一第二晶圓2具有複數個第二連通柱263。該等第二晶圓2係堆疊在一起，且利用該等第二連通柱263、該等第二凸塊23及該等第二銲墊22彼此電性連接。該等堆疊第二晶圓2切割後形成複數個堆疊第二晶粒25。此外，該堆疊式封裝結構6更包括複數個銲球61，位於該基板4下表面。或者，如圖14所示，可先形成一封膠材料62於該基板4上表面41以包覆該第一晶粒11及該等堆疊第二晶粒25，之後再切割該基板4以形成複數個堆疊式封裝結構6。
參考圖11，顯示本發明堆疊式封裝結構之第一實施例之示意圖。該堆疊式封裝結構5包括一基板4、一第一晶粒11、一第一保護層19、一第三保護層42、一第二晶粒25及一第二保護層32。
該基板4(例如一有機基板)具有一上表面41。該第一晶粒11接合於該基板4。該第一晶粒11包括一第一晶粒本體20、複數個第一連通柱12及複數個第一凸塊13。該第一晶粒本體20包括一第一表面201及一第二表面202。該等第一連通柱12係貫穿該第一晶粒本體20，且該等第一連通柱12之一端121係突出於該第一表面201。該等第一凸塊13係鄰接於該第二表面202且電性連接該等第一連通柱12，且該等第一凸塊13係電性連接該基板4上表面41。在本實施例中，該等第一凸塊13係為銅柱。
較佳地，該第一晶粒11係為一處理器晶粒(Processor Die)，其更包括一絕緣層14、一重佈層15、一表面處理層16及複數個第一銲墊17。該絕緣層14係位於該第一表面201，其材質例如是苯環丁烯(Benzocyclobutene，BCB)、聚醯亞胺(polyimide，PI)等高分子材料；亦或是無機絕緣層，如：二氧化矽(SiO2 )。該重佈層15係位於該第二表面202。該等第一銲墊17係位於該重佈層15上，且該等第一凸塊13係位於該等第一銲墊17上。該表面處理層16係位於該等第一連通柱12突出之一端121。
該第一保護層19鄰接於該第二表面202，且該等第一凸塊13係突出於該第一保護層19之外。該第三保護層42係位於該基板4上表面41及該第一保護層19之間，以保護該等第一凸塊13。在本實施例中，該第一保護層19及該第三保護層42係為非導電膜。在其他實施例中，該第一保護層19係為非導電膜而該第三保護層42係為一底膠(Underfill)。
該第二晶粒25係接合於該第一晶粒11。該第二晶粒25包括一第二晶粒本體26及複數個第二凸塊23。該第二晶粒本體26包括一第三表面261及一第四表面262，該等第二凸塊23係鄰接於該第三表面261，且該等第二凸塊23係電性連接該等第一連通柱12。
在本實施例中，該第二晶粒25係為一記憶體晶粒(Memory Die)，該等第二凸塊23係為銲料。此外，該第二晶粒本體26更包括該等第二銲墊22，其鄰接於該第三表面261，且該等第二凸塊23係位於該等第二銲墊22上。
該第二保護層32係位於該第一晶粒11第一表面201及該第二晶粒25第三表面261之間，以保護該等第二凸塊23。在本實施例中，該第二保護層32係為一非導電膜或一底膠(Underfill)。
參考圖12，該堆疊式封裝結構5更包括一封膠材料51，位於該基板4上表面41，以包覆該第一晶粒11及該第二晶粒25。
參考圖13，顯示本發明堆疊式封裝結構之第一實施例之另一種態樣示意圖。在該堆疊式封裝結構6中，該第二晶粒25係為複數個，每一第二晶粒25具有複數個第二連通柱263。該等第二晶粒25係堆疊在一起，且利用該等第二連通柱263、該等第二凸塊23及該等第二銲墊22彼此電性連接。
參考圖14，該堆疊式封裝結構6更包括一封膠材料62，位於該基板4上表面41，以包覆該第一晶粒11及該等堆疊第二晶粒25。
參考圖15至22，顯示本發明堆疊式封裝結構之製造方法之第二實施例之示意圖。參考圖15，提供一第一晶圓1及一膠帶18。該第一晶圓1包括一第一晶圓本體10、複數個第一連通柱12及複數個第一凸塊13。該第一晶圓本體10包括一第一表面101及一第二表面102。該等第一連通柱12係貫穿該第一晶圓本體10，且該等第一連通柱12之一端121係突出於該第一表面101。該等第一凸塊13係鄰接於該第二表面102且電性連接該等第一連通柱12，在本實施例中，該等第一凸塊13係為銅柱。該膠帶18係鄰接該第二表面102以覆蓋該等第一凸塊13。
較佳地，該第一晶圓1更包括一絕緣層14、一重佈層15、一表面處理層16及複數個第一銲墊17。該絕緣層14係位於該第一表面101，其材質例如是苯環丁烯(Benzocyclobutene,BCB)、聚醯亞胺(polyimide，PI)等高分子材料；亦或是無機絕緣層，如：二氧化矽(SiO2 )。該重佈層15係位於該第二表面102。該等第一銲墊17係位於該重佈層15上，且該等第一凸塊13係位於該等第一銲墊17上。該表面處理層16係位於該等第一連通柱12突出之一端121。
參考圖16，形成且固化一第一保護層19於該等第一連通柱12突出之一端121上，以覆蓋該等第一連通柱12。在本實施例中，該第一保護層19係為一非導電膜。
參考圖17，切割該第一晶圓1，以形成複數個第一晶粒11。每一第一晶粒11包括一第一晶粒本體20、該等第一連通柱12及該等第一凸塊13。該第一晶粒本體20包括一第一表面201及一第二表面202。此時，該第一保護層19係一起被切割，而切割後之該第一晶粒11及該第一保護層19仍附著於該膠帶18上。
參考圖18，提供一基板4，該基板4具有一上表面41。接著，形成一第三保護層42於該基板4上表面41。在本實施例中，該第三保護層42係為一非導電膜或一底膠(Underfill)。接著，利用一接合頭24透過該第一保護層19吸附該第一晶粒11，並分離該第一晶粒11及該膠帶18，且將該第一晶粒11接合於該基板4上，其中該第一凸塊13係接觸且電性連接該基板4上表面41。
在其他實施例中，亦可先將該第一晶粒11接合於該基板4上表面41後再形成一第三保護層42於該基板4及該第一晶粒11間。
參考圖19，移除該接合頭24，且移除部分該第一保護層19使該第一保護層19變薄，以顯露該等第一連通柱12突出之一端121。
參考圖20，提供一第二晶粒25及一第二保護層32。該第二晶粒25包括一第二晶粒本體26及複數個第二凸塊23。該第二晶粒本體26包括複數個一第三表面261及一第四表面262。該等第二凸塊23係鄰接於該第三表面261。該第二保護層32係位於該等第二凸塊23上，以覆蓋該等第二凸塊23。在本實施例中，該等第二凸塊23係為銲料。此外，該第二晶粒本體26更包括複數個第二銲墊22，其鄰接於該第三表面261，且該等第二凸塊23係位於該等第二銲墊22上。該第二保護層32係位於該等第二凸塊23上，以覆蓋該等第二凸塊23。在本實施例中，該第二保護層32係為一非導電膜或一底膠。
在其他實施例中，亦可先將該第二保護層32覆蓋於第一晶粒11之該第一保護層19上。
參考圖21，將該第二晶粒25接合於該第一晶粒11上，其中該等第二凸塊23係接觸且電性連接該等第一連通柱12。接著，切割該基板4以形成複數個堆疊式封裝結構7。或者，如圖22所示，可先形成一封膠材料71於該基板4上表面41以包覆該第一晶粒11及該第二晶粒25，之後再切割該基板4以形成複數個堆疊式封裝結構7。
同樣地，在圖21中，該第二晶粒25也可以為複數個，每一第二晶粒具有複數個第二連通柱，且該等第二晶粒25係堆疊在一起。
參考圖21，顯示本發明封裝結構之第二實施例之示意圖。本實施例之封裝結構7與第一實施例之封裝結構5(圖11)大致相同，其中相同之元件賦予相同之編號。本實施例與第一實施例不同處在於該第一保護層19之位置。在本實施例中，該第一保護層19係鄰接於該第一晶粒本體20第一表面201，且該等第一連通柱12係突出於該第一保護層19之外。該第二保護層32位於該第一保護層19及該第二晶粒26第三表面261之間，以保護該等第二凸塊23。第三保護層42係位於該基板4上表面41及該第一晶粒本體20第二表面202之間，以保護該等第一凸塊13。
在本發明中，該第一保護層19可以保護該等第一凸塊13(第一實施例)或該等第一連通柱12(第二實施例)，而且該第一保護層19還具有增加厚度及平坦化之作用，以利後續第一晶粒11之吸附。
惟上述實施例僅為說明本發明之原理及其功效，而非用以限制本發明。因此，習於此技術之人士對上述實施例進行修改及變化仍不脫本發明之精神。本發明之權利範圍應如後述之申請專利範圍所列。
1．．．第一晶圓
2．．．第二晶圓
3．．．載體
4．．．基板
5．．．堆疊式封裝結構
6．．．堆疊式封裝結構
7．．．堆疊式封裝結構
10．．．第一晶圓本體
11．．．第一晶粒
12．．．第一連通柱
13．．．第一凸塊
14．．．絕緣層
15．．．重佈層
16．．．表面處理層
17．．．第一銲墊
18．．．膠帶
19．．．第一保護層
20．．．第一晶粒本體
21．．．第二晶圓本體
22．．．第二銲墊
23．．．第二凸塊
24．．．接合頭
25．．．第二晶粒
26．．．第二晶粒本體
31．．．黏膠層
32．．．第二保護層
41．．．基板上表面
42．．．第三保護層
51．．．封膠材料
61．．．銲球
62．．．封膠材料
71．．．封膠材料
101．．．第一表面
102．．．第二表面
121．．．第一連通柱之一端
201．．．第一表面
202．．．第二表面
211．．．第三表面
212．．．第四表面
261．．．第三表面
262．．．第四表面
263．．．第二連通柱
圖1至14顯示本發明堆疊式封裝結構之製造方法之第一實施例之示意圖；及
圖15至22顯示本發明堆疊式封裝結構之製造方法之第二實施例之示意圖。
4．．．基板
5．．．堆疊式封裝結構
11．．．第一晶粒
12．．．第一連通柱
13．．．第一凸塊
14．．．絕緣層
15．．．重佈層
16．．．表面處理層
17．．．第一銲墊
19．．．第一保護層
20．．．第一晶粒本體
22．．．第二銲墊
23．．．第二凸塊
25．．．第二晶粒
26．．．第二晶粒本體
32．．．第二保護層
41．．．基板上表面
42．．．第三保護層
121．．．第一連通柱之一端
201．．．第一表面
202．．．第二表面
261‧‧‧第三表面
262‧‧‧第四表面

Claims (19)

  1. 一種堆疊式封裝結構之製造方法，包括：(a)　提供一第一晶圓，該第一晶圓包括一第一晶圓本體、複數個第一連通柱(Through Silicon Via,TSV)及複數個第一凸塊，該第一晶圓本體包括一第一表面及一第二表面，該等第一連通柱係突出於該第一表面，該等第一凸塊係鄰接於該第二表面且電性連接該等第一連通柱；(b)　形成且固化一第一保護層於該等第一凸塊上，以覆蓋該等第一凸塊；(c)　切割該第一晶圓，以形成複數個第一晶粒；(d)　提供一第二晶圓，該第二晶圓包括一第二晶圓本體及複數個第二凸塊，該第二晶圓本體包括一第三表面及一第四表面，該等第二凸塊係鄰接於該第三表面，且該第四表面係相對於該第三表面；(e)　形成一第二保護層於該等第二凸塊上，以覆蓋該等第二凸塊；(f)　利用一接合頭(Bonding Head)透過該第一保護層吸附該等第一晶粒，且將該等第一晶粒接合於該第二晶圓上，其中該等第一連通柱係電性連接該等第二凸塊；(g)　移除該接合頭，且移除部分該第一保護層以顯露該等第一凸塊；(h)　切割該第二晶圓，以形成複數個第二晶粒；(i)　提供一基板，該基板具有一上表面；(j)　形成一第三保護層於該基板上表面；及(k)　將該第一晶粒及該第二晶粒接合於該基板上表面，其中該等第一凸塊係電性連接該基板上表面。
  2. 如請求項1之方法，其中該步驟(a)中，該等第一連通柱突出之一端具有一表面處理層。
  3. 如請求項1之方法，其中該步驟(a)中，該第一晶圓更包括一絕緣層(Passivation Layer)及一重佈層(RDL)，該絕緣層係位於該第一表面，且該重佈層係位於該第二表面。
  4. 如請求項1之方法，其中該等第一凸塊係包含銅柱(Copper Pillar)，該等第二凸塊係為銲料(Solder)。
  5. 如請求項1之方法，其中該第一保護層係為一非導電膜(Non Conductive Film,NCF)，該第二保護層及該第三保護層係為一非導電膜或一底膠(Underfill)。
  6. 如請求項1之方法，其中該步驟(d)中，該第二晶圓係為複數個，每一第二晶圓具有複數個第二連通柱，且該等第二晶圓係堆疊在一起。
  7. 如請求項1之方法，其中該步驟(k)之後更包括一形成一封膠材料於該基板上表面以包覆該第一晶粒及該第二晶粒之步驟。
  8. 一種堆疊式封裝結構之製造方法，包括：(a)　提供一第一晶圓，該第一晶圓包括一第一晶圓本體、複數個第一連通柱及複數個第一凸塊，該第一晶圓本體包括一第一表面及一第二表面，該等第一連通柱係突出於該第一表面，該等第一凸塊係鄰接於該第二表面且電性連接該等第一連通柱；(b)　形成且固化一第一保護層於該等第一連通柱上，以覆蓋該等第一連通柱；(c)　切割該第一晶圓，以形成複數個第一晶粒；(d)　提供一基板，該基板具有一上表面；(e)　形成一第三保護層於該基板上表面；(f)　利用一接合頭透過該第一保護層吸附該第一晶粒，且將該第一晶粒接合於該基板上，其中該第一凸塊係電性連接該基板上表面；(g)　移除該接合頭，且移除部分該第一保護層以顯露該等第一連通柱；(h)　提供一第二晶粒及一第二保護層，該第二晶粒包括一第二晶粒本體及複數個第二凸塊，該第二晶粒本體包括一第三表面及一第四表面，該等第二凸塊係鄰接於該第三表面，該第二保護層係位於該等第二凸塊上，以覆蓋該等第二凸塊；及(i)　將該第二晶粒接合於該第一晶粒上，其中該等第二凸塊係電性連接該等第一連通柱。
  9. 如請求項8之方法，其中該第一保護層係為一非導電膜，該第二保護層係為一非導電膜或一底膠，且該第三保護層係為一非導電膜或一底膠。
  10. 如請求項8之方法，其中該步驟(h)中，該第二晶粒係為複數個，每一第二晶粒具有複數個第二連通柱，且該等第二晶粒係堆疊在一起。
  11. 如請求項8之方法，其中該步驟(i)之後更包括一形成一封膠材料於該基板上表面以包覆該第一晶粒及該第二晶粒之步驟。
  12. 一種堆疊式封裝結構，包括：一基板，具有一上表面；一第一晶粒，接合於該基板，該第一晶粒包括一第一晶粒本體、複數個第一連通柱及複數個第一凸塊，該第一晶粒本體包括一第一表面及一第二表面，該等第一連通柱係突出於該第一表面，該等第一凸塊係鄰接於該第二表面且電性連接該等第一連通柱，且該等第一凸塊係電性連接該基板上表面；一第一保護層，鄰接於該第二表面，且該等第一凸塊係突出於該第一保護層之外；一第三保護層，位於該基板上表面及該第一保護層之間，以保護該等第一凸塊；一第二晶粒，接合於該第一晶粒，該第二晶粒包括一第二晶粒本體及複數個第二凸塊，該第二晶粒本體包括一第三表面及一第四表面，該等第二凸塊係鄰接於該第三表面，且該等第二凸塊係電性連接該等第一連通柱；及一第二保護層，位於該第一晶粒第一表面及該第二晶粒第三表面之間，以保護該等第二凸塊。
  13. 如請求項12之堆疊式封裝結構，其中該等第一連通柱係貫穿該第一晶粒本體。
  14. 如請求項12之堆疊式封裝結構，其中該等第一連通柱突出之一端具有一表面處理層。
  15. 如請求項12之堆疊式封裝結構，其中該第一晶粒更包括一絕緣層及一重佈層，該絕緣層係位於該第一表面，且該重佈層係位於該第二表面。
  16. 如請求項12之堆疊式封裝結構，其中該等第一凸塊係包含銅柱，該等第二凸塊係為銲料。
  17. 如請求項12之堆疊式封裝結構，其中該第一保護層係為一非導電膜，該第二保護層係為一非導電膜或一底膠，且該第三保護層係為一非導電膜或一底膠。
  18. 如請求項12之堆疊式封裝結構，其中該第二晶粒係為複數個，每一第二晶粒具有複數個第二連通柱，且該等第二晶粒係堆疊在一起。
  19. 一種堆疊式封裝結構，包括：一基板，具有一上表面；一第一晶粒，接合於該基板，該第一晶粒包括一第一晶粒本體、複數個第一連通柱及複數個第一凸塊，該第一晶粒本體包括一第一表面及一第二表面，該等第一連通柱係突出於該第一表面，該等第一凸塊係鄰接於該第二表面且電性連接該等第一連通柱，且該等第一凸塊係電性連接該基板上表面；一第三保護層，位於該基板上表面及該第一晶粒本體第二表面之間，以保護該等第一凸塊；一第一保護層，鄰接於該第一晶粒本體第一表面，且該等第一連通柱係突出於該第一保護層之外；一第二晶粒，接合於該第一晶粒，該第二晶粒包括一第二晶粒本體及複數個第二凸塊，該第二晶粒本體包括一第三表面及一第四表面，該等第二凸塊係鄰接於該第三表面，且該等第二凸塊係電性連接該等第一連通柱；及一第二保護層，位於該第一保護層及該第二晶粒第三表面之間，以保護該等第二凸塊。
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US8623763B2 (en) * 2011-06-01 2014-01-07 Texas Instruments Incorporated Protective layer for protecting TSV tips during thermo-compressive bonding
JP5994167B2 (ja) * 2011-11-15 2016-09-21 ローム株式会社 半導体装置およびその製造方法、電子部品
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US10651116B2 (en) 2016-06-30 2020-05-12 Intel Corporation Planar integrated circuit package interconnects
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US5144407A (en) * 1989-07-03 1992-09-01 General Electric Company Semiconductor chip protection layer and protected chip
US6800930B2 (en) * 2002-07-31 2004-10-05 Micron Technology, Inc. Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies
JP3990347B2 (ja) * 2003-12-04 2007-10-10 ローム株式会社 半導体チップおよびその製造方法、ならびに半導体装置
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US7772116B2 (en) * 2005-09-01 2010-08-10 Micron Technology, Inc. Methods of forming blind wafer interconnects
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