KR101334220B1 - 버팅 콘택 방식을 이용한 웨이퍼 간의 전기적 연결방법 및 이를 이용하여 구현한 반도체 장치 - Google Patents

버팅 콘택 방식을 이용한 웨이퍼 간의 전기적 연결방법 및 이를 이용하여 구현한 반도체 장치 Download PDF

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KR101334220B1
KR101334220B1 KR1020120129899A KR20120129899A KR101334220B1 KR 101334220 B1 KR101334220 B1 KR 101334220B1 KR 1020120129899 A KR1020120129899 A KR 1020120129899A KR 20120129899 A KR20120129899 A KR 20120129899A KR 101334220 B1 KR101334220 B1 KR 101334220B1
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South Korea
Prior art keywords
wafer
butting contact
contact hole
bonding
conductive region
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KR1020120129899A
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English (en)
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전인균
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(주)실리콘화일
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Priority to KR1020120129899A priority Critical patent/KR101334220B1/ko
Priority to US14/079,075 priority patent/US8906781B2/en
Priority to JP2013235660A priority patent/JP2014103395A/ja
Priority to EP13005391.1A priority patent/EP2733736A3/en
Priority to CN201310573253.3A priority patent/CN103824867B/zh
Application granted granted Critical
Publication of KR101334220B1 publication Critical patent/KR101334220B1/ko

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Abstract

본 발명은 해결하고자 하는 기술적 과제는, 웨이퍼의 접합을 물리적인 접합과 전기적인 접합으로 구분하여, 물리적인 접합은 비교적 쉬운 공정인 산화막 공정을 이용하고, 전기적인 접합은 TSV 또는 버팅 콘택기술을 이용함으로써, 추가 공정이 단순한 버팅 콘택 방식을 이용한 웨이퍼 간의 전기적 연결방법 및 웨이퍼 간의 전기적 연결방법을 이용하여 제조한 반도체 장치를 개시(introduce)한다. 상기 웨이퍼 간의 전기적 연결방법은, 일련의 공정이 완료된 제1웨이퍼 및 제2웨이퍼를 버팅 콘택 방식을 이용하여 상기 제1웨이퍼 및 상기 제2웨이퍼를 전기적으로 연결하는 것으로, 물리적 접합단계 및 전기적 접합단계를 포함한다. 상기 물리적 접합단계는 산화막 접합 방식으로 상기 제1웨이퍼와 상기 제2웨이퍼를 물리적으로 접합한다. 상기 전기적 접합단계는 상기 제1웨이퍼의 제1전도영역과 이에 대응되는 상기 제2웨이퍼의 제2전도영역의 전기적 연결은 TSV 또는 버팅 콘택을 이용한 메탈 접합 방식으로 연결한다.

Description

버팅 콘택 방식을 이용한 웨이퍼 간의 전기적 연결방법 및 이를 이용하여 구현한 반도체 장치 {Method for electric connecting the wafers using butting contact and semiconductor device manufactured by the method}
본 발명은 2개의 웨이퍼를 전기적으로 연결하는 방법에 관한 것으로, 특히, 산화막 접합 방식으로 물리적으로 접합한 후 버팅 콘택을 이용하여 전기적으로 연결하는 웨이퍼 간의 전기적 연결방법에 관한 것이다.
기술이 발달함에 따라 웨이퍼 상에서 소자의 크기를 감소시킴으로써 집적회로의 물리적 크기를 감소시키는 것은 한계에 이르렀다. 이를 해소하기 위하여 적어도 2개의 웨이퍼를 상하로 적층하여 접합하는 방식이 제안되어 사용된다.
도 1은 종래의 메탈 접합방식에 따라 제조된 반도체 장치의 단면을 나타낸다.
설명의 편의를 위해, 도 1에 도시된 반도체 장치는 이미지센서의 일부라고 가정한다. 상부의 웨이퍼(110)에는 상부로부터 입사되는 빛의 양에 대응하는 전하를 생성하는 포토다이오드(PD) 및 상기 전하들이 일시 저장되는 부유확산영역(FD)이 구현되어 있으며, 하부의 웨이퍼(120)에는 이미지센서를 구성하는 구성요소들 중 포토다이오드(PD)를 제외한 나머지 요소들이 구현되어 있다.
도 1을 참조하면, 각각 다른 소자들이 구현된 2개의 웨이퍼가 접합되어 있다. 여기서, A, B, C 및 D 영역은 전도성 물질인 메탈 또는 다결정 실리콘이 형성되어 있는 곳을 의미한다. 상부의 웨이퍼(110)에 형성된 A영역 및 C영역은 하부의 웨이퍼(120)에 형성된 B영역 및 D영역과 전기적으로 각각 연결되어야 한다.
반도체 제조공정이 완료되었을 때, 웨이퍼의 상부 표면은 절연물질로 덮혀지게 되기 때문에 2개의 웨이퍼의 상부표면을 물리적으로 접합하는 경우, 2개의 웨이퍼는 전기적으로는 절연된다. 그렇기 때문에, 2개의 웨이퍼의 전기적 연결을 위해서는 접합되는 부분에는 전도성 물질이 형성되어 있어야 하며 또한 이들이 서로 물리적으로 접하여야 한다.
도 1을 참조하면, 상부의 웨이퍼(110)에 형성된 A영역 및 C영역의 경우 표면영역에는 구리(Cu)와 같은 전도성 물질이 형성되어 있으며, 하부의 웨이퍼(120)에 형성된 B영역 및 D영역의 경우도 동일하다.
상술한 바와 같이, 종래의 메탈접합(metal to metal bonding) 방식은, 상부의 웨이퍼(110) 및 상부의 웨이퍼(120)의 A영역 내지 D영역의 표면영역에 구리(Cu)를 이용하여 형성시킨 도전층의 경우, 순전히 2 웨이처(110, 120)의 전기적 연결을 위해 형성시킨 것으로, 웨이퍼의 두께가 증가하는 단점을 유발시킨다. 웨이퍼의 두께가 증가하면 증가할 수록, 2개의 웨이퍼(110, 120)에 형성된 소자들 사이의 전기적 연결 배선의 길이가 길어지게 되며, 이들 배선의 저항에 따른 전력 손실 등을 무시할 수 없게 된다.
또한 각 웨이퍼를 제조하는 공정에서 접합시 전기전도에 필요한 도전층을 형성시키는 공정을 각각 수행하여야 하므로, 공정수행에 소요되는 시간도 증가하게 되는 단점이 있다.
본 발명이 해결하고자 하는 기술적 과제는, 웨이퍼의 접합을 물리적인 접합과 전기적인 접합으로 구분하여, 물리적인 접합은 비교적 쉬운 공정인 산화막 공정을 이용하고, 전기적인 접합은TSV 또는 버팅 콘택기술을 이용함으로써, 추가 공정이 단순한 버팅 콘택 방식을 이용한 웨이퍼 간의 전기적 연결방법을 제공하는 것에 있다.
본 발명이 해결하고자 하는 다른 기술적 과제는, 웨이퍼의 접합을 물리적인 접합과 전기적인 접합으로 구분하여, 물리적인 접합은 비교적 쉬운 공정인 산화막 공정을 이용하고, 전기적인 접합은 TSV 또는 버팅 콘택기술을 이용함으로써, 추가 공정이 단순한 버팅 콘택 방식을 이용한 웨이퍼 간의 전기적 연결방법을 이용하여 제조한 반도체 장치를 제공하는 것에 있다.
상기 기술적 과제를 달성하기 위한 본 발명에 따른 웨이퍼 간의 전기적 연결방법은, 일련의 공정이 완료된 제1웨이퍼 및 제2웨이퍼를 버팅 콘택 방식을 이용하여 상기 제1웨이퍼 및 상기 제2웨이퍼를 전기적으로 연결하는 것으로, 물리적 접합단계 및 전기적 접합단계를 포함한다. 상기 물리적 접합단계는 산화막 접합 방식으로 상기 제1웨이퍼와 상기 제2웨이퍼를 물리적으로 접합한다. 상기 전기적 접합단계는 상기 제1웨이퍼의 제1전도영역과 이에 대응되는 상기 제2웨이퍼의 제2전도영역의 전기적 연결은 TSV 또는 버팅 콘택을 이용한 메탈 접합 방식으로 연결한다.
상기 다른 기술적 과제를 달성하기 위한 본 발명에 따른 반도체 장치는, 청구항 제1항의 방법을 이용하여 전기적으로 연결한 제1웨이퍼 및 제2웨이퍼를 이용하여 구현한 반도체 장치이며, 상기 제1웨이퍼에는 CMOS 이미지 센서를 구성하는 복수 개의 구성요소 중 적어도 하나가 구현되며, 상기 제2웨이퍼에는 상기 CMOS 이미지 센서를 구성하는 복수 개의 구성요소 중 상기 제1웨이퍼에 구현된 요소를 제외한 나머지 요소 및 픽셀 구동회로가 구현된다.
본 발명에 따른 웨이퍼 간의 전기적 연결방법 및 이에 따라 제조된 반도체 장치는, 산화막 접합(oxide to oxide bonding)이라는 메탈 접합(metal to metal bonding)에 비해 상대적으로 간단한 기술로 웨이퍼를 물리적으로 접합한 후, TSV 및 버팅 콘택홀 기술을 이용하여 웨이퍼 사이의 전기적 연결을 수행하기 때문에, 공정을 단순화 시킬 수 있어, 공정 상의 오류 및 제품 수율의 향상을 도모할 수 있는 장점이 있다.
도 1은 종래의 메탈 접합방식에 따라 제조된 반도체 장치의 단면을 나타낸다.
도 2는 본 발명에 따른 웨이퍼 간의 전기적 연결방법에 따라 제조된 반도체 장치의 단면을 나타낸다.
도 3(a)는 2개의 웨이퍼에 대하여 물리적 접합이 진행된 결과를 나타낸다.
도 3(b)는 제1웨이퍼의 기판으로부터 제1전도영역까지 형성된 제1버팅 콘택홀을 나타낸다.
도 3(c)는 제1전도영역으로부터 제2전도영역까지 형성된 제2버팅 콘택홀을 나타낸다.
본 발명과 본 발명의 동작상의 이점 및 본 발명의 실시에 의하여 달성되는 목적을 충분히 이해하기 위해서는 본 발명의 예시적인 실시 예를 설명하는 첨부 도면 및 첨부 도면에 기재된 내용을 참조하여야만 한다.
이하 첨부한 도면을 참조하여 본 발명의 바람직한 실시 예를 설명함으로써, 본 발명을 상세히 설명한다. 각 도면에 제시된 동일한 참조부호는 동일한 부재를 나타낸다.
도 2는 본 발명에 따른 웨이퍼 간의 전기적 연결방법에 따라 제조된 반도체 장치의 단면을 나타낸다.
도 2를 참조하면, 본 발명에 따른 반도체 장치는 물리적인 접합은 산화막 접합(oxide to oxide bonding)으로 구현되었다. 이는 표면이 산화막(oxide)으로 덮혀져 있는 상부의 웨이퍼(210)와 하부의 웨이퍼(220)를 물리적으로 접합하였다는 것을 의미한다. 따라서 2개의 웨이퍼(210, 220)는 전기적으로는 서로 절연되어 있다. 이 방식은 접합 시의 2 웨이퍼(210, 220)의 정렬만을 고려하면 되므로, 접합이 비교적 용이하게 구현될 수 있다.
도 2에서는 2개의 웨이퍼(210, 220) 사이의 접합이 산화막 접합(oxide to oxide bonding) 방식에 의한 것으로 도시하였으나 이는 예시적인 것이며 산화막 접합(oxide to oxide bonding) 방식이 아닌 다른 절연막 접합 방식으로도 접합할 수 있음은 당연하다.
도 1에 도시된 종래의 경우에는 2개의 웨이퍼(110, 120)가 접합되는 부분이 도전체(Cu)와 산화막(oxide)으로 구분되어 있으나, 도 2에 도시된 본 발명의 경우 2개의 웨이퍼(210, 220)가 접합되는 전체 부분이 산화막으로 되어 있다. 도 2에서 F영역은 물리적인 접합이 이루어진 다음 형성되는 버팅 컨택홀(butting contact hole)로써, 이에 대해서는 후술한다.
제1웨이퍼(210)의 기판을 관통하여 제1전도영역(A, C)에 형성된 제1버팅 콘택홀(E)과 제1전도영역(A, C)와 제2전도영역(B, D) 사이에 형성된 제2버팅 콘택홀(F)에 의해서 제1웨이퍼(210)에 형성된 제1전도영역(A, C)은 제2웨이퍼(220)에 형성된 제2전도영역(B, D)과 전기적으로 연결된다.
여기서, 제1버팅 콘택홀(E)에는 절연물질이 충진되어 있고, 제2버팅 콘택홀(F)에는 전도물질을 충진함으로써, 필요한 부분만 전기적으로 연결하도록 할 수 있다.
도 1에는 제1버팅 콘택홀(E)의 단면적이 제2버팅 콘택홀(F)의 단면적에 비해서 큰 것으로 표시되어 있지만, 단면적이 동일한 형태도 가능하다. 단면적이 서로 다른 콘택홀을 형성하는 것과 단면적이 동일한 콘택홀을 형성하는 것은 이 분야의 통상의 지식을 가진 기술자에게는 특별한 기술이 아니므로, 여기서는 그 과정에 대해서는 설명하지 않는다.
상기의 과정에서 포토 레지스터(photo resistor)를 도포하고, 포토 레지스터에 매스크(Mask)에 형성된 일정한 패턴(pattern)을 반영한 후, 포토 레지스터를 베이킹(baking)하고, 에칭(etching)하는 공정은 공통으로 사용될 것이다.
이하에서는 도 2에 도시된 본 발명에 따른 반도체 장치를 제조하는 과정에 대하여 설명한다.
도 3은 도 2에 도시된 반도체 장치의 제조 과정을 나타낸다.
도 3(a)는 2개의 웨이퍼에 대하여 물리적 접합이 진행된 결과를 나타낸다.
도 3(b)는 제1웨이퍼의 기판으로부터 제1전도영역까지 형성된 제1버팅 콘택홀을 나타낸다.
도 3(c)는 제1전도영역으로부터 제2전도영역까지 형성된 제2버팅 콘택홀을 나타낸다.
도 3(a)를 참조하면, 2개의 웨이퍼(210, 220)가 물리적으로 접합된 경우 2개의 웨이퍼(210, 220)의 표면에 형성된 산화막(oxide)이 서로 접합되므로, 산화막 접합(oxide to oxide bonding)이라고 하며, 이들 2개의 웨이퍼(210, 220)에 구현된 소자들 사이는 전기적으로 절연되어 있다.
도 3(b)를 참조하면, 제1버팅 콘택홀(E)은 제1웨이퍼(210)의 기판으로부터 제1전도영역(A, C)으로 형성된다. 이 과정에서는 상술한 바와 같이, 제1버팅 콘택홀(E)로 정의된 매스크를 이용하여 포토 레지스터 공정 및 에칭 공정을 통해 제1버팅 콘택홀(E)을 생성한다.
일반적으로 반도체 소자들이 구현되는 웨이퍼의 기판(substrate)의 두께는 상당하지만, 제1버팅 콘택홀(E)을 생성하기에 앞서, 제1웨이퍼(210)의 기판의 하부를 연마(grinding)하여 기판의 두께를 제2웨이퍼(220)의 기판(Si)에 비해 얇게 만든다. 도 2를 참조하면, 하부의 제2웨이퍼(220)의 기판의 두께가 상부의 제1웨이퍼(210)의 기판의 두께에 비해 두껍다는 것을 알 수 있다. 제1버팅 콘택홀(E)이 에칭 작업에 의해 형성되므로, 에칭되는 기판의 두께가 얇을 수록 에칭 시간이 감소하게 될 것이다.
제1웨이퍼(210)의 기판의 두께를 조절하는 시기는 조절이 가능한데, 도 3(a)에 도시된 물리적 접합 단계 이전에 실행한 후 물리적 접합 단계를 연이어 수행하도록 할 수도 있고, 물리적 접합 단계 후 도 3(b)에 도시된 단계를 수행하기 이전에 실행하는 것도 가능하다.
도 3(c)를 참조하면, 제2버팅 콘택홀(F)은 제1전도영역(A, C)으로부터 제2전도영역(B, D)까지 형성된다. 이 과정에서도, 제2버팅 콘택홀(F)로 정의된 매스크를 이용하여 포토 레지스터 공정 및 에칭 공정을 통해 제2버팅 콘택홀(F)을 생성한다. 도 3(c)에 도시된 바와 같이 2개의 버팅 콘택홀(E, F)의 단면적이 서로 다르게 할 경우, 제1버팅 콘택홀(E)과 제2버팅 콘택홀(F)의 구별이 용이하다는 장점이 있다.
상기와 같은 2 단계의 공정을 거쳐서 2개의 버팅 콘택홀(E, F)을 순차적으로 생성하는 방식을 사용할 수도 있으나, 2개의 버팅 콘택홀(E, F)의 단면적을 다르게 할 필요가 없는 경우에는, 1회의 에칭 공정으로 2개의 버팅 콘택홀(E, F)을 포함하는 하나의 버팅 콘택홀을 생성하는 방식도 실현 가능하다. 이 경우, 한 번의 공정으로 버팅 콘택홀을 생성할 수 있으므로, 공정이 간단하고 공정 시간을 감소시킬 수 있는 장점이 있다.
본 발명에서는 버팅 콘택홀을 사용하는 이외에 TSV(Throuth Silicon Via) 방식을 이용할 수도 있다. TSV는 실리콘 웨이퍼를 수십 마이크로미터 두께로 얇게 만든 칩에 직접 구멍을 뚫고 동일한 칩은 수직으로 적층해 관통 전극으로 연결하는 기술이다. 이 방식은 쌓아 올린 칩을 와이어로 연결하는 종래의 와이어 본딩 방식에 비해 빠르게 동작하는 것은 물론, 칩의 두께로 줄이고 소비전력도 감소시킬 수 있는 장점이 있다.
본 발명의 경우 어느 것을 사용하더라도 발명의 효과를 얻을 수 있다.
이상에서는 본 발명에 대한 기술사상을 첨부 도면과 함께 서술하였지만 이는 본 발명의 바람직한 실시 예를 예시적으로 설명한 것이지 본 발명을 한정하는 것은 아니다. 또한 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 이라면 누구나 본 발명의 기술적 사상의 범주를 이탈하지 않는 범위 내에서 다양한 변형 및 모방 가능함은 명백한 사실이다.
110, 210: 제1웨이퍼 120, 220: 제2웨이퍼

Claims (10)

  1. 일련의 공정이 완료된 제1웨이퍼 및 제2웨이퍼를 버팅 콘택 방식을 이용하여 상기 제1웨이퍼 및 상기 제2웨이퍼를 전기적으로 연결하는 웨이퍼 간의 전기적 연결방법에 있어서,
    절연막 접합 방식으로 상기 제1웨이퍼와 상기 제2웨이퍼를 물리적으로 접합하는 물리적 접합단계; 및
    상기 제1웨이퍼의 제1전도영역과 이에 대응되는 상기 제2웨이퍼의 제2전도영역의 전기적 연결은TSV(Through Silcon Via) 또는 버팅 콘택(butting contact)을 이용한 메탈 접합(metal to metal bonding) 방식으로 연결하는 전기적 접합단계;를 포함하되,
    상기 전기적 접합단계는,
    상기 제1웨이퍼의 기판하부 및 상기 제1전도영역을 관통하여 상기 제2전도영역에 이르는 버팅 콘택홀을 형성하는 버팅 콘택홀 형성단계;
    상기 버팅 콘택홀의 영역 중 상기 제1전도영역 및 상기 제1전도영역과 상기 제2전도영역 사이의 영역에만 전도물질을 충진하는 전도물질 충진단계; 및
    상기 버팅 콘택홀의 영역 중 전도물질이 충진되지 않은 나머지 영역에는 절연물질을 충진하는 절연물질 충진단계;를 더 포함하는 것을 특징으로 하는 웨이퍼 간의 전기적 연결방법.
  2. 삭제
  3. 제1항에 있어서, 상기 버팅 콘택홀 형성단계는,
    상기 제1웨이퍼의 기판하부를 관통하여 상기 제1전도영역에 이르는 홀을 형성하는 제1버팅 콘택홀 형성단계; 및
    상기 제1전도영역을 관통하여 상기 제2전도영역에 이르는 홀을 형성하는 제2버팅 콘택홀 형성단계;를 포함하는 것을 특징으로 하는 웨이퍼 간의 전기적 연결방법.
  4. 제3항에 있어서,
    상기 절연물질 충진단계는 상기 제1버팅 콘택홀에 절연물질을 충진하고,
    상기 전도물질 충진단계는 상기 제2버팅 콘택홀에 전도물질을 충진하는 것을 특징으로 하는 웨이퍼 간의 전기적 연결방법.
  5. 제4항에 있어서,
    상기 제1버팅 콘택홀의 단면적은 상기 제2버팅 콘택홀의 단면적에 비해 넓은 것을 특징으로 하는 웨이퍼 간의 전기적 연결방법.
  6. 제1항에 있어서,
    상기 제1웨이퍼의 기판의 하부를 연마하여 기판 하부의 일정 두께를 제거하는 기판하부 제거단계를 더 포함하는 것을 특징으로 하는 웨이퍼 간의 전기적 연결방법.
  7. 제6항에 있어서, 상기 기판하부 제거단계는,
    상기 물리적 접합단계 이전에 수행하거나,
    상기 물리적 접합단계를 완료한 이후 상기 전기적 접합단계 이전에 수행하는 것을 특징으로 하는 웨이퍼 간의 전기적 연결방법.
  8. 제1항에 있어서, 상기 물리적 접합단계는,
    산화막 접합(oxide to oxide bonding) 방식으로 상기 제1웨이퍼와 상기 제2웨이퍼를 물리적으로 접합하는 단계인 것을 특징으로 하는 웨이퍼 간의 전기적 연결방법.
  9. 제1항의 방법을 이용하여 전기적으로 연결한 제1웨이퍼 및 제2웨이퍼를 이용하여 구현한 반도체 장치에 있어서,
    상기 제1웨이퍼에는 CMOS 이미지 센서를 구성하는 복수 개의 구성요소 중 적어도 하나가 구현되며,
    상기 제2웨이퍼에는 상기 CMOS 이미지 센서를 구성하는 복수 개의 구성요소 중 상기 제1웨이퍼에 구현된 요소를 제외한 나머지 요소 및 픽셀 구동회로가 구현된 것을 특징으로 하는 반도체 장치.
  10. 제9항에 있어서,
    상기 제1웨이퍼에는 상기 CMOS 이미지 센서를 구성하는 복수 개의 구성요소 중 입사되는 빛에 대응하는 전하를 생성하는 포토다이오드가 형성된 것을 특징으로 하는 반도체 장치.
KR1020120129899A 2012-11-16 2012-11-16 버팅 콘택 방식을 이용한 웨이퍼 간의 전기적 연결방법 및 이를 이용하여 구현한 반도체 장치 KR101334220B1 (ko)

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US14/079,075 US8906781B2 (en) 2012-11-16 2013-11-13 Method for electrically connecting wafers using butting contact structure and semiconductor device fabricated through the same
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