CN102341907A - 使用先介电键合后通孔形成的三维集成电路的集成 - Google Patents

使用先介电键合后通孔形成的三维集成电路的集成 Download PDF

Info

Publication number
CN102341907A
CN102341907A CN2010800103402A CN201080010340A CN102341907A CN 102341907 A CN102341907 A CN 102341907A CN 2010800103402 A CN2010800103402 A CN 2010800103402A CN 201080010340 A CN201080010340 A CN 201080010340A CN 102341907 A CN102341907 A CN 102341907A
Authority
CN
China
Prior art keywords
hole
group
bonding
insulating barrier
bonded interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2010800103402A
Other languages
English (en)
Inventor
M·G·法鲁
R·汉侬
S·S·伊耶
E·R·金瑟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN102341907A publication Critical patent/CN102341907A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/08146—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bonding area connecting to a via connection in the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9202—Forming additional connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种实现多个集成电路(IC)器件的三维(3D)集成的方法，包括在第一IC器件之上形成第一绝缘层(120)；在第二IC器件之上形成第二绝缘层(220)；通过使第一绝缘层与第二绝缘层对准并键合以便将第一键合界面(302)界定于它们之间来形成3D键合的IC器件，将第一组通孔(306)界定于该3D键合的IC器件之内，第一组通孔着落在位于第一IC器件之内的导电焊盘(110)之上，以及将第二组通孔(306)界定于该3D键合的IC器件之内，第二组通孔着落在位于第二器件之内的导电焊盘(210)之上，使得第二组通孔穿过键合界面(302)；以及以导电材料(310)填充第一和第二组通孔。

Description

使用先介电键合后通孔形成的三维集成电路的集成
技术领域
本发明一般地涉及半导体器件制造技术，并且更特别地，涉及实现多个集成电路(IC)器件的三维集成。
背景技术
在电子工业中的封装密度持续增加以便将更多的电子器件容纳于封装之内。在这点上，三维(3D)晶片-晶片堆叠技术显著有助于器件集成工艺。典型地，半导体晶片包括被构建于硅衬底之上的若干层的集成电路(例如，处理器，可编程器件、存储器器件等)。晶片的顶层可以通过硅互连或通孔与晶片的底层连接。为了形成3D晶片叠层，两个或更多的晶片一个叠一个地布置并被键合。
3D晶片堆叠技术提供了许多潜在的优点，包括，例如，改进的形状因子、更低的成本、增强的性能以及通过片上系统(SOC)解决方案的更大的集成度。另外，3D晶片堆叠技术可以给芯片提供其他的功能。例如，在形成之后，3D晶片叠层可以被切割成堆叠的管芯或芯片，其中每个堆叠的芯片具有集成电路的多个层(即，分层)。由3D晶片堆叠所形成的SOC架构能够使产品(例如，逻辑电路和动态随机存取存储器(DRAM))的高带宽连通性成为可能，除非所述产品具有不兼容的工艺流程。目前，3D晶片堆叠技术有许多应用，包括高性能的处理器器件、视频和图形处理器、高密度和高带宽的存储芯片，以及其他SOC解决方案。
发明内容
在一种示例性的实施例中，一种实现多个集成电路(IC)器件的三维(3D)集成的方法包括：在第一IC器件之上形成第一绝缘层；在第二IC器件之上形成第二绝缘层；通过使第一IC器件的第一绝缘层与第二IC器件的第二绝缘层对准并键合以便将键合界面界定于它们之间来形成3D键合的IC器件，其中键合界面不含导电材料；在键合之后，将第一组通孔界定于3D键合的IC器件之内，第一组通孔着落(land)在位于第一IC器件之内的导电焊盘之上，以及将第二组通孔界定于3D键合的IC器件之内，第二组通孔着落在位于第二器件之内的导电焊盘之上，使得第二组通孔穿过键合界面；以及以导电材料填充第一和第二组通孔，以及将第一组通孔中的至少一个通孔电连接至第二组通孔中的至少一个通孔，由此建立在3D键合的IC器件的第一和第二IC之间的电通信。
在另一种实施例中，一种实现多个集成电路(IC)器件的三维(3D)集成的方法包括：形成具有半导体衬底、前段工艺(FEOL)结构、中段工艺(MOL)结构和后段工艺(BEOL)结构的第一IC器件，在第一IC器件的BEOL结构之上具有第一绝缘层；形成具有半导体衬底、FEOL结构、MOL结构和BEOL结构的第二IC器件，在第二IC器件的BEOL结构之上具有第二绝缘层；通过使第一IC器件的第一绝缘层与第二IC器件的第二绝缘层对准并键合以便将第一键合界面界定于它们之间来形成3D键合的IC器件，其中第一键合界面不含导电材料；在键合之后，将第一组通孔界定于3D键合的IC器件之内，第一组通孔着落在位于第一IC器件之内的导电焊盘之上，以及将第二组通孔界定于3D键合的IC器件之内，第二组通孔着落在位于第二器件之内的导电焊盘之上，使得第二组通孔穿过第一键合界面；以及以导电材料填充第一和第二组通孔，以及将第一组通孔中的至少一个通孔电连接至第二组通孔中的至少一个通孔，由此建立在3D键合的IC器件的第一和第二IC之间的电通信。
在另一种实施例中，三维(3D)集成电路(IC)器件包括第一IC器件，该第一IC器件与第二IC器件键合于它们之间的第一键合界面处，由此界定3D键合的IC器件，第一键合界面界定于第一IC器件的第一绝缘层与第二IC器件的第二绝缘层之间，其中第一键合界面不含导电材料；界定于3D键合的IC器件之内的第一组通孔，第一组通孔着落在位于第一IC器件之内的导电焊盘之上，以及界定于3D键合的IC器件之内的第二组通孔，第二组通孔着落在位于第二器件之内的导电焊盘之上，使得第二组通孔穿过第一键合界面；以及第一和第二组通孔以导电材料来填充，以及将第一组通孔中的至少一个通孔电连接至第二组通孔中的至少一个通孔，由此建立在3D键合的IC器件的第一和第二IC之间的电通信。
附图说明
参考示例性的附图，其中相同的元件在这几个附图中编号相同：
图1到16是示出根据本发明的一种实施例实现多个集成电路(IC)器件的三维集成的方法的一系列截面图。
与当前的3D晶片堆叠技术相关的一个缺点涉及键合晶片的粘合剂的使用。此类粘合剂由于所不希望的固有的聚合物粘合剂的性质(例如热稳定性)限制了实际的、工厂内(in-fab)加工的数量以及可靠性提高的问题。另外，实现在一对晶片的整个直径之上的预先存在的硅穿孔(TSV)的可接受的对准同样是困难的，这还造成了可靠性的问题。
因此，在此公开了一种用于3D晶片集成键合的方法以及所产生的结构，在该方法中TSV在键合之后形成。以这种方式，实际键合仅涉及晶片的氧化物-氧化物键合(或者更一般地涉及绝缘体-绝缘体键合)，因为TSV没有在键合之前形成于个体晶片之上，所以在它们之间不存在关于通孔的对准问题。
应当意识到，虽然在此描述了具体的晶片衬底键合的工艺流程，但是此类描述只是示例性的，并且在此所公开的原理同样适用于各种类型的TSV导电材料、电介质和粘合剂界面材料，以及多种类型的半导体晶片和衬底。
具体实施方式
首先参考图1(a)，图中示出了将要与一个或更多个另外的晶片集成并键合的第一晶片100的截面图。在所示出的示例性实施例中，晶片100表示本技术领域所已知的具有形成于其上的前段工艺(FEOL)、中段工艺(MOL)和后段工艺(BEOL)结构的存储器晶片。另外，示例性的存储器晶片100被示出具有厚的牺牲基层102(例如，重掺杂的P+层)，以及形成于牺牲基层之上的轻掺杂的外延层104。牺牲基层102可以具有例如为外延层104的掺杂浓度的1000倍的掺杂质浓度。FEOL结构形成于外延层104之内，该FEOL结构用作存储器层的衬底。如以上所指出的，该外延层104能够由半导电材料的块体衬底或绝缘体上半导体(SOI)衬底来实现。
应当意识到，在晶片的MOL和BEOL区中示出的布线层(例如，106和108)只是示例性的。在实际的器件中，可以有若干绝缘体材料层关于以及形成于其中的相关布线。同样如图1(a)所示，在布线层中形成了一个或更多个条带/着落焊盘110。为了例示起见，在M1(第一)布线层中示出了焊盘，尽管此类焊盘能够形成于器件之内的各个层中。
现在参考图1(b)，图中示出了将要与图1(a)所示的第一晶片100集成并键合的第二晶片200的截面图。在所示出的示例性实施例中，晶片200表示本技术领域所已知的具有形成于其上的FEOL、MOL和BEOL结构的处理器晶片。另外，示例性的存储器晶片200被示出具有衬底基层202(例如，P型层)，该衬底基层202可以由半导电材料(例如，硅)块体衬底或SOI衬底来实现。再者，在晶片200的MOL和BEOL区中所示出的布线层(例如，206和208)只是示例性的。与存储器晶片100的情形一样，处理器晶片200同样包括形成于一个或更多个布线层内的金属条带/着落焊盘210。
图2(a)和2(b)分别示出了在准备晶片键合时晶片100、200以氧化物层120、220或者其他适合类型的绝缘体材料(包括任意粘合剂材料)进行的钝化。钝化的晶片100、200两者然后共同示出于图3中，特别地，在图3中存储器晶片100被翻转并与处理器晶片200对准。该对准可以通过任何已知的技术(例如，红外(IR)对准)或其他适合的方法来实现。应当指出，由于至此还没有TSV形成于晶片100、200中的任一晶片之内，因而没有必要使晶片之间的任意导体材料对准。
如图4所示，晶片100、200被键合到一起以形成集成晶片，现在总体上图示于300。在将氧化物用作个体晶片的钝化材料的情况下，键合可以是，例如，氧化物-氧化物键合(例如，通过退火)、氧化物/粘合剂键合，或者本技术领域所已知的引起电绝缘层之间的强键合的任意其他适合的技术。因而键合的集成晶片300在层120和220之间具有键合界面302，其中该界面完全由绝缘体材料组成，而没有导电材料(例如，通孔)。
应当意识到，在这点上，被键合形成集成晶片300的示例性的晶片100、200不需要是以上实例所给出的具体类型的晶片。例如，处理器晶片同样可以被“翻转”并与存储器晶片键合。另外，一种存储器晶片能够被翻转并且按照以上所描述的方式与另一个存储器晶片键合。甚至更一般地，晶片100、200可以表示形成于衬底上的任意类型的集成电路器件，在该衬底上希望以3D的方式来集成相同或其他类型的集成电路器件。
在任何情况下，图5示出了在形成晶片300的存储器部分时所使用的厚的牺牲基层的去除。该去除可以通过半导体领域中任意适合的方法来实现，包括，例如，诸如磨削、化学机械抛光(CMP)、蚀刻等技术，以及这些技术的结合。通过高浓度掺杂牺牲基层(相对于外延层104)，在这两个层之间产生了强蚀刻选择性。因而，蚀刻变成一种适用于去除牺牲基层的技术。一旦去除牺牲基层，集成晶片300的存储器部分的外延层104就露出用于进一步处理。
现在参考图6，开始进行用于“后通孔”TSV形成的处理步骤。这可以包括，例如，在外延层104上形成钝化层304(例如，氧化物)。然后，第一和第二组TSV通过通孔的图形化和蚀刻来界定。更具体而言，“浅的”那组TSV 306被形成穿过钝化层304、外延层104以及布线层106、108中对应于晶片300的存储器部分的着落焊盘110的特定位置的一个或更多个。另外，“深的”那组TSV 308被形成穿过晶片300的整个存储器部分，以及钝化层120和220，一直到在晶片300的处理器部分中的着落焊盘210。与存储器部分中的着落焊盘110的情形一样，在处理器部分中的着落焊盘210同样可以位于各个布线层内，并且因而在着落焊盘210存在于这些层中的情况下，则深的TSV的蚀刻可以继续进行穿过布线层206、208中的一个或更多个。
在一种示例性的实施例中，浅的TSV 306可以具有大约2-3微米(μm)的直径，大约8-15μm的总深度，以及大约10μm或更大的间距(间隔)。深的TSV 308可以具有大约5-10μm的直径，大约25-40μm的总深度，以及大约10μm或更大的间距。在两组TSV的初始蚀刻之后，氧化物内衬被形成于TSV的侧壁之上以便防止导电性的通孔填充材料后来的扩散。在薄的氧化物内衬的沉积之后紧接着是各向异性的蚀刻以从水平表面(例如，金属着落焊盘110、210)上去除内衬。然后，可以执行标准的处理以形成通孔内衬层(例如，钽、氮化钽等)、金属籽晶层和金属填充物310(例如，铜)，其后使过量的材料平坦化，例如通过CMP，如图7所示。
在工艺中的这点上，可以形成在浅的和深的TSV之间所需要的任何连接条带(由此界定在集成晶片300的处理器和储存器部分之间的电通信)，如图8所示。如图所示，在图形化蚀刻、内衬层、籽晶层、金属电镀和CMP以形成浅/深TSV对之间的连接条带314之后，形成另一钝化(例如，氧化物)层312。虽然所示出的实施例是单镶嵌处理的实例，但是应当理解，同样能够使用双镶嵌处理来同时界定和填充通孔和条带结构。
在所形成的3D集成结构在这点基本上完成了的情况下，那么然后将实施最后的处理步骤，例如形成顶钝化层(没有示出)，图形化钝化层以及形成导电捕获焊盘(capture pad)(没有示出)或者用于外部连接的其他冶金物(例如，C4焊料球)。但是，为了例示起见，应当假定，进一步的3D晶片集成是所希望的，诸如(例如)增添更多的存储器芯片。因此，如图9所示，另一个钝化层320被形成于晶片之上。例如，层320可以是氧化物层，例如层120、220所使用的，或者在准备晶片键合时包括任何粘合剂材料的其他适合类型的绝缘体材料。
图10示出第二存储器晶片400与集成晶片300的对准。第二存储器晶片400在构造上与图3所示的第一存储器晶片100相似，因为晶片400包括厚的牺牲基层402(例如，重掺杂的P+层)，形成于牺牲基层402上的轻微掺杂的外延层404，在MOL和BEOL区之内的一个或更多个布线层406、408，以及形成于布线层内的一个或更多个条带/着落焊盘410。然后如图11所示，晶片300和400被键合到一起以形成单一集成晶片，现在总体上图示于500。同样，在将氧化物用作个体晶片的钝化材料的情况下，键合可以是，例如，氧化物-氧化物键合(例如，通过退火)、氧化物/粘合剂键合，或者本技术领域所已知的引起电绝缘层之间的强键合的任意其他适合的技术。因而键合的集成晶片500在层320和520之间具有键合界面502，其中(与第一键合界面302类似)第二键合界面502完全由绝缘体材料组成，而没有导电材料(例如，通孔)。
在处理序列中的后续步骤与图5-8所示的步骤相似。例如，在图12中，用来形成第二存储器晶片400的厚的牺牲基层402通过半导体领域中的任意适合的方法(例如磨削、CMP、蚀刻等)来去除。一旦去除了牺牲基层，集成晶片500的第二存储器部分的外延404就露出用于进一步处理。图13然后示出了另一组TSV的形成，包括在外延层404上形成钝化层504(例如，氧化物)。同样，浅的那组TSV 506被形成穿过钝化层504、外延层404，以及布线层406、408中对应于晶片500的第二存储器部分的着落焊盘410的特定位置的一个或更多个。另外，深的那组TSV 508被形成穿过晶片500的整个第二存储器部分，以及钝化层420和320。在所示出的示例性实施例中，深的TSV 508之一着落于条带314之上，该条带314连接在晶片500的处理器和第一存储器部分之间的电路。深的TSV 508中的另一个被示出以连接至早先形成的TSV，由此使TSV 508的总深度从器件的顶部向下延伸至处理器部分中的着落条带210。
在这两组TSV 506、508的蚀刻之后，氧化物内衬被形成于其侧壁之上以便防止导电性的通孔填充材料后来的扩散。在薄的氧化物内衬的沉积之后紧接着是各向异性的蚀刻以从水平表面上去除内衬。然后，可以执行标准的处理以形成通孔内衬层(例如，钽、氮化钽等)、金属籽晶层和金属填充物510(例如，铜)，其后使过量的材料平坦化，例如通过CMP，如图14所示。在图15中形成了在浅的和深的TSV之间的连接条带。特别地，在图形化蚀刻、内衬层、籽晶层、金属电镀和CMP以形成浅/深TSV对之间的连接条带514之后，形成另一钝化(例如，氧化物)层512。同样，虽然所示出的实施例是单镶嵌处理的实例，但是应当理解，同样能够使用双镶嵌处理来同时界定和填充通孔和条带结构。
最后，图16示出了形成于晶片500之上用于提供3D集成的晶片500的外部电接触的捕获焊盘516(例如，C4)。可以形成捕获焊盘516使之具有或不具有另一钝化层(没有示出)。再者，在形成任何外部的捕获焊盘之前，在使键合晶片电互连的“后通孔”的界定之前，还可以按照以上所描述的方式来堆叠并键合另外的晶片层。这样做时，所有键合工艺在本质上都是绝缘体-绝缘体的键合工艺，因为该集成不需要进行导电性结构的对准/键合。应当指出，虽然深的TSV最终穿过了晶片键合界面，但是通孔本身并不包括该界面的一部分，因为金属填充在键合之后进行。
应当理解，在此所描述的示例性的工艺流程可以具有许多变化，包括，但不限于，使用关于直的、“只有通孔”的晶片，仅具有布线再分布和晶片连接TSV的晶片，以及具有诸如电容器、电压调节模块(VRM)等的具体特征的晶片。另外，各种晶片(例如，处理器，晶片)在其内还可以包括埋置氧化物(BOX)层，以用于SOI应用。
虽然本发明已经参考一种或更多种优选的实施例进行了描述，但是本领域技术人员应当理解，在不脱离本发明的范围的情况下可以进行各种改变以及元件可以用其等价物来替代。另外，在不脱离本发明的本质范围的情况下，还可以进行许多修改以使特定的情况或材料适合于本发明的教导。因此，希望本发明不受限于作为为实施本发明而构想出的最好的模式来公开的具体实施例，而是本发明将包括属于所附权利要求的范围之内的所有实施例。

Claims (20)

1.一种实现多个集成电路(IC)器件的三维(3D)集成的方法，所述方法包括：
在第一IC器件之上形成第一绝缘层(120)；
在第二IC器件之上形成第二绝缘层(220)；
通过使所述第一IC器件的所述第一绝缘层(120)与所述第二IC器件的所述第二绝缘层(220)对准并键合以便将第一键合界面(302)界定于它们之间来形成3D键合的IC器件，其中所述第一键合界面不含导电材料；
在所述键合之后，将第一组通孔(306)界定于所述3D键合的IC器件之内，所述第一组通孔着落在位于所述第一IC器件之内的导电焊盘(110)之上，以及将第二组通孔(308)界定于所述3D键合的IC器件之内，所述第二组通孔着落在位于所述第二IC器件之内的导电焊盘(210)之上，使得所述第二组通孔穿过所述第一键合界面(302)；以及
以导电材料(310)填充所述第一和第二组通孔，并将所述第一组通孔中的至少一个通孔电连接(314)至所述第二组通孔中的至少一个通孔，由此建立在所述3D键合的IC器件的所述第一和第二IC之间的电通信。
2.根据权利要求1所述的方法，还包括：
在所述3D键合的IC器件之上形成第三绝缘层(320)；
在第三IC器件之上形成第四绝缘层(420)；
通过使所述第三IC器件的所述第四绝缘层(420)与所述3D键合的IC器件的所述第三绝缘层(320)对准并键合以便将第二键合界面(502)界定于它们之间来将所述第三IC器件附接于所述3D键合的IC器件，其中所述第二键合界面(502)不含导电材料；
将第三组通孔(506)界定于所述3D键合的IC器件之内，所述第三组通孔着落在位于所述第三IC器件之内的导电焊盘(410)之上，以及将第四组通孔(508)界定于所述3D键合的IC器件之内，所述第四组通孔着落在所述3D键合的IC器件之内的所述第二组通孔(308)中的一个或更多个通孔以及在所述3D键合的IC器件之内的所述第一和第二组通孔之间的电连接(314)之上，使得所述第四组通孔穿过所述第二键合界面(502)；以及
以导电材料(510)填充所述第三和第四组通孔，并将所述第三组通孔中的至少一个通孔电连接(514)至所述第四组通孔中的至少一个通孔，由此建立在所述3D键合的IC器件的所述第一、第二和第三IC之间的电通信。
3.根据权利要求1所述的方法，其中所述第一IC器件包括形成于牺牲基层(102)之上的外延生长的半导体层(104)，以及其中所述牺牲基层在使所述第一和第二IC器件键合之后且在所述第一和第二组通孔的形成之前被去除。
4.根据权利要求2所述的方法，其中所述第一IC器件的所述牺牲基层(102)相对于所述外延生长的半导体层(104)具有实质上更高的掺杂浓度以便在它们之间产生蚀刻选择性。
5.根据权利要求1所述的方法，其中所述第一绝缘层(120)和第二绝缘层(220)包括氧化物层，以及所述键合包括氧化物-氧化物键合和氧化物/粘合剂键合中的一种或更多种。
6.根据权利要求1所述的方法，其中所述第一IC器件包括存储器器件，并且所述第二IC器件包括处理器器件。
7.根据权利要求2所述的方法，其中所述第一IC器件包括存储器器件，所述第二IC器件包括处理器器件，并且所述第三IC器件包括另一存储器器件。
8.一种实现多个集成电路(IC)器件的三维(3D)集成的方法，所述方法包括：
形成具有半导体衬底、前段工艺(FEOL)结构、中段工艺(MOL)结构和后段工艺(BEOL)结构的第一IC器件(100)，在所述第一IC器件的所述BEOL结构之上具有第一绝缘层(120)；
形成具有半导体衬底、FEOL结构、MOL结构和BEOL结构的第二IC器件(200)，在所述第二IC器件的所述BEOL结构之上具有第二绝缘层(220)；
通过使所述第一IC器件的所述第一绝缘层(120)与所述第二IC器件的所述第二绝缘层(220)对准并键合以便将第一键合界面(302)界定于它们之间来形成3D键合的IC器件(300)，其中所述第一键合界面不含导电材料；
在所述键合之后，将第一组通孔(306)界定于所述3D键合的IC器件之内，所述第一组通孔着落在位于所述第一IC器件之内的导电焊盘(110)之上，以及将第二组通孔(308)界定于所述3D键合的IC器件之内，所述第二组通孔着落在位于所述第二器件之内的导电焊盘(210)之上，使得所述第二组通孔穿过所述第一键合界面(302)；以及
以导电材料(310)填充所述第一和第二组通孔，并将所述第一组通孔中的至少一个通孔电连接(314)至所述第二组通孔中的至少一个通孔，由此建立在所述3D键合的IC器件的所述第一和第二IC之间的电通信。
9.根据权利要求8所述的方法，还包括：
在所述3D键合的IC器件之上形成第三绝缘层(320)；
形成具有半导体衬底、FEOL结构、MOL结构和BEOL结构的第三IC器件(400)，在所述第三IC器件的所述BEOL结构之上具有第四绝缘层(420)；
通过使所述第三IC器件的所述第四绝缘层(420)与所述3D键合的IC器件的所述第三绝缘层(320)对准并键合以便将第二键合界面(502)界定于它们之间来将所述第三IC器件(400)附接于所述3D键合的IC器件(300)，其中所述第二键合界面(502)不含导电材料；
将第三组通孔(506)界定于所述3D键合的IC器件之内，所述第三组通孔着落在位于所述第三IC器件之内的导电焊盘(410)之上，以及将第四组通孔(508)界定于所述3D键合的IC器件之内，所述第四组通孔着落在所述3D键合的IC器件之内的所述第二组通孔(308)中的一个或更多个通孔以及在所述3D键合的IC器件之内的所述第一和第二组通孔之间的电连接(314)之上，使得所述第四组通孔穿过所述第二键合界面；以及
以导电材料(510)填充所述第三和第四组通孔，并将所述第三组通孔中的至少一个通孔电连接(514)至所述第四组通孔中的至少一个通孔，由此建立在所述3D键合的IC器件的所述第一、第二和第三IC之间的电通信。
10.根据权利要求8所述的方法，其中形成所述第一IC器件包括：使其所述半导体层(104)外延生长于牺牲基层(102)之上，以及其中在使所述第一和第二IC器件键合之后且在所述第一和第二组通孔的形成之前去除所述牺牲基层。
11.根据权利要求9所述的方法，其中所述第一IC器件的所述牺牲基层(102)相对于所述外延生长的半导体层(104)具有实质上更高的掺杂浓度以便在它们之间产生蚀刻选择性。
12.根据权利要求8所述的方法，其中所述第一(120)和第二(220)绝缘层包括氧化物层，并且所述键合包括氧化物-氧化物键合和氧化物/粘合剂键合中的一种或更多种。
13.根据权利要求8所述的方法，其中所述第一IC器件包括存储器器件，并且所述第二IC器件包括处理器器件。
14.根据权利要求9所述的方法，其中所述第一IC器件包括存储器器件，所述第二IC器件包括处理器器件，并且所述第三IC器件包括另一存储器器件。
15.一种三维(3D)集成电路(IC)器件，包括：
第一IC器件(100)，与第二IC器件(200)键合于它们之间的第一键合界面(302)处，由此界定3D键合的IC器件，所述第一键合界面(302)界定于所述第一IC器件的第一绝缘层(120)与所述第二IC器件的第二绝缘层(220)之间，其中所述第一键合界面不含导电材料；
界定于所述3D键合的IC器件之内的第一组通孔(306)，所述第一组通孔着落在位于所述第一IC器件之内的导电焊盘(110)之上，以及界定于所述3D键合的IC器件之内的第二组通孔(308)，所述第二组通孔着落在位于所述第二器件之内的导电焊盘(210)之上，使得所述第二组通孔穿过所述第一键合界面(302)；以及
所述第一和第二组通孔填充有导电材料(310)，并且所述第一组通孔中的至少一个通孔电连接(314)至所述第二组通孔中的至少一个通孔，由此建立在所述3D键合的IC器件的所述第一和第二IC之间的电通信。
16.根据权利要求15所述的器件，还包括：
第三IC器件(400)，与所述3D键合的IC器件(300)附接于它们之间的第二键合界面(502)，所述第二键合界面界定于形成于所述3D键合的IC器件之上的第三绝缘层(320)与由所述第三IC器件形成的第四绝缘层(420)之间；
界定于所述3D键合的IC器件之内的第三组通孔(506)，所述第三组通孔着落在位于所述第三IC器件之内的导电焊盘(410)之上，以及界定于所述3D键合的IC器件之内的第四组通孔(508)，所述第四组通孔着落在所述3D键合的IC器件之内的所述第二组通孔(308)中的一个或更多个通孔以及在所述3D键合的IC器件之内的所述第一和第二组通孔之间的电连接(314)之上，使得所述第四组通孔穿过所述第二键合界面(502)；以及
所述第三和第四组通孔填充有导电材料(510)，并且所述第三组通孔中的至少一个通孔电连接(514)至所述第四组通孔中的至少一个通孔，由此建立在所述3D键合的IC器件的所述第一、第二和第三IC之间的电通信。
17.根据权利要求15所述的器件，其中所述第一绝缘层(120)和第二绝缘层(220)包括氧化物层。
18.根据权利要求15所述的器件，其中所述第二组通孔(308)中的通孔比所述第一组通孔(306)中的通孔深。
19.根据权利要求18所述的器件，其中所述第二组通孔(308)中的通孔与所述第一组通孔(306)中的通孔相比具有更大的直径。
20.根据权利要求15所述的方法，其中所述第一IC器件包括存储器器件，并且所述第二IC器件包括处理器器件。
CN2010800103402A 2009-04-20 2010-04-08 使用先介电键合后通孔形成的三维集成电路的集成 Pending CN102341907A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/426,466 US9406561B2 (en) 2009-04-20 2009-04-20 Three dimensional integrated circuit integration using dielectric bonding first and through via formation last
US12/426,466 2009-04-20
PCT/US2010/030357 WO2010123691A1 (en) 2009-04-20 2010-04-08 Three dimensional integrated circuit integration using dielectric bonding first and through via formation last

Publications (1)

Publication Number Publication Date
CN102341907A true CN102341907A (zh) 2012-02-01

Family

ID=42980379

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2010800103402A Pending CN102341907A (zh) 2009-04-20 2010-04-08 使用先介电键合后通孔形成的三维集成电路的集成

Country Status (4)

Country Link
US (1) US9406561B2 (zh)
EP (1) EP2422366A4 (zh)
CN (1) CN102341907A (zh)
WO (1) WO2010123691A1 (zh)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103066093A (zh) * 2013-01-14 2013-04-24 陆伟 一种用深槽隔离制造影像传感器的方法及影像传感器结构
CN103972151A (zh) * 2013-01-31 2014-08-06 旺宏电子股份有限公司 连接叠层结构的导电层的中间连接件的形成方法
CN104657533A (zh) * 2013-11-18 2015-05-27 台湾积体电路制造股份有限公司 Feol/mol/beol中的不同缩放比率
CN104752366A (zh) * 2013-12-27 2015-07-01 国际商业机器公司 用于制造3d集成方案的结构和方法
TWI501192B (zh) * 2012-07-06 2015-09-21 Nvidia Corp 位於圖形處理單元〈ＧＰＵs〉上之動態隨機存取記憶體〈ＤＲＡＭs〉的替代立體〈３Ｄ〉堆疊架構
CN108766893A (zh) * 2018-05-31 2018-11-06 德淮半导体有限公司 半导体装置及其制造方法
CN109148469A (zh) * 2018-08-01 2019-01-04 长江存储科技有限责任公司 存储器结构及其制造方法
CN109473436A (zh) * 2018-11-15 2019-03-15 长江存储科技有限责任公司 半导体器件及其形成方法
CN109560099A (zh) * 2018-11-29 2019-04-02 德淮半导体有限公司 用于等离子体损伤检测的半导体器件及其检测方法、形成方法
CN111354736A (zh) * 2018-12-22 2020-06-30 艾克瑟尔西斯公司 3d nand高长径比串和沟道
CN112164688A (zh) * 2017-07-21 2021-01-01 联华电子股份有限公司 芯片堆叠结构及管芯堆叠结构的制造方法
CN112164674A (zh) * 2020-09-24 2021-01-01 芯盟科技有限公司 堆叠式高带宽存储器
CN118471932A (zh) * 2024-07-09 2024-08-09 武汉新芯集成电路股份有限公司 半导体器件及其制备方法

Families Citing this family (195)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7727887B2 (en) * 2007-10-30 2010-06-01 International Business Machines Corporation Method for improved power distribution in a three dimensional vertical integrated circuit
US8222097B2 (en) 2008-08-27 2012-07-17 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US7839163B2 (en) * 2009-01-22 2010-11-23 International Business Machines Corporation Programmable through silicon via
US9406561B2 (en) 2009-04-20 2016-08-02 International Business Machines Corporation Three dimensional integrated circuit integration using dielectric bonding first and through via formation last
US11018133B2 (en) 2009-10-12 2021-05-25 Monolithic 3D Inc. 3D integrated circuit
US10366970B2 (en) 2009-10-12 2019-07-30 Monolithic 3D Inc. 3D semiconductor device and structure
US12027518B1 (en) 2009-10-12 2024-07-02 Monolithic 3D Inc. 3D semiconductor devices and structures with metal layers
US11374118B2 (en) 2009-10-12 2022-06-28 Monolithic 3D Inc. Method to form a 3D integrated circuit
US11984445B2 (en) 2009-10-12 2024-05-14 Monolithic 3D Inc. 3D semiconductor devices and structures with metal layers
US10388863B2 (en) 2009-10-12 2019-08-20 Monolithic 3D Inc. 3D memory device and structure
US10910364B2 (en) 2009-10-12 2021-02-02 Monolitaic 3D Inc. 3D semiconductor device
US8012802B2 (en) * 2010-02-04 2011-09-06 Headway Technologies, Inc. Method of manufacturing layered chip package
US8304863B2 (en) * 2010-02-09 2012-11-06 International Business Machines Corporation Electromigration immune through-substrate vias
US9293366B2 (en) 2010-04-28 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate vias with improved connections
KR101124568B1 (ko) 2010-05-31 2012-03-16 주식회사 하이닉스반도체 반도체 칩, 이를 포함하는 적층 칩 구조의 반도체 패키지
US11482440B2 (en) 2010-12-16 2022-10-25 Monolithic 3D Inc. 3D semiconductor device and structure with a built-in test circuit for repairing faulty circuits
US10497713B2 (en) 2010-11-18 2019-12-03 Monolithic 3D Inc. 3D semiconductor memory device and structure
US10896931B1 (en) 2010-10-11 2021-01-19 Monolithic 3D Inc. 3D semiconductor device and structure
US11227897B2 (en) 2010-10-11 2022-01-18 Monolithic 3D Inc. Method for producing a 3D semiconductor memory device and structure
US11158674B2 (en) 2010-10-11 2021-10-26 Monolithic 3D Inc. Method to produce a 3D semiconductor device and structure
US11315980B1 (en) 2010-10-11 2022-04-26 Monolithic 3D Inc. 3D semiconductor device and structure with transistors
US11469271B2 (en) 2010-10-11 2022-10-11 Monolithic 3D Inc. Method to produce 3D semiconductor devices and structures with memory
US11018191B1 (en) 2010-10-11 2021-05-25 Monolithic 3D Inc. 3D semiconductor device and structure
US11257867B1 (en) 2010-10-11 2022-02-22 Monolithic 3D Inc. 3D semiconductor device and structure with oxide bonds
US11024673B1 (en) 2010-10-11 2021-06-01 Monolithic 3D Inc. 3D semiconductor device and structure
US11600667B1 (en) 2010-10-11 2023-03-07 Monolithic 3D Inc. Method to produce 3D semiconductor devices and structures with memory
US11163112B2 (en) 2010-10-13 2021-11-02 Monolithic 3D Inc. Multilevel semiconductor device and structure with electromagnetic modulators
US11855100B2 (en) 2010-10-13 2023-12-26 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11929372B2 (en) 2010-10-13 2024-03-12 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US10833108B2 (en) 2010-10-13 2020-11-10 Monolithic 3D Inc. 3D microdisplay device and structure
US10679977B2 (en) 2010-10-13 2020-06-09 Monolithic 3D Inc. 3D microdisplay device and structure
US12094892B2 (en) 2010-10-13 2024-09-17 Monolithic 3D Inc. 3D micro display device and structure
US11063071B1 (en) 2010-10-13 2021-07-13 Monolithic 3D Inc. Multilevel semiconductor device and structure with waveguides
US11327227B2 (en) 2010-10-13 2022-05-10 Monolithic 3D Inc. Multilevel semiconductor device and structure with electromagnetic modulators
US11404466B2 (en) 2010-10-13 2022-08-02 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US11869915B2 (en) 2010-10-13 2024-01-09 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US10943934B2 (en) 2010-10-13 2021-03-09 Monolithic 3D Inc. Multilevel semiconductor device and structure
US12080743B2 (en) 2010-10-13 2024-09-03 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11694922B2 (en) 2010-10-13 2023-07-04 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11605663B2 (en) 2010-10-13 2023-03-14 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11043523B1 (en) 2010-10-13 2021-06-22 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US11133344B2 (en) 2010-10-13 2021-09-28 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US11855114B2 (en) 2010-10-13 2023-12-26 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11437368B2 (en) 2010-10-13 2022-09-06 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US10978501B1 (en) 2010-10-13 2021-04-13 Monolithic 3D Inc. Multilevel semiconductor device and structure with waveguides
US10998374B1 (en) 2010-10-13 2021-05-04 Monolithic 3D Inc. Multilevel semiconductor device and structure
US11984438B2 (en) 2010-10-13 2024-05-14 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11164898B2 (en) 2010-10-13 2021-11-02 Monolithic 3D Inc. Multilevel semiconductor device and structure
US8557677B2 (en) * 2010-11-10 2013-10-15 Institute of Microelectronics, Chinese Academy of Sciences Stack-type semiconductor device and method for manufacturing the same
CN102468284B (zh) * 2010-11-10 2014-04-16 中国科学院微电子研究所 堆叠的半导体器件及其制造方法
US11862503B2 (en) 2010-11-18 2024-01-02 Monolithic 3D Inc. Method for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11615977B2 (en) 2010-11-18 2023-03-28 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11854857B1 (en) 2010-11-18 2023-12-26 Monolithic 3D Inc. Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11355380B2 (en) 2010-11-18 2022-06-07 Monolithic 3D Inc. Methods for producing 3D semiconductor memory device and structure utilizing alignment marks
US11569117B2 (en) 2010-11-18 2023-01-31 Monolithic 3D Inc. 3D semiconductor device and structure with single-crystal layers
US11804396B2 (en) 2010-11-18 2023-10-31 Monolithic 3D Inc. Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11508605B2 (en) 2010-11-18 2022-11-22 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11018042B1 (en) 2010-11-18 2021-05-25 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11610802B2 (en) 2010-11-18 2023-03-21 Monolithic 3D Inc. Method for producing a 3D semiconductor device and structure with single crystal transistors and metal gate electrodes
US12033884B2 (en) 2010-11-18 2024-07-09 Monolithic 3D Inc. Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11923230B1 (en) 2010-11-18 2024-03-05 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11521888B2 (en) 2010-11-18 2022-12-06 Monolithic 3D Inc. 3D semiconductor device and structure with high-k metal gate transistors
US11121021B2 (en) 2010-11-18 2021-09-14 Monolithic 3D Inc. 3D semiconductor device and structure
US11482439B2 (en) 2010-11-18 2022-10-25 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device comprising charge trap junction-less transistors
US11004719B1 (en) 2010-11-18 2021-05-11 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US12068187B2 (en) 2010-11-18 2024-08-20 Monolithic 3D Inc. 3D semiconductor device and structure with bonding and DRAM memory cells
US12100611B2 (en) 2010-11-18 2024-09-24 Monolithic 3D Inc. Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11901210B2 (en) 2010-11-18 2024-02-13 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11211279B2 (en) 2010-11-18 2021-12-28 Monolithic 3D Inc. Method for processing a 3D integrated circuit and structure
US11443971B2 (en) 2010-11-18 2022-09-13 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11094576B1 (en) 2010-11-18 2021-08-17 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11031275B2 (en) 2010-11-18 2021-06-08 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11784082B2 (en) 2010-11-18 2023-10-10 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11164770B1 (en) 2010-11-18 2021-11-02 Monolithic 3D Inc. Method for producing a 3D semiconductor memory device and structure
US11735462B2 (en) 2010-11-18 2023-08-22 Monolithic 3D Inc. 3D semiconductor device and structure with single-crystal layers
US11355381B2 (en) 2010-11-18 2022-06-07 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11495484B2 (en) 2010-11-18 2022-11-08 Monolithic 3D Inc. 3D semiconductor devices and structures with at least two single-crystal layers
US11482438B2 (en) 2010-11-18 2022-10-25 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11107721B2 (en) 2010-11-18 2021-08-31 Monolithic 3D Inc. 3D semiconductor device and structure with NAND logic
US8546961B2 (en) 2011-01-10 2013-10-01 International Business Machines Corporation Alignment marks to enable 3D integration
US8563396B2 (en) 2011-01-29 2013-10-22 International Business Machines Corporation 3D integration method using SOI substrates and structures produced thereby
US20130010165A1 (en) * 2011-07-05 2013-01-10 United Microelectronics Corp. Optical micro structure, method for fabricating the same and applications thereof
US9496255B2 (en) 2011-11-16 2016-11-15 Qualcomm Incorporated Stacked CMOS chipset having an insulating layer and a secondary layer and method of forming same
US11881443B2 (en) 2012-04-09 2024-01-23 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11476181B1 (en) 2012-04-09 2022-10-18 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11735501B1 (en) 2012-04-09 2023-08-22 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11088050B2 (en) 2012-04-09 2021-08-10 Monolithic 3D Inc. 3D semiconductor device with isolation layers
US11164811B2 (en) 2012-04-09 2021-11-02 Monolithic 3D Inc. 3D semiconductor device with isolation layers and oxide-to-oxide bonding
US11594473B2 (en) 2012-04-09 2023-02-28 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11616004B1 (en) 2012-04-09 2023-03-28 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11410912B2 (en) 2012-04-09 2022-08-09 Monolithic 3D Inc. 3D semiconductor device with vias and isolation layers
US10600888B2 (en) 2012-04-09 2020-03-24 Monolithic 3D Inc. 3D semiconductor device
US11694944B1 (en) 2012-04-09 2023-07-04 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US8563403B1 (en) 2012-06-27 2013-10-22 International Business Machines Corporation Three dimensional integrated circuit integration using alignment via/dielectric bonding first and through via formation last
US11961827B1 (en) 2012-12-22 2024-04-16 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11916045B2 (en) 2012-12-22 2024-02-27 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11967583B2 (en) 2012-12-22 2024-04-23 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11309292B2 (en) 2012-12-22 2022-04-19 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US12051674B2 (en) 2012-12-22 2024-07-30 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11018116B2 (en) 2012-12-22 2021-05-25 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US11217565B2 (en) 2012-12-22 2022-01-04 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US11784169B2 (en) 2012-12-22 2023-10-10 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US10811395B2 (en) * 2012-12-22 2020-10-20 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US11063024B1 (en) 2012-12-22 2021-07-13 Monlithic 3D Inc. Method to form a 3D semiconductor device and structure
US11004694B1 (en) 2012-12-29 2021-05-11 Monolithic 3D Inc. 3D semiconductor device and structure
US10600657B2 (en) 2012-12-29 2020-03-24 Monolithic 3D Inc 3D semiconductor device and structure
US11087995B1 (en) 2012-12-29 2021-08-10 Monolithic 3D Inc. 3D semiconductor device and structure
US11430668B2 (en) 2012-12-29 2022-08-30 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US10651054B2 (en) 2012-12-29 2020-05-12 Monolithic 3D Inc. 3D semiconductor device and structure
US11177140B2 (en) 2012-12-29 2021-11-16 Monolithic 3D Inc. 3D semiconductor device and structure
US10892169B2 (en) 2012-12-29 2021-01-12 Monolithic 3D Inc. 3D semiconductor device and structure
US10903089B1 (en) 2012-12-29 2021-01-26 Monolithic 3D Inc. 3D semiconductor device and structure
US11430667B2 (en) 2012-12-29 2022-08-30 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US10325651B2 (en) 2013-03-11 2019-06-18 Monolithic 3D Inc. 3D semiconductor device with stacked memory
US11935949B1 (en) 2013-03-11 2024-03-19 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and memory cells
US12094965B2 (en) 2013-03-11 2024-09-17 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and memory cells
US8902663B1 (en) 2013-03-11 2014-12-02 Monolithic 3D Inc. Method of maintaining a memory state
US11869965B2 (en) 2013-03-11 2024-01-09 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and memory cells
US11088130B2 (en) 2014-01-28 2021-08-10 Monolithic 3D Inc. 3D semiconductor device and structure
US11398569B2 (en) 2013-03-12 2022-07-26 Monolithic 3D Inc. 3D semiconductor device and structure
US11923374B2 (en) 2013-03-12 2024-03-05 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US12100646B2 (en) 2013-03-12 2024-09-24 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US10840239B2 (en) 2014-08-26 2020-11-17 Monolithic 3D Inc. 3D semiconductor device and structure
US9536777B2 (en) * 2013-03-13 2017-01-03 Taiwan Semiconductor Manufacutring Company, Ltd. Interconnect apparatus and method
US10224279B2 (en) 2013-03-15 2019-03-05 Monolithic 3D Inc. Semiconductor device and structure
US11341309B1 (en) 2013-04-15 2022-05-24 Monolithic 3D Inc. Automation for monolithic 3D devices
US11574109B1 (en) 2013-04-15 2023-02-07 Monolithic 3D Inc Automation methods for 3D integrated circuits and devices
US11270055B1 (en) 2013-04-15 2022-03-08 Monolithic 3D Inc. Automation for monolithic 3D devices
US11720736B2 (en) 2013-04-15 2023-08-08 Monolithic 3D Inc. Automation methods for 3D integrated circuits and devices
US11030371B2 (en) 2013-04-15 2021-06-08 Monolithic 3D Inc. Automation for monolithic 3D devices
US11487928B2 (en) 2013-04-15 2022-11-01 Monolithic 3D Inc. Automation for monolithic 3D devices
US9021414B1 (en) 2013-04-15 2015-04-28 Monolithic 3D Inc. Automation for monolithic 3D devices
US9929050B2 (en) * 2013-07-16 2018-03-27 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming three-dimensional integrated circuit (3DIC) stacking structure
JP6330151B2 (ja) * 2013-09-17 2018-05-30 パナソニックＩｐマネジメント株式会社 半導体装置及びその製造方法
US10163897B2 (en) 2013-11-15 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Inter-level connection for multi-layer structures
US10056353B2 (en) * 2013-12-19 2018-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC interconnect apparatus and method
US9559040B2 (en) * 2013-12-30 2017-01-31 International Business Machines Corporation Double-sided segmented line architecture in 3D integration
US10297586B2 (en) 2015-03-09 2019-05-21 Monolithic 3D Inc. Methods for processing a 3D semiconductor device
US11107808B1 (en) 2014-01-28 2021-08-31 Monolithic 3D Inc. 3D semiconductor device and structure
US11031394B1 (en) 2014-01-28 2021-06-08 Monolithic 3D Inc. 3D semiconductor device and structure
US12094829B2 (en) 2014-01-28 2024-09-17 Monolithic 3D Inc. 3D semiconductor device and structure
JP2015173144A (ja) * 2014-03-11 2015-10-01 株式会社東芝 配線基板とそれを用いた半導体装置
US9449914B2 (en) 2014-07-17 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated circuits with redistribution lines
US10319701B2 (en) * 2015-01-07 2019-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded 3D integrated circuit (3DIC) structure
US10825779B2 (en) 2015-04-19 2020-11-03 Monolithic 3D Inc. 3D semiconductor device and structure
US11011507B1 (en) 2015-04-19 2021-05-18 Monolithic 3D Inc. 3D semiconductor device and structure
US11056468B1 (en) 2015-04-19 2021-07-06 Monolithic 3D Inc. 3D semiconductor device and structure
US10381328B2 (en) 2015-04-19 2019-08-13 Monolithic 3D Inc. Semiconductor device and structure
CN106158853B (zh) * 2015-04-24 2019-05-21 中国科学院微电子研究所 一种集成电路结构及其制造方法、半导体器件
US9704827B2 (en) 2015-06-25 2017-07-11 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid bond pad structure
US11956952B2 (en) 2015-08-23 2024-04-09 Monolithic 3D Inc. Semiconductor memory device and structure
US9691695B2 (en) 2015-08-31 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure
US11937422B2 (en) 2015-11-07 2024-03-19 Monolithic 3D Inc. Semiconductor memory device and structure
US11978731B2 (en) 2015-09-21 2024-05-07 Monolithic 3D Inc. Method to produce a multi-level semiconductor memory device and structure
CN115942752A (zh) 2015-09-21 2023-04-07 莫诺利特斯3D有限公司 3d半导体器件和结构
US11114427B2 (en) 2015-11-07 2021-09-07 Monolithic 3D Inc. 3D semiconductor processor and memory device and structure
US12100658B2 (en) 2015-09-21 2024-09-24 Monolithic 3D Inc. Method to produce a 3D multilayer semiconductor device and structure
US11297258B2 (en) * 2015-10-01 2022-04-05 Qualcomm Incorporated High dynamic range solid state image sensor and camera system
US10522225B1 (en) 2015-10-02 2019-12-31 Monolithic 3D Inc. Semiconductor device with non-volatile memory
US12120880B1 (en) 2015-10-24 2024-10-15 Monolithic 3D Inc. 3D semiconductor device and structure with logic and memory
US12035531B2 (en) 2015-10-24 2024-07-09 Monolithic 3D Inc. 3D semiconductor device and structure with logic and memory
US10847540B2 (en) 2015-10-24 2020-11-24 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11114464B2 (en) 2015-10-24 2021-09-07 Monolithic 3D Inc. 3D semiconductor device and structure
US10418369B2 (en) 2015-10-24 2019-09-17 Monolithic 3D Inc. Multi-level semiconductor memory device and structure
US11991884B1 (en) 2015-10-24 2024-05-21 Monolithic 3D Inc. 3D semiconductor device and structure with logic and memory
US11296115B1 (en) 2015-10-24 2022-04-05 Monolithic 3D Inc. 3D semiconductor device and structure
US12016181B2 (en) 2015-10-24 2024-06-18 Monolithic 3D Inc. 3D semiconductor device and structure with logic and memory
US9881896B2 (en) 2015-12-17 2018-01-30 International Business Machines Corporation Advanced chip to wafer stacking
US10510592B2 (en) 2016-07-25 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit (IC) structure for high performance and functional density
US10367031B2 (en) * 2016-09-13 2019-07-30 Imec Vzw Sequential integration process
US11869591B2 (en) 2016-10-10 2024-01-09 Monolithic 3D Inc. 3D memory devices and structures with control circuits
US11711928B2 (en) 2016-10-10 2023-07-25 Monolithic 3D Inc. 3D memory devices and structures with control circuits
US11251149B2 (en) 2016-10-10 2022-02-15 Monolithic 3D Inc. 3D memory device and structure
US11329059B1 (en) 2016-10-10 2022-05-10 Monolithic 3D Inc. 3D memory devices and structures with thinned single crystal substrates
US11812620B2 (en) 2016-10-10 2023-11-07 Monolithic 3D Inc. 3D DRAM memory devices and structures with control circuits
US11930648B1 (en) 2016-10-10 2024-03-12 Monolithic 3D Inc. 3D memory devices and structures with metal layers
US10020223B1 (en) 2017-04-12 2018-07-10 International Business Machines Corporation Reduced tip-to-tip and via pitch at line end
US10163864B1 (en) 2017-08-16 2018-12-25 Globalfoundries Inc. Vertically stacked wafers and methods of forming same
US10651153B2 (en) * 2018-06-18 2020-05-12 Intel Corporation Three-dimensional (3D) memory with shared control circuitry using wafer-to-wafer bonding
CN109148498B (zh) * 2018-08-14 2021-06-15 武汉新芯集成电路制造有限公司 一种高存储容量的三维键合传感器的结构及其制造方法
US11205620B2 (en) * 2018-09-18 2021-12-21 International Business Machines Corporation Method and apparatus for supplying power to VLSI silicon chips
US11296106B2 (en) 2019-04-08 2022-04-05 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11018156B2 (en) 2019-04-08 2021-05-25 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US10892016B1 (en) 2019-04-08 2021-01-12 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11158652B1 (en) 2019-04-08 2021-10-26 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11763864B2 (en) 2019-04-08 2023-09-19 Monolithic 3D Inc. 3D memory semiconductor devices and structures with bit-line pillars
CN110192269A (zh) 2019-04-15 2019-08-30 长江存储科技有限责任公司 三维nand存储器件与多个功能芯片的集成
US11056426B2 (en) 2019-05-29 2021-07-06 International Business Machines Corporation Metallization interconnect structure formation
US11600519B2 (en) * 2019-09-16 2023-03-07 International Business Machines Corporation Skip-via proximity interconnect
US11355464B2 (en) * 2020-11-10 2022-06-07 Nanya Technology Corporation Semiconductor device structure with bottle-shaped through silicon via and method for forming the same
US11842979B2 (en) * 2021-03-11 2023-12-12 Nanya Technology Corporation Semiconductor device and method of manufacturing the same
US11876077B2 (en) * 2021-03-12 2024-01-16 Nanya Technology Corporation Semiconductor device and method of manufacturing the same
KR20230033397A (ko) * 2021-09-01 2023-03-08 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US12074094B2 (en) * 2022-02-11 2024-08-27 Micron Technology, Inc. Monolithic conductive column in a semiconductor device and associated methods
DE102022211198A1 (de) 2022-10-21 2024-05-02 Robert Bosch Gesellschaft mit beschränkter Haftung Verfahren zur Herstellung eines mikromechanischen Bauelements

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5489554A (en) * 1992-07-21 1996-02-06 Hughes Aircraft Company Method of making a 3-dimensional circuit assembly having electrical contacts that extend through the IC layer
US20060286767A1 (en) * 2005-06-17 2006-12-21 Clarke Rowland C Novel thinning process for 3 - dimensional integration via wafer bonding

Family Cites Families (111)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1166681B (it) 1979-03-09 1987-05-06 Montedison Spa Piretroidi
US4939101A (en) * 1988-09-06 1990-07-03 General Electric Company Method of making direct bonded wafers having a void free interface
KR960009074A (ko) * 1994-08-29 1996-03-22 모리시다 요이치 반도체 장치 및 그 제조방법
US6809421B1 (en) 1996-12-02 2004-10-26 Kabushiki Kaisha Toshiba Multichip semiconductor device, chip therefor and method of formation thereof
US5889302A (en) * 1997-04-21 1999-03-30 Advanced Micro Devices, Inc. Multilayer floating gate field effect transistor structure for use in integrated circuit devices
US6984571B1 (en) 1999-10-01 2006-01-10 Ziptronix, Inc. Three dimensional device integration method and integrated device
JP3750444B2 (ja) 1999-10-22 2006-03-01 セイコーエプソン株式会社 半導体装置の製造方法
US6577013B1 (en) 2000-09-05 2003-06-10 Amkor Technology, Inc. Chip size semiconductor packages with stacked dies
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US7354798B2 (en) 2002-12-20 2008-04-08 International Business Machines Corporation Three-dimensional device fabrication method
US6821826B1 (en) 2003-09-30 2004-11-23 International Business Machines Corporation Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers
US7091124B2 (en) 2003-11-13 2006-08-15 Micron Technology, Inc. Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices
WO2005122706A2 (en) 2004-05-31 2005-12-29 Joon-Mo Kang Method of aligning semiconductor device and semiconductor structure thereof
US7232754B2 (en) 2004-06-29 2007-06-19 Micron Technology, Inc. Microelectronic devices and methods for forming interconnects in microelectronic devices
US7312487B2 (en) 2004-08-16 2007-12-25 International Business Machines Corporation Three dimensional integrated circuit
US7083425B2 (en) 2004-08-27 2006-08-01 Micron Technology, Inc. Slanted vias for electrical circuits on circuit boards and other substrates
US7300857B2 (en) 2004-09-02 2007-11-27 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
US7326629B2 (en) 2004-09-10 2008-02-05 Agency For Science, Technology And Research Method of stacking thin substrates by transfer bonding
TWI261733B (en) 2004-12-28 2006-09-11 Ind Tech Res Inst Alignment method of using alignment marks on wafer edge
US7271482B2 (en) 2004-12-30 2007-09-18 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US7354862B2 (en) 2005-04-18 2008-04-08 Intel Corporation Thin passivation layer on 3D devices
US20060278979A1 (en) 2005-06-09 2006-12-14 Intel Corporation Die stacking recessed pad wafer design
US7795134B2 (en) 2005-06-28 2010-09-14 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US7262134B2 (en) 2005-09-01 2007-08-28 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7863187B2 (en) 2005-09-01 2011-01-04 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7410884B2 (en) 2005-11-21 2008-08-12 Intel Corporation 3D integrated circuits using thick metal for backside connections and offset bumps
US7514116B2 (en) 2005-12-30 2009-04-07 Intel Corporation Horizontal Carbon Nanotubes by Vertical Growth and Rolling
US7626257B2 (en) 2006-01-18 2009-12-01 Infineon Technologies Ag Semiconductor devices and methods of manufacture thereof
KR100743648B1 (ko) 2006-03-17 2007-07-27 주식회사 하이닉스반도체 웨이퍼 레벨 시스템 인 패키지의 제조방법
KR100753415B1 (ko) 2006-03-17 2007-08-30 주식회사 하이닉스반도체 스택 패키지
US7898095B2 (en) 2006-03-20 2011-03-01 Tezzaron Semiconductor, Inc. Fiducial scheme adapted for stacked integrated circuits
US7692310B2 (en) 2006-03-27 2010-04-06 Intel Corporation Forming a hybrid device
US7378339B2 (en) 2006-03-30 2008-05-27 Freescale Semiconductor, Inc. Barrier for use in 3-D integration of circuits
JP3942190B1 (ja) 2006-04-25 2007-07-11 国立大学法人九州工業大学 両面電極構造の半導体装置及びその製造方法
US7749899B2 (en) 2006-06-01 2010-07-06 Micron Technology, Inc. Microelectronic workpieces and methods and systems for forming interconnects in microelectronic workpieces
KR100769144B1 (ko) 2006-07-24 2007-10-22 동부일렉트로닉스 주식회사 에스아이피 구조의 반도체 장치 및 그 제조방법
US7629249B2 (en) 2006-08-28 2009-12-08 Micron Technology, Inc. Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods
US7902643B2 (en) 2006-08-31 2011-03-08 Micron Technology, Inc. Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods
US7427803B2 (en) 2006-09-22 2008-09-23 Taiwan Semiconductor Manufacturing Company, Ltd. Electromagnetic shielding using through-silicon vias
US7666768B2 (en) 2006-09-29 2010-02-23 Intel Corporation Through-die metal vias with a dispersed phase of graphitic structures of carbon for reduced thermal expansion and increased electrical conductance
KR100800161B1 (ko) 2006-09-30 2008-02-01 주식회사 하이닉스반도체 관통 실리콘 비아 형성방법
JP2008153499A (ja) 2006-12-19 2008-07-03 Sharp Corp 半導体装置の製造方法
US7812459B2 (en) 2006-12-19 2010-10-12 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional integrated circuits with protection layers
US7494846B2 (en) 2007-03-09 2009-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. Design techniques for stacking identical memory dies
US7598523B2 (en) 2007-03-19 2009-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Test structures for stacking dies having through-silicon vias
US7795735B2 (en) 2007-03-21 2010-09-14 Taiwan Semiconductor Manufacturing Co., Ltd. Methods for forming single dies with multi-layer interconnect structures and structures formed therefrom
JP2008294423A (ja) 2007-04-24 2008-12-04 Nec Electronics Corp 半導体装置
US7564115B2 (en) 2007-05-16 2009-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Tapered through-silicon via structure
US7883938B2 (en) 2007-05-22 2011-02-08 United Test And Assembly Center Ltd. Stacked die semiconductor package and method of assembly
KR100895813B1 (ko) 2007-06-20 2009-05-06 주식회사 하이닉스반도체 반도체 패키지의 제조 방법
KR100871382B1 (ko) 2007-06-26 2008-12-02 주식회사 하이닉스반도체 관통 실리콘 비아 스택 패키지 및 그의 제조 방법
US7939941B2 (en) 2007-06-27 2011-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of through via before contact processing
US7692946B2 (en) 2007-06-29 2010-04-06 Intel Corporation Memory array on more than one die
US7902069B2 (en) 2007-08-02 2011-03-08 International Business Machines Corporation Small area, robust silicon via structure and process
TWI341554B (en) 2007-08-02 2011-05-01 Enthone Copper metallization of through silicon via
KR101481571B1 (ko) 2007-08-21 2015-01-14 삼성전자주식회사 반도체 패키지 장치 및 그의 제작방법
US7973413B2 (en) 2007-08-24 2011-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate via for semiconductor device
SG150410A1 (en) 2007-08-31 2009-03-30 Micron Technology Inc Partitioned through-layer via and associated systems and methods
US7692448B2 (en) 2007-09-12 2010-04-06 Neal Solomon Reprogrammable three dimensional field programmable gate arrays
US7772880B2 (en) 2007-09-12 2010-08-10 Neal Solomon Reprogrammable three dimensional intelligent system on a chip
US7958627B2 (en) 2007-09-24 2011-06-14 Kemet Electronics Corporation Method of attaching an electronic device to an MLCC having a curved surface
KR101448150B1 (ko) 2007-10-04 2014-10-08 삼성전자주식회사 메모리 칩이 적층된 멀티 칩 패키지 메모리, 메모리 칩의적층 방법 및 멀티 칩 패키지 메모리의 동작 제어 방법
JP2009124087A (ja) 2007-11-19 2009-06-04 Oki Semiconductor Co Ltd 半導体装置の製造方法
JP5159273B2 (ja) 2007-11-28 2013-03-06 ルネサスエレクトロニクス株式会社 電子装置の製造方法
US7884015B2 (en) 2007-12-06 2011-02-08 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US7791175B2 (en) 2007-12-20 2010-09-07 Mosaid Technologies Incorporated Method for stacking serially-connected integrated circuits and multi-chip device made from same
US7843064B2 (en) 2007-12-21 2010-11-30 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and process for the formation of TSVs
US7750459B2 (en) 2008-02-01 2010-07-06 International Business Machines Corporation Integrated module for data processing system
US7777330B2 (en) 2008-02-05 2010-08-17 Freescale Semiconductor, Inc. High bandwidth cache-to-processing unit communication in a multiple processor/cache system
US7803714B2 (en) 2008-03-31 2010-09-28 Freescale Semiconductor, Inc. Semiconductor through silicon vias of variable size and method of formation
US7821107B2 (en) 2008-04-22 2010-10-26 Micron Technology, Inc. Die stacking with an annular via having a recessed socket
US7838967B2 (en) 2008-04-24 2010-11-23 Powertech Technology Inc. Semiconductor chip having TSV (through silicon via) and stacked assembly including the chips
US7666711B2 (en) 2008-05-27 2010-02-23 Stats Chippac, Ltd. Semiconductor device and method of forming double-sided through vias in saw streets
US7838975B2 (en) 2008-05-27 2010-11-23 Mediatek Inc. Flip-chip package with fan-out WLCSP
US7741156B2 (en) 2008-05-27 2010-06-22 Stats Chippac, Ltd. Semiconductor device and method of forming through vias with reflowed conductive material
US7863721B2 (en) 2008-06-11 2011-01-04 Stats Chippac, Ltd. Method and apparatus for wafer level integration using tapered vias
KR101462604B1 (ko) 2008-06-23 2014-11-20 삼성전자주식회사 반도체 장치 및 멀티-칩 패키지
US7888668B2 (en) 2008-07-17 2011-02-15 United Microelectronics Corp. Phase change memory
US7813043B2 (en) 2008-08-15 2010-10-12 Ether Precision, Inc. Lens assembly and method of manufacture
US7776741B2 (en) 2008-08-18 2010-08-17 Novellus Systems, Inc. Process for through silicon via filing
US7848153B2 (en) 2008-08-19 2010-12-07 Qimonda Ag High speed memory architecture
US8014166B2 (en) 2008-09-06 2011-09-06 Broadpak Corporation Stacking integrated circuits containing serializer and deserializer blocks using through silicon via
US7872332B2 (en) 2008-09-11 2011-01-18 Micron Technology, Inc. Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods
JP5331427B2 (ja) 2008-09-29 2013-10-30 株式会社日立製作所 半導体装置
US7936052B2 (en) 2008-09-30 2011-05-03 Infineon Technologies Ag On-chip RF shields with backside redistribution lines
US7875948B2 (en) 2008-10-21 2011-01-25 Jaroslav Hynecek Backside illuminated image sensor
US7825024B2 (en) 2008-11-25 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming through-silicon vias
US7838337B2 (en) 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias
US7989318B2 (en) 2008-12-08 2011-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for stacking semiconductor dies
US7795650B2 (en) 2008-12-09 2010-09-14 Teledyne Scientific & Imaging Llc Method and apparatus for backside illuminated image sensors using capacitively coupled readout integrated circuits
US7741148B1 (en) 2008-12-10 2010-06-22 Stats Chippac, Ltd. Semiconductor device and method of forming an interconnect structure for 3-D devices using encapsulant for structural support
US7859099B2 (en) 2008-12-11 2010-12-28 Stats Chippac Ltd. Integrated circuit packaging system having through silicon via with direct interconnects and method of manufacture thereof
US7786008B2 (en) 2008-12-12 2010-08-31 Stats Chippac Ltd. Integrated circuit packaging system having through silicon vias with partial depth metal fill regions and method of manufacture thereof
US7863106B2 (en) 2008-12-24 2011-01-04 International Business Machines Corporation Silicon interposer testing for three dimensional chip stack
US7910473B2 (en) 2008-12-31 2011-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon via with air gap
US7893529B2 (en) 2009-01-12 2011-02-22 International Business Machines Corporation Thermoelectric 3D cooling
US7943473B2 (en) 2009-01-13 2011-05-17 Maxim Integrated Products, Inc. Minimum cost method for forming high density passive capacitors for replacement of discrete board capacitors using a minimum cost 3D wafer-to-wafer modular integration scheme
US7884016B2 (en) 2009-02-12 2011-02-08 Asm International, N.V. Liner materials and related processes for 3-D integration
US7904273B2 (en) 2009-02-16 2011-03-08 International Business Machines Corporation In-line depth measurement for thru silicon via
US7759165B1 (en) 2009-03-01 2010-07-20 Rajeev Bajaj Nanospring
TWI466258B (zh) 2009-04-10 2014-12-21 Nanya Technology Corp 電性通透連接及其形成方法
US7960242B2 (en) 2009-04-14 2011-06-14 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US7964916B2 (en) 2009-04-14 2011-06-21 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US7986042B2 (en) 2009-04-14 2011-07-26 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US9406561B2 (en) 2009-04-20 2016-08-02 International Business Machines Corporation Three dimensional integrated circuit integration using dielectric bonding first and through via formation last
US7939369B2 (en) 2009-05-14 2011-05-10 International Business Machines Corporation 3D integration structure and method using bonded metal planes
US7960282B2 (en) 2009-05-21 2011-06-14 Globalfoundries Singapore Pte. Ltd. Method of manufacture an integrated circuit system with through silicon via
JP4505035B1 (ja) 2009-06-02 2010-07-14 パナソニック株式会社 ステレオマイクロホン装置
US7900519B2 (en) 2009-06-11 2011-03-08 Qualcomm Incorporated Microfluidic measuring tool to measure through-silicon via depth
US7867821B1 (en) 2009-09-18 2011-01-11 Stats Chippac Ltd. Integrated circuit package system with through semiconductor vias and method of manufacture thereof
JP5518879B2 (ja) 2009-09-21 2014-06-11 株式会社東芝 ３次元集積回路製造方法、及び装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5489554A (en) * 1992-07-21 1996-02-06 Hughes Aircraft Company Method of making a 3-dimensional circuit assembly having electrical contacts that extend through the IC layer
US20060286767A1 (en) * 2005-06-17 2006-12-21 Clarke Rowland C Novel thinning process for 3 - dimensional integration via wafer bonding

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI501192B (zh) * 2012-07-06 2015-09-21 Nvidia Corp 位於圖形處理單元〈ＧＰＵs〉上之動態隨機存取記憶體〈ＤＲＡＭs〉的替代立體〈３Ｄ〉堆疊架構
US9343449B2 (en) 2012-07-06 2016-05-17 Nvidia Corporation Alternative 3D stacking scheme for DRAMs atop GPUs
CN103066093B (zh) * 2013-01-14 2015-12-09 武汉新芯集成电路制造有限公司 一种用深槽隔离制造影像传感器的方法及影像传感器结构
CN103066093A (zh) * 2013-01-14 2013-04-24 陆伟 一种用深槽隔离制造影像传感器的方法及影像传感器结构
CN103972151A (zh) * 2013-01-31 2014-08-06 旺宏电子股份有限公司 连接叠层结构的导电层的中间连接件的形成方法
CN103972151B (zh) * 2013-01-31 2016-06-29 旺宏电子股份有限公司 连接叠层结构的导电层的中间连接件的形成方法
CN104657533A (zh) * 2013-11-18 2015-05-27 台湾积体电路制造股份有限公司 Feol/mol/beol中的不同缩放比率
CN104657533B (zh) * 2013-11-18 2018-01-26 台湾积体电路制造股份有限公司 不同缩放比率的集成芯片设计方法及eda工具
CN104752366A (zh) * 2013-12-27 2015-07-01 国际商业机器公司 用于制造3d集成方案的结构和方法
CN112164688A (zh) * 2017-07-21 2021-01-01 联华电子股份有限公司 芯片堆叠结构及管芯堆叠结构的制造方法
CN112164688B (zh) * 2017-07-21 2023-06-13 联华电子股份有限公司 芯片堆叠结构及管芯堆叠结构的制造方法
CN108766893A (zh) * 2018-05-31 2018-11-06 德淮半导体有限公司 半导体装置及其制造方法
CN109148469A (zh) * 2018-08-01 2019-01-04 长江存储科技有限责任公司 存储器结构及其制造方法
CN109148469B (zh) * 2018-08-01 2020-08-25 长江存储科技有限责任公司 存储器结构及其制造方法
CN109473436B (zh) * 2018-11-15 2020-05-26 长江存储科技有限责任公司 半导体器件及其形成方法
CN109473436A (zh) * 2018-11-15 2019-03-15 长江存储科技有限责任公司 半导体器件及其形成方法
CN109560099A (zh) * 2018-11-29 2019-04-02 德淮半导体有限公司 用于等离子体损伤检测的半导体器件及其检测方法、形成方法
CN111354736A (zh) * 2018-12-22 2020-06-30 艾克瑟尔西斯公司 3d nand高长径比串和沟道
US11404439B2 (en) 2018-12-22 2022-08-02 Xcelsis Corporation 3D NAND—high aspect ratio strings and channels
US12035529B2 (en) 2018-12-22 2024-07-09 Adeia Semiconductor Inc. 3D NAND—high aspect ratio strings and channels
CN112164674A (zh) * 2020-09-24 2021-01-01 芯盟科技有限公司 堆叠式高带宽存储器
CN118471932A (zh) * 2024-07-09 2024-08-09 武汉新芯集成电路股份有限公司 半导体器件及其制备方法
CN118471932B (zh) * 2024-07-09 2024-10-01 武汉新芯集成电路股份有限公司 半导体器件及其制备方法

Also Published As

Publication number Publication date
EP2422366A1 (en) 2012-02-29
EP2422366A4 (en) 2014-01-22
WO2010123691A1 (en) 2010-10-28
US9406561B2 (en) 2016-08-02
US20100264551A1 (en) 2010-10-21

Similar Documents

Publication Publication Date Title
CN102341907A (zh) 使用先介电键合后通孔形成的三维集成电路的集成
US8563403B1 (en) Three dimensional integrated circuit integration using alignment via/dielectric bonding first and through via formation last
US11456284B2 (en) Microelectronic device assemblies and packages and related methods
US8421193B2 (en) Integrated circuit device having through via and method for preparing the same
US7943473B2 (en) Minimum cost method for forming high density passive capacitors for replacement of discrete board capacitors using a minimum cost 3D wafer-to-wafer modular integration scheme
US7700410B2 (en) Chip-in-slot interconnect for 3D chip stacks
KR20130053338A (ko) Ｔｓｖ 구조를 구비한 집적회로 소자
US20210343650A1 (en) Power distribution structure and method
CN203085525U (zh) 可用于堆叠的集成电路
EP3048642A1 (en) Semiconductor package structure and method for forming the same
US11417587B2 (en) Package structure and method of fabricating the same
US20130026612A1 (en) Method of shielding through silicon vias in a passive interposer
CN106057776B (zh) 包括以三维堆叠布置接合的集成电路装置的电子封装件
US11948921B2 (en) Methods of forming stacked semiconductors die assemblies
US20220375902A1 (en) Microelectronic device assemblies and packages and related methods and systems
KR101223541B1 (ko) 반도체 칩, 및 이를 포함하는 멀티 칩 패키지
CN113671625A (zh) 基于硅光转接板技术的硅基光电子器件及制备方法
KR20140038195A (ko) Ｔｓｖ구조 형성 방법
US20230369292A1 (en) Chip stacking structure and preparation method thereof, chip stacking package, and electronic device
US20240071823A1 (en) Semiconductor device circuitry formed through volumetric expansion
CN108091623B (zh) 基于bjt的系统级封装抗静电转接板
CN117995795A (zh) 芯片、芯片堆叠结构、芯片封装结构以及电子设备
CN115732400A (zh) 半导体装置与其制造方法
CN114446961A (zh) 中介板结构及其制造方法
US20170117353A1 (en) Circuit board and electronic device

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20120201