CN109390312A - 半导体封装装置和其制造方法 - Google Patents

半导体封装装置和其制造方法 Download PDF

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Publication number
CN109390312A
CN109390312A CN201810528317.0A CN201810528317A CN109390312A CN 109390312 A CN109390312 A CN 109390312A CN 201810528317 A CN201810528317 A CN 201810528317A CN 109390312 A CN109390312 A CN 109390312A
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passivation layer
layer
opening
conducting element
conductive structure
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CN201810528317.0A
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CN109390312B (zh
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吕文隆
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

一种半导体封装装置，其包括钝化层、导电元件、重新分布层RDL和电子组件。所述钝化层具有第一表面和与所述第一表面相对的第二表面。所述导电元件在所述钝化层内。所述导电元件界定面向所述钝化层的所述第二表面的凹槽。所述RDL在所述钝化层上且与所述导电元件电连接。所述电子组件安置于所述RDL上且与所述RDL电连接。

Description

半导体封装装置和其制造方法
技术领域
本公开大体上涉及一种半导体封装装置和其制造方法。更具体地说，本公开涉及包含焊接垫结构的半导体封装装置和其制造方法。
背景技术
半导体封装装置可包含将电子组件电连接到衬底的焊球。在相当的半导体封装装置中，焊球可直接地接合到平坦焊垫。那些焊垫被称作“防焊剂限定(SMD)”类型焊垫。然而，焊球与焊垫之间的连接通常不可承受相对较大的侧向应力，因为这可能导致焊球的脱层。
当试图解决上述问题时，焊垫的侧表面可从衬底露出且焊球连接到焊垫的侧表面和底表面两者。此种类型的焊垫也被称作“非防焊剂限定(NSMD)”类型焊垫。然而，归因于焊垫的侧表面和底表面上不均匀的障壁层(例如，障壁层在侧表面上相对较薄且在底表面上相对较厚)，可形成不均匀的金属间化合物(IMC)(例如，IMC层在侧表面上相对较厚且在底表面上相对较薄)。IMC的相对较厚部分可能易于开裂。此外，归因于焊垫的侧表面与衬底的介电层之间形成的间隙和/或间隙中的污染，错误焊接可发生。
发明内容
在一或多个实施例中，导电结构包括钝化层、由钝化层环绕的导电元件和邻近于导电元件的导电接触件。导电元件具有第一表面和邻近于第一表面的第二表面。第一表面与第二表面之间的角度大于约90度。导电接触件邻近于导电元件且与导电元件的第一表面和第二表面电连接。
在一或多个实施例中，导电结构包括钝化层和导电元件。钝化层具有第一表面和与第一表面相对的第二表面。钝化层界定从钝化层的第一表面朝向钝化层的第二表面逐渐变窄的第一开口。导电元件在第一开口内。导电元件界定朝向钝化层的第二表面的凹槽。
在一或多个实施例中，半导体封装装置包括钝化层、导电元件、重新分布层(RDL)和电子组件。钝化层具有第一表面和与第一表面相对的第二表面。导电元件在钝化层内。导电元件界定面向钝化层的第二表面的凹槽。RDL在钝化层上且与导电元件电连接。电子组件安置于RDL上且与RDL电连接。
附图说明
当结合附图阅读时，从以下详细描述最好地理解本公开的各方面。应注意，各种特征可能未按比例绘制，且出于论述的清楚起见，各种特征的尺寸可任意增大或减小。
图1A说明根据本公开的一些实施例的半导体封装装置的横截面视图；
图1B说明根据本公开的一些实施例的图1A的半导体封装装置的部分的放大视图；
图1C说明根据本公开的一些实施例的图1A的半导体封装装置的部分的放大视图；
图1D说明根据本公开的一些实施例的图1A的半导体封装装置的部分的放大视图；
图2A说明根据本公开的一些实施例的半导体封装装置的横截面视图；
图2B说明根据本公开的一些实施例的半导体封装装置的横截面视图；
图3A说明根据本公开的一些实施例的制造半导体封装装置的方法的一或多个阶段；
图3B说明根据本公开的一些实施例的制造半导体封装装置的方法的一或多个阶段；
图3C说明根据本公开的一些实施例的制造半导体封装装置的方法的一或多个阶段；
图3D说明根据本公开的一些实施例的制造半导体封装装置的方法的一或多个阶段；
图3E说明根据本公开的一些实施例的制造半导体封装装置的方法的一或多个阶段；
图3F说明根据本公开的一些实施例的制造半导体封装装置的方法的一或多个阶段；
图3G说明根据本公开的一些实施例的制造半导体封装装置的方法的一或多个阶段；
图3H说明根据本公开的一些实施例的制造半导体封装装置的方法的一或多个阶段；
图3I说明根据本公开的一些实施例的制造半导体封装装置的方法的一或多个阶段；
图4A说明根据本公开的一些实施例的各种类型的半导体封装装置；且
图4B说明根据本公开的一些实施例的各种类型的半导体封装装置。
贯穿图式和详细描述使用共同参考标号指示相同或类似元件。根据以下结合附图作出的详细描述，本公开将更显而易见。
具体实施方式
图1A说明根据本公开的一些实施例的半导体封装装置1的横截面视图。半导体封装装置1包含钝化层10、介电层11、电子组件12、封装体13、互连结构14(也被称作导电元件)和电接触件15。
钝化层10具有顶表面101(也被称作第一表面)和与顶表面相对的底表面102(也被称作第二表面)。在一些实施例中，钝化层10包含氧化硅、氮化硅、氧化镓、氧化铝、氧化钪、氧化锆、氧化镧、氧化铪、另一氧化物、另一氮化物，或其中的两个或多于两个的组合。在一些实施例中，钝化层10可取决于各种实施例的规范被替换为防焊剂液体(例如，以油墨形式)或膜。
钝化层10界定从顶表面101朝向底表面102逐渐变窄的第一开口，和从底表面102朝向顶表面101逐渐变窄的的第二开口。第一开口和第二开口经连接以穿过钝化层10。互连结构14安置于第一开口内。举例来说，互连14可由钝化层10环绕。
在一些实施例中，互连结构14安置于第一开口和第二开口的至少部分内。如说明由方框A圈出的图1A的半导体封装装置1的部分的放大视图的图1B中所展示，在一些实施例中，第一开口的侧壁103的倾斜部以不同于第二开口的侧壁104的倾斜部的倾斜角的角度倾斜。在一些实施例中，钝化层10的底表面102与第二开口的侧壁104之间的角度θ1介于约160度到约180度、约165度到约178度或约173度到约178度的范围内。互连结构14包含第一金属层14a、障壁层14b和第二金属层14c。
第一金属层14a在第一开口内且由钝化层10环绕。第一金属层14a具有基本上平行于钝化层10的顶表面101的第一表面14a1、邻近于第一表面14a1的第二表面14a2和邻近于第一表面14a1的第三表面14a3。在一些实施例中，由第一表面14a1和第二表面14a2界定的角度θ2大于约90度且小于约180度。举例来说，由第一表面14a1和第二表面14a2界定的角度θ2可以是钝角角度。第一表面14a1、第二表面14a2和第三表面14a3界定面朝电接触件15的凹槽。在一些实施例中，第一金属层14a包含金(Au)、银(Ag)、镍(Ni)、铜(Cu)、其它金属或合金，或其中的两个或多于两个的组合。
障壁层14b安置于第一金属层14a上且由钝化层10环绕。在一些实施例中，障壁层14b与第一金属层14a共形。因此，障壁层14b被塑形为面朝第一金属层14a和/或容纳第一金属层14a的至少部分的凹槽。在一些实施例中，障壁层14b包含钛(Ti)、Ni、钯(Pd)、其它金属或合金，或其中的两个或多于两个的组合。
第二金属层14c安置于障壁层14b上且由钝化层10环绕。在一些实施例中，第二金属层14c与障壁层14b共形。因此，第二金属层14c被塑形为面朝障壁层14b和/或容纳障壁层14b的至少部分的凹槽。在一些实施例中，第二金属层14c包含Cu、其它金属或合金，或其组合。
电接触件15的至少部分在钝化层10的第二开口内。如图1B中所展示，电接触件15的至少部分安置于由第一金属层14a的第一表面14a1、第二表面14a2和第三表面14a3界定的凹槽内。电接触件15电接触第一金属层14a的第一表面14a1、第二表面14a2和第三表面14a3中的一或多个。在一些实施例中，电接触件15是可控塌陷芯片连接(C4)凸块、球栅阵列(BGA)或焊盘网格阵列(LGA)。
如上文所提到，SMD类型焊垫和NSMD类型焊垫具有阻碍其正确地与焊球接合的问题(例如，缺失焊球、错误焊接或开裂)。根据图1A和1B中所展示的实施例，焊垫(例如，包含第一金属层14a、障壁层14b和/或第二金属层14c的焊垫)形成为用于容纳焊球(例如，电接触件15)的夹钳结构。因此，上述问题可通过增加焊球与焊垫之间的接合强度，继而增强半导体封装装置1的电气性能来解决。
此外，由于第一开口从钝化层10的顶表面101朝向钝化层10的底表面102逐渐变窄，因此布置可防止互连结构14剥落。此外，由于第二开口从钝化层10的底表面102朝向钝化层10的顶表面101逐渐变窄，因此布置可防止电接触件15在回流过程期间接触钝化层10，且防止电接触件15中空隙的形成。
晶种层10s安置于钝化层10的顶表面101和第二金属层14c上。晶种层10s在第一开口内延伸且接触第一开口的侧壁103的部分。因此，晶种层10s具有小于约90度、小于约100度或小于约120度的转向角θ3。具有转向角的晶种层10s的部分也被称作铆接结构。晶种层10s的转向角可增加互连结构14与晶种层10s和/或导电层10r之间的接合强度。
导电层10r安置于晶种层10s上。举例来说，导电层10r安置于钝化层10的顶表面101上方且在第一开口内延伸。在一些实施例中，导电层10r包含Cu、Ag、Au、铂(Pt)、铝(Al)、焊料合金，或其中的两个或多于两个的组合。
介电层11安置于钝化层10的顶表面101的至少部分上，且覆盖钝化层10的顶表面101的至少部分、晶种层10s和导电层10r的部分。介电层11界定用以露出导电层10r的部分的开口。在一些实施例中，介电层和导电层的数目可根据若干不同实施例而变化。在一些实施例中，介电层11可包含有机材料、防焊剂、聚酰亚胺(PI)、环氧树脂、味之素堆积膜(ABF)、模制原料，或其中的两个或多于两个的组合。
晶种层11s安置于介电层11上，且在介电层11的开口内延伸以电接触导电层10r的露出部分。导电层11r安置于晶种层11s上。举例来说，导电层11r安置于介电层11上方且在介电层11的开口内延伸。在一些实施例中，导电层11r包含Cu、Ag、Au、Pt、Al、焊料合金，或其中的两个或多于两个的组合。
晶种层10s、导电层10r、晶种层11s和导电层11r可统称为重新分布层(RDL)。替代地，晶种层10s、导电层10r、晶种层11s和导电层11r的组合的任何部分可被称为RDL。
返回参看图1A，电子组件12安置于介电层11上且通过导电接触件16电连接到导电层11r。电子组件12可以是在其中包含半导体衬底、一或多个集成电路装置和一或多个上覆互连结构的芯片或裸片。集成电路装置可包含例如晶体管等有源装置和/或例如电阻器、电容器、电感器等无源装置，或其中的两个或多于两个的组合。
图1C说明根据本公开的一些实施例的如图1A中所展示的导电接触件16的放大视图。导电接触件16包含微凸块16a(例如，Cu)、焊接连接层16b、表面垫16c(例如，Au、Cu或其组合)和焊层16d。
图1D说明根据本公开的一些实施例的如图1A中所展示的导电接触件16'的放大视图。导电接触件16'类似于图1C中所展示的导电接触件16，例外为导电接触件16'不包含焊接连接层16b和表面垫16c。微凸块16a(例如，Cu)通过焊层16d连接到导电层11r。
返回参看图1A，底层填充物12u可安置于介电层11上以覆盖电子组件12的有源表面(也被称作有源侧)和导电接触件16。在一些实施例中，底层填充物12u包含环氧树脂、模制原料(例如，环氧模制原料或其它模制原料)、聚酰亚胺、酚类化合物或材料、包含分散在其中的硅酮的材料，或其中的两个或多于两个的组合。在一些实施例中，取决于不同实施例的规范，底层填充物12u可以是毛细管底层填充物(CUF)、经模制底层填充物(MUF)或分配凝胶。
封装体13安置于介电层11上且覆盖电子组件12和底层填充物12u。在一些实施例中，封装体13覆盖电子组件12的后表面(也被称作后侧)。替代地，如图1A中所展示，封装体13露出电子组件12的后表面。在一些实施例中，封装体13包含例如一或多个有机材料(例如，模制原料、双马来酰亚胺三嗪(BT)、PI、聚苯并恶唑(PBO)、阻焊剂、ABF、聚丙烯(PP)、基于环氧树脂的材料，或其中的两个或多于两个的组合)、无机材料(例如，硅、玻璃、陶瓷或石英，或其中的两个或多于两个的组合)、液膜材料、干膜材料，或其中的两个或多于两个的组合。
图2A说明根据本公开的一些实施例的半导体封装装置2A。半导体封装装置2A类似于图1A中所展示的半导体封装装置1，例外为半导体封装装置2A包含多个介电层11a、11b和多个导电层11r。在一些实施例中，取决于各种实施例的设计规范，半导体封装装置可包含任何数目个介电层和导电层。在一些实施例中，可除去介电层，如图2B的半导体封装装置2B中所展示。在半导体封装装置2B中，晶种层10s和导电层10r可统称为RDL。
图3A、3B、3C、3D、3E、3F、3G、3H和3I是根据本公开的一些实施例的在各个阶段制造的半导体结构的横截面视图。已简化各个图式，以便更好地理解本公开的方面。
参看图3A，提供金属板39。在一些实施例中，金属板39由例如Cu或其它金属或合金形成。在一些实施例中，金属板39的厚度是约100微米(μm)到200μm，约50μm到约400μm，或约10μm到约1000μm。
光刻胶膜37(或掩模)附接到金属板39的顶表面391。一或多个开口37b通过例如光刻技术形成于光刻胶膜37上，以露出金属板39的顶表面391的部分。在一些实施例中，空隙37a形成于光刻胶膜37与金属板39的顶表面391之间。
参看图3B，金属层39a形成于金属板39的顶表面391的露出部分上且延伸到空隙37a中。在一些实施例中，金属层39a通过例如电镀或其它合适的过程形成。
参看图3C，随着电镀时间增加，光刻胶膜37的边缘将归因于占据空隙37a的金属层39a的体积增大而被金属层39a抬高。因此，金属凸块39b形成于金属板39的顶表面391的露出部分上，如图3C中所展示。
参看图3D，光刻胶膜37被移除且钝化层30形成于金属板39的顶表面391上和金属凸块39b上。一或多个开口形成为穿过钝化层30且露出金属凸块39b。开口从钝化层30的顶表面301到钝化层30中逐渐变窄。
互连结构34接着形成于开口内和金属凸块39b上。在一些实施例中，互连结构34可通过依序在开口内形成第一金属层34a、障壁层34b和第二金属层34c而形成。在一些实施例中，第一金属层34a、障壁层34b和/或第二金属层34c可通过例如电镀、无电镀覆、溅镀、胶合印刷，或其它合适的工艺形成。
参看图3E，光刻胶层38a放置在钝化层30的顶表面301上。光刻胶层38a界定一或多个开口，以露出钝化层30的顶表面301的部分和第二金属层34c。晶种层30s形成于钝化层30的顶表面301的露出部分和第二金属层34c上。晶种层30s在开口内延伸且接触开口的侧壁303的部分。在一些实施例中，晶种层30s可通过例如溅镀金属(例如，Ti或Cu)形成。导电层30r接着通过例如电镀金属(例如，Cu)形成于晶种层30s上。
参看图3F，光刻胶层38a被移除且介电层31形成于导电层30r上。一或多个开口形成为穿过介电层31以露出导电层30r的部分。在一些实施例中，开口可通过例如铣切、蚀刻、钻孔或其它合适的过程形成。
光刻胶层38b放置在介电层31上。光刻胶层38b界定一或多个开口，以露出介电层31的部分和导电层30r的部分。晶种层31s形成于介电层31的露出部分上且在介电层31的开口内延伸，以接触导电层30r的露出部分。在一些实施例中，晶种层31s可通过例如溅镀金属(例如，Ti或Cu)形成。导电层31r通过例如电镀金属(例如，Cu)形成于晶种层31s上。在一些实施例中，光刻胶层38b被移除且另一光刻胶层38c形成，如图3G中所展示。在一些替代实施例中，额外光刻胶材料沉积于光刻胶层38b上，以形成光刻胶层38c，如图3G中所展示。
参看图3G，光刻胶层38c放置在介电层31上。光刻胶层38c界定一或多个开口，以露出导电层31r的部分。导电接触件36形成于每一开口内，以电接触导电层31r的露出部分。在一些实施例中，导电接触件36与图1C中所展示的导电接触件16基本上相同或类似。替代地，导电接触件36与图1D中所展示的导电接触件16'基本上相同或类似。在一些实施例中，导电接触件36通过例如电镀金属(例如，Cu、Ni、Au，或其中的两个或多于两个的组合)形成。
参看图3H，光刻胶层38c被移除且电子组件32放置在导电接触件36上以供电连接到导电接触件36。
底层填充物32u可安置于或形成于介电层31上以覆盖电子组件32的有源表面和电接触件36。在一些实施例中，底层填充物32u包含环氧树脂、模制原料(例如，环氧模制原料或其它模制原料)、聚酰亚胺、酚类化合物或材料、包含分散在其中的硅酮的材料，或其中的两个或多于两个的组合。在一些实施例中，取决于不同实施例的各种规范，底层填充物32u可以是CUF、MUF或分配凝胶。
封装体33形成于介电层31上且覆盖电子组件32的表面区域的至少部分和底层填充物32u。在一些实施例中，封装体32包含例如有机材料(例如，模制原料、BT、PI、PBO、阻焊剂、ABF、PP、基于环氧树脂的材料，或其中的两个或多于两个的组合)、无机材料(例如，硅、玻璃、陶瓷、石英，或其中的两个或多于两个的组合)、液膜材料、干膜材料，或其中的两个或多于两个的组合。封装体32可通过例如传递模制或压缩模制等模制技术形成。
参看图3I，金属层39被移除，以形成一或多个凹槽，以露出第一金属层34a。在一些实施例中，金属层39可通过例如蚀刻、等离子、剥离或剪切而被移除。
电接触件35(例如，凸点或焊球)形成于第一金属层34a上，以形成半导体封装装置3。在一些实施例中，电接触件35是C4凸点、BGA或LGA。在一些实施例中，电接触件35可通过例如电镀、无电镀敷、溅镀、焊膏印刷、凸起或接合过程形成。在一些实施例中，图3I中所展示的半导体封装装置3与图1A中所展示的半导体封装装置1基本上相同或类似。
图4A和4B说明根据本公开的一些实施例的不同类型的半导体封装裝置。
如图4A中所展示，多个芯片40和/或裸片放置在正方形的载体41上。在一些实施例中，载体41可包含有机材料(例如，模制原料、BT、PI、PBO、阻焊剂、ABF、PP、基于环氧树脂的材料，或其中的两个或多于两个的组合)或无机材料(例如，硅、玻璃、陶瓷、石英，或其中的两个或多于两个的组合)。
如图4B中所展示，多个芯片40和/或裸片放置在圆形的载体42上。在一些实施例中，载体42可包含有机材料(例如，模制原料、BT、PI、PBO、阻焊剂、ABF、PP、基于环氧树脂的材料，或其中的两个或多于两个的组合)或无机材料(例如，硅、玻璃、陶瓷、石英，或其中的两个或多于两个的组合)。
如本文中所使用，术语“大约”、“基本上”、“基本的”和“约”用以描述和说明小的变化。当与事件或情况结合使用时，术语可指事件或情况精确发生的例子以及事件或情况极近似地发生的例子。举例来说，当结合数值使用时，术语可指小于或等于数值的±10％的变化范围，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％，或小于或等于±0.05％。举例来说，如果值之间的差小于或等于值的平均值的±10％(例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％、或小于或等于±0.05％)，那么可认为两个数值“基本上”或“大体上”相同。举例来说，“基本上”平行可指相对于0°的小于或等于±10°(例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°,或小于或等于±0.05°)的角变化范围。举例来说，“基本上”垂直可指相对于90°的小于或等于±10°(例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°、或小于或等于±0.05°)的角度变化范围。
如果两个表面之间的位移不大于5μm、不大于2μm、不大于1μm或不大于0.5μm，那么可认为两个表面是共面的或基本上共面的。
如本文中所使用，术语“导电(conductive/electrically conductive)”和“导电性”是指传输电流的能力。导电材料通常指示对电流流动展现极少或零对抗的材料。导电性的一个量度为西门子/米(S/m)。通常，导电材料是导电率大于大约104S/m，例如至少105S/m或至少106S/m的一种材料。材料的导电性有时可随温度而变化。除非另外规定，否则在室温下测量材料的导电性。
如本文中所使用，除非上下文另外明确规定，否则单数术语“一”和“所述”可包含复数指示物。在一些实施例的描述中，一个组件提供于另一组件“上”或“上方”可涵盖前一组件直接在后一组件上(例如，与后一组件物理接触)的情况，以及一或多个中间组件位于前一组件与后一组件之间的情况。
尽管已参考本公开的特定实施例描述和说明本公开，但这些描述和说明并不限制本公开。所属领域的技术人员可明确地理解，在不脱离如由所附权利要求书界定的本公开的真实精神和范围的情况下，可进行各种改变，且可在实施例内取代等效组件。图式可能未必按比例绘制。归因于制造过程中的变化和此些原因，本公开中的艺术再现与实际设备之间可存在区别。可存在并未具体说明的本公开的其它实施例。应将本说明书和图式视为说明性的而非限定性的。可进行修改，以使特定情形、材料、物质组成、方法或过程适宜于本公开的目标、精神和范围。所有此类修改既定在此所附权利要求书的范围内。虽然已参考按特定次序执行的特定操作描述本文中所公开的方法，但应理解，可在不脱离本公开的教示的情况下组合、细分或重新排序这些操作以形成等效方法。因此，除非本文中特别指示，否则操作的次序和分组并非本公开的限制。

Claims (27)

1.一种导电结构，其包括：
钝化层；
导电元件，其由所述钝化层环绕，所述导电元件具有第一表面和邻近于所述第一表面的第二表面，其中所述第一表面与所述第二表面之间的角度大于约90度；以及
导电接触件，其邻近于所述导电元件，且与所述导电元件的所述第一表面和所述第二表面电连接。
2.根据权利要求1所述的导电结构，其中所述第一表面与所述第二表面之间的所述角度小于约180度。
3.根据权利要求1所述的导电结构，其中
所述钝化层具有第一表面和与所述第一表面相对的第二表面，所述第二表面邻近于所述导电接触件；
所述钝化层界定从所述钝化层的所述第一表面朝向所述钝化层的所述第二表面逐渐变窄的第一开口，和从所述钝化层的所述第二表面朝向所述钝化层的所述第一表面逐渐变窄的第二开口；且
所述第一开口和所述第二开口经连接以穿过所述钝化层。
4.根据权利要求3所述的导电结构，其中所述导电元件的至少部分在所述第一开口内，且所述导电接触件的至少部分在所述第二开口内。
5.根据权利要求3所述的导电结构，其中所述第一开口的侧壁的倾斜角不同于所述第二开口的侧壁的倾斜角。
6.根据权利要求3所述的导电结构，其中所述钝化层的所述第二表面与所述第二开口的侧壁之间的角度介于约173度到约178度的范围内。
7.根据权利要求3所述的导电结构，其进一步包括在所述钝化层的所述第一表面上且沿着所述第一开口的侧壁的至少部分延伸的经图案化导电层。
8.根据权利要求1所述的导电结构，其中所述导电元件包括第一金属层、所述第一金属层上的障壁层和所述障壁层上的第二金属层。
9.根据权利要求1所述的导电结构，其中
所述导电元件包括邻近于所述第一表面的第三表面；且
所述导电元件的所述第一表面、所述第二表面和所述第三表面界定面向所述导电接触件的凹槽。
10.一种导电结构，其包括：
钝化层，其具有第一表面和与所述第一表面相对的第二表面，所述钝化层界定从所述钝化层的所述第一表面朝向所述钝化层的所述第二表面逐渐变窄的第一开口；以及
导电元件，其在所述第一开口内，其中所述导电元件界定朝向所述钝化层的所述第二表面的凹槽。
11.根据权利要求10所述的导电结构，其进一步包括从所述钝化层的所述第二表面朝向所述钝化层的所述第一表面逐渐变窄的第二开口，其中所述第二开口和所述第一开口经连接以穿过所述钝化层。
12.根据权利要求11所述的导电结构，其中所述第一开口的侧壁的倾斜角不同于所述第二开口的侧壁的倾斜角。
13.根据权利要求11所述的导电结构，其中所述钝化层的所述第二表面与所述第二开口的侧壁之间的角度介于约173度到约178度的范围内。
14.根据权利要求10所述的导电结构，其中所述导电元件包括第一金属层、所述第一金属层上的障壁层和所述障壁层上的第二金属层。
15.根据权利要求10所述的导电结构，其进一步包括导电接触件，其中所述导电接触件的至少部分在所述导电元件的所述凹槽内。
16.根据权利要求10所述的导电结构，其中
所述导电元件具有大体上平行于所述钝化层的所述第一表面的第一表面，邻近于所述第一表面的第二表面和邻近于所述第一表面的第三表面，且
所述导电元件的所述第一表面、所述第二表面和所述第三表面界定所述凹槽。
17.根据权利要求16所述的导电结构，其中所述导电元件的所述第一表面与所述导电元件的所述第二表面之间的角度大于约90度且小于约180度。
18.根据权利要求10所述的导电结构，其进一步包括所述钝化层的所述第一表面上的经图案化导电层，其中所述经图案化导电层具有在所述第一开口的侧壁上的铆接部分。
19.一种半导体封装装置，其包括：
钝化层，其具有第一表面和与所述第一表面相对的第二表面；
导电元件，其在所述钝化层内，其中所述导电元件界定面向所述钝化层的所述第二表面的凹槽；
重新分布层RDL，其在所述钝化层上且与所述导电元件电连接；以及
电子组件，其安置于所述RDL上且与所述RDL电连接。
20.根据权利要求19所述的半导体封装装置，其进一步包括导电接触件，其中所述导电接触件的至少部分在所述导电元件的所述凹槽内。
21.根据权利要求19所述的半导体封装装置，其中所述钝化层界定从所述第一表面朝向所述第二表面逐渐变窄的第一开口，和从所述第二表面朝向所述第一表面逐渐变窄的第二开口，其中所述第二开口和所述第一开口经连接以穿过所述钝化层。
22.根据权利要求21所述的半导体封装装置，其中所述导电元件的至少部分在所述第一开口内。
23.根据权利要求21所述的半导体封装装置，其中所述第一开口的侧壁的倾斜角不同于所述第二开口的侧壁的倾斜角。
24.根据权利要求21所述的半导体封装装置，其中所述RDL具有在所述第一开口的侧壁上的铆接部分。
25.根据权利要求19所述的半导体封装装置，其中所述导电元件包括第一金属层、所述第一金属层上的障壁层和所述障壁层上的第二金属层。
26.根据权利要求19所述的半导体封装装置，其中
所述导电元件具有大体上平行于所述钝化层的所述第一表面的第一表面，邻近于所述第一表面的第二表面和邻近于所述第一表面的第三表面，且
所述导电元件的所述第一表面、所述第二表面和所述第三表面界定所述凹槽。
27.根据权利要求26所述的半导体封装装置，其中所述导电元件的所述第一表面与所述导电元件的所述第二表面之间的角度大于约90度且小于约180度。
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