CN108461406A - 衬底结构、半导体封装结构及其制造方法 - Google Patents
衬底结构、半导体封装结构及其制造方法 Download PDFInfo
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- CN108461406A CN108461406A CN201810149175.7A CN201810149175A CN108461406A CN 108461406 A CN108461406 A CN 108461406A CN 201810149175 A CN201810149175 A CN 201810149175A CN 108461406 A CN108461406 A CN 108461406A
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- 239000004065 semiconductor Substances 0.000 title claims description 99
- 238000004519 manufacturing process Methods 0.000 title claims description 35
- 229910052751 metal Inorganic materials 0.000 claims abstract description 194
- 239000002184 metal Substances 0.000 claims abstract description 194
- 239000010410 layer Substances 0.000 claims description 521
- 229910000765 intermetallic Inorganic materials 0.000 claims description 63
- 238000000034 method Methods 0.000 claims description 48
- 239000000463 material Substances 0.000 claims description 44
- 239000000758 substrate Substances 0.000 claims description 43
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 29
- 239000010949 copper Substances 0.000 claims description 29
- 229910052802 copper Inorganic materials 0.000 claims description 25
- 239000011241 protective layer Substances 0.000 claims description 22
- 238000004806 packaging method and process Methods 0.000 claims description 14
- 230000005611 electricity Effects 0.000 claims description 13
- 230000003746 surface roughness Effects 0.000 claims description 11
- 229910052718 tin Inorganic materials 0.000 claims description 11
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 229910000679 solder Inorganic materials 0.000 description 42
- 239000011135 tin Substances 0.000 description 24
- 239000010931 gold Substances 0.000 description 18
- 230000008569 process Effects 0.000 description 16
- 229910052737 gold Inorganic materials 0.000 description 15
- 238000000465 moulding Methods 0.000 description 15
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 12
- 238000005476 soldering Methods 0.000 description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 10
- 239000011888 foil Substances 0.000 description 10
- 239000011889 copper foil Substances 0.000 description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 8
- 230000009471 action Effects 0.000 description 7
- 150000001875 compounds Chemical class 0.000 description 7
- 229910052763 palladium Inorganic materials 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 239000004952 Polyamide Substances 0.000 description 6
- 239000004642 Polyimide Substances 0.000 description 6
- 229910052759 nickel Inorganic materials 0.000 description 6
- 238000002161 passivation Methods 0.000 description 6
- 229920002647 polyamide Polymers 0.000 description 6
- 229920001721 polyimide Polymers 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 229920002577 polybenzoxazole Polymers 0.000 description 5
- 239000000945 filler Substances 0.000 description 4
- 230000003993 interaction Effects 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 238000003825 pressing Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005336 cracking Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 238000003384 imaging method Methods 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 229910016570 AlCu Inorganic materials 0.000 description 2
- 229910018471 Cu6Sn5 Inorganic materials 0.000 description 2
- 229910005907 NiSn4 Inorganic materials 0.000 description 2
- 229910007637 SnAg Inorganic materials 0.000 description 2
- 229910001069 Ti alloy Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910010293 ceramic material Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 150000000183 1,3-benzoxazoles Chemical class 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000000740 bleeding effect Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- IUYOGGFTLHZHEG-UHFFFAOYSA-N copper titanium Chemical compound [Ti].[Cu] IUYOGGFTLHZHEG-UHFFFAOYSA-N 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- -1 for example Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
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- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
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- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
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Abstract
一种衬底结构包含载体、第一金属层、电路层和电介质层。所述载体具有第一表面和第二表面。所述第一金属层安置于所述载体的所述第一表面上。所述电路层安置于所述第一金属层上。所述电介质层覆盖所述电路层,且界定多个开口,以暴露所述电路层的若干部分以及所述第一金属层的若干部分。
Description
相关申请案的交叉参考
本申请案主张2017年2月22日申请的第62/462,248号美国临时专利申请案的权益和优先权,所述申请案以全文引用的方式并入本文中。
技术领域
本发明涉及一种衬底结构、一种半导体封装结构和一种制造方法,且涉及一种嵌入迹线衬底(embedded trace substrate,ETS)结构、一种包含ETS结构的半导体封装结构和一种制造半导体封装结构的方法。
背景技术
一些半导体装置封装包含ETS,例如其中嵌入迹线的衬底,其中所述迹线的一部分从所述衬底暴露。在一些此类封装中,可能会使用迹线(trace)作为焊料球(或焊料凸块)焊盘垫(solder ball(or solder bump)land pads)。然而,在一些情况下,薄迹线(例如具有小于约20微米(μm)的厚度)在此类封装中的使用可导致焊料凸块焊盘垫在模制工艺(molding process)期间或之后变形。这可能导致使封装的大小最小化较困难,所述最小化在一些情况下是需要的。
发明内容
在一些实施例中,根据一方面,一种衬底结构包含载体、第一金属层、电路层和电介质层(dielectric layer)。所述载体具有第一表面和第二表面。第一金属层安置于所述载体的第一表面上。所述电路层安置于所述第一金属层上。所述电介质层覆盖所述电路层,且界定多个开口,以暴露所述电路层的若干部分以及所述第一金属层的若干部分。
在一些实施例中,根据另一方面,一种半导体封装结构包含电路层、电介质层、半导体裸片和连接元件。所述电介质层覆盖所述电路层的第一表面,且具有第一表面和第二表面。所述电介质层界定开口以暴露所述电路层的一部分,且所述开口延伸穿过(extendsthrough)所述电介质层。所述半导体裸片通过倒装芯片接合(flip chip bonding)附接到所述电路层。所述连接元件电连接所述半导体裸片与所述电路层。所述连接元件的至少一部分安置于所述电介质层的开口中,且从所述电介质层的所述第二表面暴露。
在一些实施例中,根据另一方面,一种半导体封装结构包含电路层、电介质层、半导体裸片和多个连接元件。所述电介质层覆盖所述电路层的第一表面,且界定多个开口以暴露所述电路层的若干部分。所述半导体裸片通过倒装芯片接合附接到所述电路层。所述连接元件电连接半导体裸片与所述电路层的由开口暴露的部分。所述连接元件中的每一者的至少一部分分别安置于所述电介质层的开口中,且从所述电介质层的表面暴露。所述连接元件的暴露部分的形状分别由所述电介质层的开口界定。
在一些实施例中,根据另一方面,一种用于制造半导体封装结构的方法包含:(a)提供衬底结构,其中所述衬底结构包括载体、金属层、电路层和电介质层,其中所述载体具有第一表面和第二表面,所述金属层安置于所述载体的第一表面上,所述电路层安置于所述金属层上,且所述电介质层覆盖所述电路层且界定多个开口以暴露所述电路层的若干部分和所述金属层的若干部分;以及(b)通过经由多个连接元件的倒装芯片接合将半导体裸片附接到所述衬底结构,其中所述连接元件分别安置于所述电介质层的开口中的所述电路层的暴露部分和所述金属层的暴露部分上。
附图说明
当结合附图阅读时,从以下具体实施方式容易地理解本发明的一些实施例的特性。应注意,各种结构可能未按比例绘制,且各种结构的尺寸可出于论述的清楚起见而任意增大或减小。
图1说明根据本发明的一方面的衬底结构的一些实施例的截面图。
图2说明图1的衬底结构的一部分的一些实施例的立体图。
图3说明图1的衬底结构的一部分的一些实施例的俯视图。
图4说明根据本发明的一方面的半导体封装结构的一些实施例的截面图。
图5说明图4的半导体封装结构的区域“A”的放大图。
图6说明图4的半导体封装结构的区域“B”的放大图。
图7说明根据本发明的一方面的用于制造半导体封装结构的方法的一些实施例的一或多个阶段。
图8说明根据本发明的一方面的用于制造半导体封装结构的方法的一些实施例的一或多个阶段。
图9说明根据本发明的一方面的用于制造半导体封装结构的方法的一些实施例的一或多个阶段。
图10说明根据本发明的一方面的用于制造半导体封装结构的方法的一些实施例的一或多个阶段。
图11说明根据本发明的一方面的用于制造半导体封装结构的方法的一些实施例的一或多个阶段。
图12说明根据本发明的一方面的用于制造半导体封装结构的方法的一些实施例的一或多个阶段。
图13说明根据本发明的一方面的用于制造半导体封装结构的方法的一些实施例的一或多个阶段。
图14说明根据本发明的一方面的用于制造半导体封装结构的方法的一些实施例的一或多个阶段。
图15说明根据本发明的一方面的用于制造半导体封装结构的方法的一些实施例的一或多个阶段。
图16说明图15中的区域“C”的放大图。
图17说明根据本发明的一方面的用于制造半导体封装结构的方法的一些实施例的一或多个阶段。
图18说明根据本发明的一方面的用于制造半导体封装结构的方法的一些实施例的一或多个阶段。
图19说明根据本发明的一方面的用于制造半导体封装结构的方法的一些实施例的一或多个阶段。
图20说明根据本发明的一方面的用于制造半导体封装结构的方法的一些实施例的一或多个阶段。
图21说明根据本发明的一方面的用于制造半导体封装结构的方法的一些实施例的一或多个阶段。
具体实施方式
贯穿图式和详细描述使用共同参考标号来指示相同或相似组件。根据以下结合附图作出的详细描述将容易地理解本发明的实施例。
以下揭示提供用于实施所提供标的物的不同特征的许多不同实施例或实例。下文描述组件和布置的具体实例来阐释本发明的某些方面。当然,这些只是实例且无意为限制性的。举例来说,在以下描述中,对第一特征在第二特征上面或第二特征上的形成的提及可包含第一特征和第二特征直接接触地形成或安置的实施例,并且还可包含额外特征可在第一特征与第二特征之间形成或安置以使得第一特征和第二特征可不直接接触的实施例。另外,本发明可以在各种实例中重复参考标号和/或字母。此重复是出于简化和清楚的目的,且本身并不指示所论述的各种实施方案和/或配置之间的关系。
本发明的至少一些实施例揭示一种衬底结构,其包含安置于第一金属层上的电路层,以及界定多个开口以暴露所述电路层的若干部分和所述第一金属层的若干部分的电介质层。本发明的至少一些实施例进一步揭示一种半导体封装结构,其包含电连接半导体裸片和电路层的多个连接元件,其中所述连接元件的至少一部分安置于电介质层的开口中,且从所述电介质层的表面暴露。本发明的至少一些实施例进一步揭示用于制造所述半导体封装结构的技术。
在比较性ETS结构中,单个电路层(包含至少一个迹线)嵌入于单个电介质层中。所述电路层的上表面的若干部分从电介质层的上表面暴露,且可充当在其上附接半导体裸片的裸片垫(die pad)。应注意,裸片垫中的每一者的宽度可大于迹线的宽度。所述电介质层界定多个开口,以使所述电路层的下表面的若干部分从电介质层的下表面暴露。电路层的暴露部分可充当在其上附接焊料球(或焊接凸块)的焊料球(或焊料凸块)焊盘垫。应注意,焊料凸块焊盘垫中的每一者的宽度可大于迹线的宽度,且所述焊料凸块焊盘垫中的每一者的上表面还从电介质层的上表面暴露。
在用于制造包含此ETS结构的半导体封装结构的过程中,所述ETS结构附接到载体,使得电介质层的下表面接触载体,且空的空间(empty space)由电介质层的开口、焊料凸块焊盘垫和载体所界定。接着,半导体裸片附接到裸片垫。所述半导体裸片在半导体裸片的作用表面(active surface)上包含多个导电柱。多个连接元件(例如焊接凸块)用以连接导电柱与裸片垫。接着,施加模制化合物(molding compound)来覆盖半导体裸片、导电柱、连接元件和载体。接着,去除所述载体,以便获得半导体封装结构。接着,使用多个焊球(或焊接凸块)以将焊料凸块焊盘垫连接到印刷电路板(PCB)。
在模制操作(molding operation)之前,上文所提到的空的空间已被界定。也就是说,焊料凸块焊盘垫的上表面和下表面是空的。因此,在模制操作期间,模制化合物可流动以按压焊料凸块焊盘垫的上表面。如果焊料凸块焊盘垫太薄(例如具有小于约20μm的厚度),那么其可容易地变形。另外,在模制操作之后,使模制化合物固化。所述模制化合物的固化处理可使焊料凸块焊盘垫进一步变形。为了增加电路层的结构刚性,以承受模制流在模制操作期间的压力以及固化处理期间的弯曲力,可将电路层设计成具有大于20μm的厚度。因此,电路层的线宽和线距(line width and line space,L/S)可等于或大于12μm/12μm。这可使得难以最小化半导体封装结构的大小。
另外,电路层的上表面可从电介质层的上表面暴露,因此,连接元件可渗移和接触电路层的邻近裸片垫或迹线,这可导致桥接(bridge)和短路(short circuit)。为了避免此情况,电路层的邻近裸片垫或迹线可安置成彼此远离。这可导致电路层的L/S较大。为了避免此桥接和短路,保护层(例如阻焊层)可形成或安置于电介质层的上表面上,以覆盖所述电路层的上表面。所述保护层界定多个开口,以暴露电路层的裸片垫。应注意,从俯视图来看的开口的区域可大于从俯视图来看的裸片垫的区域,使得裸片垫大部分(例如完全)暴露。然而,由于保护层的制造可以大分辨率(resolution)进行,且制造容差(manufacturingtolerance)可较大,保护层的开口的区域可比电路层的裸片垫的区域大得多。举例来说,保护层的开口的大小可为约80μm*约110μm。因此,电路层的迹线可远离电路层的裸片垫隔开(例如,以确保其被保护层覆盖,且不被保护层的开口暴露)。这可导致电路层的大L/S。
为了至少解决这些问题,本发明的一些实施例是针对半导体封装结构和制造半导体封装结构的方法,其包含延伸的金属间化合物层(extended intermetallic compound(IMC)layer)。此外,使用ETS以提供焊盘垫(例如用于焊接凸块、通孔(via)或其它电气或金属连接件的连接点),箔,例如包含金属(例如铜(Cu)的金属箔可在制造工艺期间安置于衬底中或衬底上(例如所述衬底的薄Cu层上),所述箔的一部分暴露。焊盘垫或裸片垫(其可包含与所述箔中的金属相同或不同的金属)可安置于所述箔上,从而使所述箔的邻近于焊盘垫(或裸片垫)的部分暴露。在制造工艺中,焊料可位于焊盘垫(或裸片垫)上以及所述箔的邻近部分上。焊料可润湿焊盘垫(或裸片垫)和箔两者。这可导致在焊盘垫(或裸片垫)上以及箔上形成IMC层,也就是说,IMC层可延伸到所述箔。延伸的IMC可有助于在结构上和/或机械上加强焊盘垫(或裸片垫)与焊料之间的连接,且可允许焊接点处的较好电连接(例如可降低焊接点处的现场电阻(on-site electrical resistance))。
本发明至少解决上述问题,且提供一种改进的衬底结构和半导体封装结构,以及用于制造所述半导体封装结构的改进的技术。在半导体封装结构的制造工艺中,电路层形成于载体的第一金属层上,使得焊料凸块焊盘垫在模制操作期间由第一金属层支撑,且将不变形。
图1说明根据本发明的一方面的衬底结构1的一些实施例的截面图。衬底结构1可为ETS,其包含载体10、第一金属层16、电路层18、电介质层20和第二金属层22。载体10可包含(例如)金属材料、陶瓷材料、玻璃材料、电介质材料或半导体晶片。载体10的形状可为(例如)大体上矩形或正方形。或者,载体10的形状可为(例如)大体上圆形或椭圆形。载体10具有第一表面101和与第一表面101相对的第二表面102。
第一金属层16安置于载体10的第一表面101上。在图1中说明的实施例中,第一金属层16可包含基底金属层12和导电金属层14。基底金属层12安置于载体10的第一表面101上,且导电金属层14安置于基底金属层12上。在一些实施例中,基底金属层12可为按压在载体10上或粘附到载体10的铜箔,且导电金属层14也可为粘附到基底金属层12的铜箔。在一些实施例中,基底金属层12的厚度可不同于导电金属层14的厚度。基底金属层12的厚度可在导电金属层14的厚度的约四到约六倍大的范围内。举例来说,基底金属层12的厚度可为约18μm,且导电金属层14的厚度可为约3μm。
电路层18安置于第一金属层16上。在一些实施例中,电路层18安置于第一金属层16的导电金属层14上。在一些实施例中,电路层18可为经图案化的电路层,且可通过电镀形成。电路层18可包含至少一个迹线19、至少一个裸片垫191和至少一个焊料凸块焊盘垫192。电路层18具有第一表面181和与第一表面181相对的第二表面182。电路层18的第二表面182直接接触第一金属层16的导电金属层14。在一些实施例中,电路层18的厚度在约10μm到约15μm的范围内,且电路层18的线宽和线距(L/S)在约5μm/约5μm到约12μm/约12μm的范围内。
电介质层20覆盖电路层18以及第一金属层16的导电金属层14。电介质层20可包含以下各项或由以下各项形成:光致抗蚀剂层;经固化感光材料;经固化光可成像电介质(PID)材料,例如聚酰胺(PA)、聚酰亚胺(PI)、环氧树脂或聚苯并恶唑(PBO),或其两个或多个的组合。电介质层20具有第一表面201以及与第一表面201相对的第二表面202。电介质层20的厚度大于电路层18的厚度(例如大约1.3或更多、约1.5或更多,或约1.7或更多的比率),使得电介质层20的第二表面202与电路层18的第二表面182大体上共面,且电介质层20的第一表面201高于电路层18的第一表面181(并且例如覆盖其至少一部分)。电介质层20界定多个开口(包含例如多个第一开口203a和多个第二开口203b),以暴露电路层18的若干部分(例如裸片垫191)以及第一金属层16的导电金属层14的若干部分。在一些实施例中,第一开口203a的横截面的形状不同于第二开口203b的横截面的形状。举例来说,电介质层20的第一表面201与第一开口203a的侧壁之间的夹角可大体上等于90度,且电介质层20的第一表面201与第二开口203b的侧壁之间的夹角可大于约90度(例如可在从约91度到约135度的范围内)。在一或多个实施例中,这是因为第一开口203a是通过曝光和显影来形成,且第二开口203b是通过激光钻孔形成。如图1中所示,电路层18的第一表面181的暴露部分从电介质层20的第一表面201凹入。另外,电介质层20的第二表面202的表面粗糙度(Ra)大于约0.15μm,且第一金属层16的导电金属层14的表面粗糙度(Ra)大于约0.15μm。在一或多个实施例中,电介质层20的第二表面202和/或第一金属层16的导电金属层14的表面粗糙度(Ra)可小于约0.5μm。
第二金属层22安置于载体10的第二表面102上。在一些实施例中,第二金属层22可包含底部基底金属层和底部导电金属层。底部基底金属层安置于载体10的第二表面102上,且底部导电金属层安置于底部基底金属层上。在一些实施例中,底部基底金属层可为按压在载体10上或粘附到载体10的铜箔,且底部导电金属层还可为铜箔,且粘附到底部基底金属层。在一些实施例中,底部基底金属层的厚度可不同于底部导电金属层的厚度。底部基底金属层的厚度可在底部导电金属层的厚度的约四到约六倍大的范围内。举例来说,底部基底金属层的厚度可为约18μm,且底部导电金属层的厚度可为约3μm。
在图1中说明的实施例中,电路层18(例如电路层18的75%或更多、电路层18的90%或更多、电路层18的95%或更多,或大体上整个电路层18)由第一金属层16支撑。因此,当模制操作进行到衬底结构1时,焊料凸块焊盘垫192下方将大体上不存在空的空间,因为焊料凸块焊盘垫192接触第一金属层16的导电金属层14。应注意,在模制操作之后,可去除第一金属层16(包含基底金属层12和导电金属层14)和载体10。因此,封装体44(如图4所示)的流动将极少影响焊料凸块焊盘垫192,且焊料凸块焊盘垫192大体上不会变形。因此,电路层18的厚度和宽度可减小。举例来说,电路层18的厚度可小于约20μm(例如约19μm或更少,或约18μm或更少),且电路层18的迹线19的宽度可在约7μm到约12μm的范围内,或小于约7μm。因此,电路层18的线宽和线距(L/S)可有效地减小。举例来说,电路层18的线宽和线距(L/S)可在约5μm/约5μm到约12μm/约12μm的范围内。
图2说明图1的衬底结构1的一部分的一些实施例的立体图。图3说明图1的衬底结构1的一部分的一些实施例的俯视图。在一些实施例中,电介质层20的开口203a、203b中的一或多者的大小可在约40μm*约40μm到约80μm*约80μm的范围内。举例来说,电介质层20的开口203a、203b中的一或多者的大小可为约40μm*约70μm。另外,电路层18的裸片垫191以及第一金属层16的导电金属层14的一部分在开口203a、203b中暴露。导电金属层14的暴露区域大体上等于开口203a、203b的区域。在后续焊接过程期间,如图4中所示,连接元件40(例如包含焊料)分别安置于开口203a、203b中,以接触裸片垫191以及导电金属层14的暴露区域。如果出现开口203a、203b的轻微偏移,那么开口203a、203b仍可暴露导电金属层14的足够区域,以供焊料接触,这确保焊接质量。因此,裸片垫191的宽度可设计成大体上等于迹线19的宽度(裸片垫191不需要具有大于迹线19的宽度的宽度)。如图2和图3中所示出,由于电介质层20的开口203a的大小可减小,所以迹线19与邻近迹线19a、19b之间的间距可相应地减小,且电路层18的布局可具有较多灵活性。另外,由于电路层18大体上由电介质层20覆盖(除了在开口203a、203b中暴露的裸片垫191),所以将极少有出现焊料桥接的风险或没有这样的风险。也就是说,迹线19的裸片垫191上的焊料将不接触邻近迹线19a、19b。另外,焊料可接触导电金属层14的暴露区域,因此,可很好地控制焊料与衬底结构1之间的接触面积。
图4说明根据本发明的一方面的半导体封装结构4的一些实施例的截面图。半导体封装结构4包含电路层18、电介质层20、半导体裸片3、多个连接元件40、保护层42、封装体44以及多个外部连接件46(例如焊接凸块)。
电路层18可为经图案化的电路层,且可通过电镀形成。电路层18可包含至少一个迹线19、至少一个裸片垫191和至少一个焊料凸块焊盘垫192。电路层18具有第一表面181和与第一表面181相对的第二表面182。在一些实施例中,电路层18的厚度在约10μm到约15μm的范围内,且电路层18的线宽和线距(L/S)在约5μm/约5μm到约12μm/约12μm的范围内。
电介质层20覆盖电路层18的第一表面181。电介质层20可包含以下各项或由以下各项形成:光致抗蚀剂层;经固化感光材料;经固化光可成像电介质(PID)材料,例如聚酰胺(PA)、聚酰亚胺(PI)、环氧树脂或聚苯并恶唑(PBO),或其两个或多个的组合。电介质层20具有第一表面201以及与第一表面201相对的第二表面202。电介质层20的厚度大于电路层18的厚度(例如约1.3或更多、约1.5或更多,或约1.7或更多的比率),使得电介质层20的第一表面201高于电路层18的第一表面181(且例如,覆盖其至少一部分)。电路层18的第二表面182从电介质层20的第二表面202暴露,且电路层18并不从电介质层20的第二表面202突出。在一或多个实施例中,电路层18的第二表面182可从电介质层20的第二表面202凹入。在其它实施例中,电路层18的第二表面182可与电介质层20的第二表面202大体上共面。
电介质层20界定多个开口(举例来说,包含多个第一开口203a和多个第二开口203b),其延伸穿过电介质层20以暴露电路层18的若干部分(例如裸片垫191)。在一些实施例中,第一开口203a的横截面的形状不同于第二开口203b的横截面的形状。举例来说,电介质层20的第一表面201与第一开口203a的侧壁之间的夹角可大体上等于90度,且电介质层20的第一表面201与第二开口203b的侧壁之间的夹角可大于约90度(例如可在从约91度到约135度的范围内)。在一或多个实施例中,这是因为第一开口203a是通过曝光和显影来形成,且第二开口203b是通过激光钻孔形成。应注意,第一开口203a的大小可与第二开口203b的大小大体上相同或不同。如图4中所示,电路层18的第一表面181的一部分从电介质层20的第一表面201凹入。另外,电介质层20的第二表面202的表面粗糙度(Ra)大于约0.15μm(例如为约0.17μm或更大,或为约0.19μm或更大)。
半导体裸片3通过倒装芯片接合附接到电路层18。在一些实施例中,半导体裸片3包含主体30、金属导电层32、多个晶种层36、多个铜柱38和钝化层34。主体包含作用表面301。金属导电层32安置于作用表面301上。在一些实施例中,金属导电层32包含彼此绝缘的多个片段(segments),且所述片段的材料包含例如铝(Al)、Cu、另一导电金属,或合金(例如AlCu)。钝化层34覆盖作用表面301和金属导电层32,且界定多个开口以暴露金属导电层32的若干部分。铜柱38安置为邻近于金属导电层32,且电连接到金属导电层32。在图4中说明的实施例中,晶种层36安置于钝化层34的开口中的金属导电层32上,且铜柱38安置于晶种层36上。也就是说,晶种层36的一部分安置于铜柱38和金属导电层32中的每一者之间。然而,可省略晶种层36,且铜柱38可直接安置于金属导电层32上。在一或多个实施例中,晶种层36的材料是钛合金(例如钛-铜(TiCu)合金)。
连接元件40(例如焊接凸块)电连接半导体裸片3与电路层18。连接元件40中的一或多者的至少一部分安置于电介质层20的开口203a、203b中的一或多者中,且从电介质层20的第二表面202暴露。如图4中所示,连接元件40中的每一者分别安置于铜柱38中的一者与电路层18的裸片垫191中的一者之间。在一些实施例中,连接元件40直接接触铜柱38与裸片垫191,使得半导体裸片3的铜柱38通过连接元件40电连接到电路层18。连接元件40(例如焊接凸块)的材料可包含锡(Sn)或锡-银(SnAg)合金。
保护层42安置于电介质层20的第二表面202上,以覆盖电路层18的一部分。保护层42界定多个开口423,以暴露电路层18的第二表面182的若干部分(例如焊料球焊盘垫192)。保护层42的材料可与电介质层20的材料相同或不同。
封装体44(例如模制化合物)覆盖半导体裸片3和电介质层20。如图4中所示,封装体44进一步延伸到半导体裸片3与电介质层20之间的空间中,以便覆盖铜柱38和连接元件40。然而,在一些实施例中,底填充料(underfill)可安置于半导体裸片3与电介质层20之间的空间中,以覆盖铜柱38和连接元件40(例如代替封装体44),且因此,封装体44可接触所述底填充料。另外,封装体44的侧表面可与电介质层20的侧表面和保护层42的侧表面大体上共面(例如由于封装体44,电介质层20和保护层42在同一制造阶段同时被切割)。
外部连接件46(例如焊接凸块)分别形成或安置于开口423中的相应一者中以及电路层18的暴露部分(例如焊料凸块焊盘垫192)上,以用于外部连接。举例来说,使用外部连接件46(例如焊接凸块)以将焊料凸块焊盘垫192连接到印刷电路板(PCB)。
图5说明图4的半导体封装结构4的区域“A”的放大图。区域“A”的位置对应于电介质层20的第二开口203b的位置。如图5中所示,电介质层20的第一表面201与第二开口203b的侧壁之间的夹角可大于约90度(例如可在从约91度到约135度的范围内)。在一或多个实施例中,这是因为第二开口203b可通过激光钻孔形成。所描绘的连接元件40具有外围表面401、第一表面402、内侧表面403、第二表面404、中心部分405和底部部分406。外围表面401可接触第二开口203b的侧壁。第一表面402是中心部分405与裸片垫191之间的界面。内侧表面403是底部部分406与保护层42之间的界面,且在裸片垫191下方。第二表面404是底部部分406与保护层42之间的界面,且在底部部分406下方。因此,连接元件40的底部部分406的内侧表面403和第二表面404从电介质层20的第二表面202暴露,且保护层42接触连接元件40的内侧表面403和第二表面404。在一些实施例中,连接元件40大体上填充电介质层20的第二开口203b。因此,连接元件40的暴露部分(例如底部部分406的暴露的第二表面404)中的一或多者由电介质层20的第二开口203b的底部所界定。另外,连接元件40的第二表面404与电介质层20的第二表面202共面,且电路层18的第二表面182从电介质层20的第二表面202和连接元件40的第二表面404凹入。在一些实施例中,连接元件40的第二表面404的表面粗糙度(Ra)大于电路层18的第二表面182的表面粗糙度(Ra)(例如大约1.3或更多、约1.5或更多,或约1.7或更大的倍率)。
如图5中所示,连接元件40的中心部分405包含安置为邻近于第一表面402的第一金属间化合物(IMC)41,且连接元件40的底部部分406包含安置为邻近于内侧表面403和第二表面404的第二IMC 41a。第一IMC 41是连接元件40与裸片垫191与之间的金属相互作用的结果,且第二IMC 41a是连接元件40与第一金属层16(图1)的导电金属层14之间的金属相互作用的结果。在一或多个实施例中,裸片垫191的材料可与导电金属层14的材料相同,且因此,第一IMC 41的材料可与第二IMC 41a的材料相同。然而,裸片垫191的材料可与导电金属层14的材料不同,且因此,第一IMC 41的材料可与第二IMC 41a的材料不同。举例来说,第一IMC 41和第二IMC 41a可包含Cu、镍(Ni)、Sn组合;金(Au)、Sn组合(例如AuSn4);钯(Pd)、Sn组合(例如PdSn4);或Au、Sn组合和Pd、Sn组合两者。在一实施例中,第一IMC 41和第二IMC41a可包含(Cu、Ni、Au、Pd)6Sn5(例如Cu6Sn5、Ni6Sn5、Au6Sn5或Pd6Sn5中的一或多者)和/或其它IMC。在一实施例中,第一IMC 41和第二IMC 41a可包含(Au、Pd、Ni)Sn4(例如AuSn4、PdSn4或NiSn4中的一或多者)和/或其它IMC。如图4中所示,第一IMC 41和第二IMC 41a可不连续地形成。也就是说,第一IMC 41和第二IMC 41a可为不连续结构,或第一IMC 41和第二IMC41a中的每一者可不具有一致厚度。应注意,第一IMC 41与第二IMC 41a的组合体积与连接元件40的体积的体积比可控制为小于约80%(例如约75%或更小,或约70%或更小),从而避免接合点开裂(joint cracking),且增加半导体倒装芯片接合的装置的机械可靠性。控制金属间接合以形成第一IMC 41和第二IMC 4a1的额外益处是避免了连接元件40中的空隙(void);因此,半导体倒装芯片接合的装置的寿命得以增加。
图6说明图4的半导体封装结构4的区域“B”的放大图。区域“B”的位置对应于电介质层20的第一开口203a的位置。如图6所示,电介质层20的第一表面201与第一开口203a的侧壁之间的夹角可大体上等于90度。在一或多个实施例中,这是因为第一开口203a可通过曝光和显影形成。
图7到图21说明根据本发明的一方面的用于制造半导体封装结构的方法的一些实施例的各个阶段。在一些实施例中,所述方法用于制造例如图1中所展示的衬底结构1等衬底结构。此外,所述方法还用于制造半导体封装结构,例如图4中所示的半导体封装结构4。参看图7,提供载体10。载体10可包含(例如)金属材料、陶瓷材料、玻璃材料、电介质材料或半导体晶片。载体10的形状可为(例如)大体上矩形或正方形。或者,载体10的形状可为(例如)大体上圆形或椭圆形。载体10具有第一表面101和与第一表面101相对的第二表面102。第一金属层16安置于载体10的第一表面101上。在图7中说明的实施例中,第一金属层16可包含基底金属层12和导电金属层14。基底金属层12安置于载体10的第一表面101上,且导电金属层14安置于基底金属层12上。在一些实施例中,基底金属层12可为按压在载体10上或粘附到载体10的铜箔,且导电金属层14也可为铜箔,且粘附到基底金属层12。在一些实施例中,基底金属层12的厚度可不同于导电金属层14的厚度。基底金属层12的厚度可在导电金属层14的厚度的约四到约六倍大的范围内。举例来说,基底金属层12的厚度可为约18μm,且导电金属层14的厚度可为约3μm。
第二金属层22进一步安置于载体10的第二表面102上。在一些实施例中,第二金属层22可包含底部基底金属层和底部导电金属层。底部基底金属层安置于载体10的第二表面102上,且底部导电金属层安置于底部基底金属层上。在一些实施例中,底部基底金属层可为按压在载体10上或粘附到载体10的铜箔,且底部导电金属层也可为铜箔,且粘附到底部基底金属层。在一些实施例中,底部基底金属层的厚度可不同于底部导电金属层的厚度。底部基底金属层的厚度可在底部导电金属层的厚度的约四到约六倍大的范围内。举例来说,底部基底金属层的厚度可为约18μm,且底部导电金属层的厚度可为约3μm。
如图7中所示,顶部结构1a和底部结构1b通过释放层(release layer)48附接在一起。在一些实施例中,顶部结构1a的元件与底部结构1b的元件相同或相似。也就是说,顶部结构1a和底部结构1b两者包含载体10、第一金属层16和第二金属层22的实施方案。举例来说,顶部结构1a的第二金属层22通过释放层48附接到底部结构1b的第二金属层22。因此,可对顶部结构1a和底部结构1b中的一者,或同时对顶部结构1a和底部结构1b两者执行下文所描述的过程。为简单起见,本文参考顶部结构1a和底部结构1b中的一者来描述一些此类过程的描述,但可同时对顶部结构1a和底部结构1b两者执行所述过程。
参看图8,光致抗蚀剂层50(例如干膜)例如通过层压(laminating)形成于第一金属层16的导电金属层14上。接着,例如通过曝光和显影来形成延伸穿过光致抗蚀剂层50的多个开口501。
参看图9,电路层18形成于光致抗蚀剂层50的开口501中,且安置于第一金属层16上。在一些实施例中,电路层18安置于第一金属层16的导电金属层14上。在一些实施例中,电路层18可为经图案化的电路层,且可通过电镀形成。电路层18可包含至少一个迹线19、至少一个裸片垫191和至少一个焊料凸块焊盘垫192。电路层18具有第一表面181和与第一表面181相对的第二表面182。电路层18的第二表面182直接接触第一金属层16的导电金属层14。在一些实施例中,电路层18的厚度在约10μm到约15μm的范围内,且电路层18的线宽和线距(L/S)在约5μm/约5μm到约12μm/约12μm的范围内。
参看图10,举例来说,通过剥离来去除光致抗蚀剂层50。
参看图11,举例来说,通过层压形成电介质层20,以覆盖电路层18和第一金属层16的导电金属层14。电介质层20可包含以下各项或由以下各项形成:光致抗蚀剂层;经固化感光材料;经固化光可成像电介质(PID)材料,例如聚酰胺(PA)、聚酰亚胺(PI)、环氧树脂或聚苯并恶唑(PBO),或其两个或多个的组合。电介质层20具有第一表面201以及与第一表面201相对的第二表面202。电介质层20的厚度大于电路层18的厚度(例如大约1.3或更多、约1.5或更多,或约1.7或更大的倍率),使得电介质层20的第二表面202与电路层18的第二表面182大体上共面,且电介质层20的第一表面201高于电路层18的第一表面181(且例如覆盖其至少一部分)。另外,电介质层20的第二表面202的表面粗糙度(Ra)大于约0.15μm,且第一金属层16的导电金属层14的表面粗糙度(Ra)大于约0.15μm。在一或多个实施例中,电介质层20的第二表面202和/或第一金属层16的导电金属层14的表面粗糙度(Ra)可小于约0.5μm。
参看图12,多个第一开口203a形成于电介质层20中,以暴露电路层18的若干部分(例如裸片垫191)以及第一金属层16的导电金属层14的若干部分。第一开口203a延伸穿过电介质层20。电介质层20的第一开口203a的宽度大于电路层18的迹线19的宽度(例如大约1.1或更多、约1.2或更多,或约1.3或更大的倍率),以便暴露电路层18的迹线19的第一表面181和至少两个侧表面。应注意,迹线19的暴露部分包含裸片垫191。在一些实施例中,电介质层20的第一表面201与第一开口203a的侧壁之间的夹角可大体上等于90度。这是因为第一开口203a是通过曝光和显影形成的。
参看图13,多个第二开口203b形成于电介质层20中,以暴露电路层18的若干部分(例如裸片垫191)以及第一金属层16的导电金属层14的若干部分。第二开口203b延伸穿过电介质层20。电介质层20的第二开口203b的宽度大于电路层18的迹线19的宽度(例如大约1.1或更多、约1.2或更多,或约1.3或更大的倍率),以便暴露电路层18的迹线19的第一表面181以及至少两个侧表面。应注意,迹线19的暴露部分包含裸片垫191。在一些实施例中,电介质层20的第一表面201与第二开口203b的侧壁之间的夹角可大于约90度(例如可在从约91度到约135度的范围内)。这是因为第二开口203b是由激光50形成。因此,将顶部结构1a和底部结构1b中的每一者制造成变为衬底结构1'。
参看图14,衬底结构1'例如通过热释放从释放层48分离。应注意,可将衬底结构1'单体化,以形成如图1中所示的多个衬底结构1。
参看图15,提供衬底结构1'中的一者。如上文所论述,衬底结构1'包含载体10、第一金属层16、电路层18、电介质层20和第二金属层22。接着,半导体裸片3通过经由多个连接元件40的倒装芯片接合附接到衬底结构1'。
在一些实施例中,半导体裸片3包含主体30、金属导电层32、多个晶种层36、多个铜柱38和钝化层34。主体30包含作用表面301。金属导电层32安置于作用表面301上。在一些实施例中,金属导电层32包含彼此绝缘的多个片段,且所述片段的材料包含例如Al、Cu、另一导电金属,或合金(例如AlCu)。钝化层34覆盖作用表面301和金属导电层32,且界定多个开口以暴露金属导电层32的若干部分。铜柱38安置为邻近于金属导电层32,且电连接到金属导电层32。在图15中说明的实施例中,晶种层36安置于钝化层34的开口中的金属导电层32上,且铜柱38安置于晶种层36上。也就是说,晶种层36的一部分安置于铜柱38和金属导电层32中的每一者之间。然而,可省略晶种层36,且铜柱38可直接安置于金属导电层32上。在一实施例中,晶种层36的材料是钛合金(例如TiCu)。
连接元件40(例如焊接凸块)电连接半导体裸片3与电路层18。连接元件40中的每一者的至少一部分分别安置于电介质层20的开口203a、203b中的电路层18的暴露部分(例如裸片垫191)和第一金属层16的导电金属层14的暴露部分上。如图15中所示,连接元件40中的每一者分别安置于铜柱38中的一者与电路层18的裸片垫191之间。在一些实施例中,连接元件40直接接触铜柱38与裸片垫191,使得半导体裸片3的铜柱38通过连接元件40电连接到电路层18。连接元件40的材料可包含锡(Sn)或锡-银(SnAg)合金。
图16说明图15中的区域“C”的放大图。区域“C”的位置对应于电介质层20的第二开口203b的位置。连接元件40包含外围表面401、第一表面402、第二表面404、中心部分405和底部部分406。外围表面401可接触第二开口203b的侧壁。第一表面402是中心部分405与裸片垫191之间的界面。第二表面404是底部部分406与导电金属层14之间的界面。在一些实施例中,连接元件40大体上填充电介质层20的第一开口203a或第二开口203b,且因此,覆盖并接触电介质层20的开口203a或203b中的第一金属层16的导电金属层14的暴露部分。因此,连接元件40的底部部分406的第二表面404由电介质层20的第一开口203a或第二开口203b的底部界定。另外,连接元件40的第二表面404与电介质层20的第二表面202共面。
如图16中所示,连接元件40的中心部分405包含安置为邻近于第一表面402的第一金属间化合物(IMC)41,且连接元件40的底部部分406包含安置为邻近于第二表面404的第二IMC 41a。第一IMC 41是连接元件40与裸片垫191与之间的金属相互作用的结果,且第二IMC 41a是连接元件40与第一金属层16的导电金属层14之间的金属相互作用的结果。在一或多个实施例中,裸片垫191的材料可与导电金属层14的材料相同,且因此,第一IMC 41的材料可与第二IMC 41a的材料相同。然而,裸片垫191的材料可与导电金属层14的材料不同,且因此,第一IMC 41的材料可与第二IMC 41a的材料不同。举例来说,第一IMC 41和第二IMC41a可包含Cu、Ni、Sn组合;Au、Sn组合,例如AuSn4;Pd、Sn组合,例如PdSn4;或Au、Sn组合和Pd、Sn组合两者。在一实施例中,第一IMC 41和第二IMC 41a可包含(Cu、Ni、Au、Pd)6Sn5(例如Cu6Sn5、Ni6Sn5、Au6Sn5或Pd6Sn5中的一或多者)以及其它IMC。在一实施例中,第一IMC 41和第二IMC 41a可包含(Au、Pd、Ni)Sn4(例如AuSn4、PdSn4或NiSn4中的一或多者)以及其它IMC。如图16中所示,第一IMC 41和第二IMC 41a可不连续地形成。也就是说,第一IMC 41和第二IMC41a可为不连续结构,或第一IMC 41和第二IMC 41a中的每一者可不具有一致厚度。应注意,第一IMC 41与第二IMC 41a的组合体积与连接元件40的体积的体积比控制为小于80%(例如75%或更小,或70%或更小),从而避免接合点开裂,且增加半导体倒装芯片接合的装置的机械可靠性。控制金属间接合以形成第一IMC 41和第二IMC 4a1的额外益处是避免了连接元件40中的空隙;因此,半导体倒装芯片接合的装置的寿命得以增加。
参看图17,进行模制操作。形成封装体44(例如模制化合物),以覆盖衬底结构1'的半导体裸片3和电介质层20。如图17中所示出,封装体44进一步延伸到半导体裸片3与电介质层20之间的空间中,以便覆盖铜柱38和连接元件40。然而,在一些实施例中,底填充料可安置于半导体裸片3与电介质层20之间的空间中(例如代替封装体44),以覆盖铜柱38和连接元件40,且因此,封装体44可接触底填充料。
在模制操作期间,如图17,电路层18(例如电路层18的75%或更多、电路层18的90%或更多、电路层18的95%或更多,或大体上整个电路层18)由第一金属层16支撑。因此,焊料凸块焊盘垫192下方将大体上不存在空的空间,因为焊料凸块焊盘垫192仍接触第一金属层16的导电金属层14。封装体44的流动大体上不会影响焊料凸块焊盘垫192,且焊料凸块焊盘垫192大体上不会变形。因此,电路层18的厚度和宽度可减小。因此,电路层18的线宽和线距(L/S)可有效地减小。
参看图18,去除载体10和基底金属层12,或使其从导电金属层14分离。
参看图19,举例来说,通过蚀刻来去除第一金属层16的导电金属层14。也就是说,将蚀刻剂54施加到导电金属层14。
参看图20,过度蚀刻电路层18的第二表面182,使得电路层18的第二表面182暴露,且从电介质层20的第二表面202和连接元件40的第二表面404凹入,如图5和图6所示。同时,形成连接元件40的内侧表面403。内侧表面403安置为邻近于电路层18的迹线19的底部拐角。
参看图21,保护层42形成于电介质层20的第二表面202上,以覆盖电路层18的第二表面182的一部分。保护层42界定多个开口423,以暴露电路层18的第二表面182的若干部分(例如焊料凸块焊盘垫192)。保护层42的材料可与电介质层20的材料相同或不同。
接着,进行单切工艺(singulation process),以形成如图4中所示的多个半导体封装结构4。另外,多个外部连接件46(例如焊接凸块)分别形成或安置于开口423中的相应一者中以及电路层18的暴露部分(例如焊料凸块焊盘垫192)上,以用于外部连接。
除非另外说明,否则例如“上方”、“下方”、“上”、“左”、“右”、“下”、“顶部”、“底部”、“垂直”、“水平”、“侧面”、“高于”、“低于”、“上部”、“在……上”、“在……下”等等的空间描述是相对于图中所示的定向来指示的。应理解,本文中所使用的空间描述仅是出于说明的目的,且本文中所描述的结构的实际实施方案可在空间上以任何定向或方式布置,其限制条件是本发明的实施例的优点不因此类布置而有偏差。
如本文所使用,术语“大约”、“大体上”、“大体”和“约”用于描述和说明小变化。当与事件或情形结合使用时,所述术语可指其中事件或情形明确发生的情况以及其中事件或情形极接近于发生的情况。举例来说,当结合数值使用时,术语可指代小于或等于所述数值的±10%的变化范围,例如小于或等于±5%、小于或等于±4%、小于或等于±3%、小于或等于±2%、小于或等于±1%、小于或等于±0.5%、小于或等于±0.1%、或小于或等于±0.05%。举例来说,如果两个数值之间的差小于或等于所述值的平均值的±10%(例如小于或等于±5%、小于或等于±4%、小于或等于±3%、小于或等于±2%、小于或等于±1%、小于或等于±0.5%、小于或等于±0.1%、或小于或等于±0.05%),那么可认为所述两个数值“基本上”相同或相等。
如果两个表面之间的位移不大于5μm、不大于2μm、不大于1μm、不大于0.5μm或不大于0.1μm,那么可认为这两个表面共面或大体上共面。如果表面的最高点与最低点之间的差不大于5μm、不大于2μm、不大于1μm、不大于0.5μm或不大于0.1μm,那么可认为表面为平面或大体上平面。
另外,有时在本文中按范围格式呈现量、比率和其它数值。应理解,此类范围格式是用于便利和简洁起见,且应灵活地理解,不仅包含明确地指定为范围限制的数值,而且包含涵盖于所述范围内的所有个别数值或子范围,如同明确地指定每一数值和子范围一般。
虽然已参考本发明的特定实施例描述并说明本发明,但这些描述及说明并非限制性的。所属领域的技术人员应理解,可在不脱离如由所附权利要求书界定的本揭示的真实精神和范围的情况下,作出各种改变且取代等效物。说明可能未必按比例绘制。由于制造工艺和公差,本发明中的艺术再现与实际设备之间可存在区别。可存在并未特定说明的本揭露的其它实施例。应将所述说明书和图式视为说明性的,而非限制性的。可做出修改,以使特定情况、材料、物质组成、方法或过程适应于本发明的目标、精神以及范围。所有此类修改既定在所附权利要求书的范围内。虽然本文中所揭示的方法已参考按特定次序执行的特定操作加以描述,但应理解,可在不脱离本发明的教示的情况下组合、细分或重新排序这些操作以形成等效方法。因此,除非本文中特别指示,否则操作的次序和分组并非本发明的限制。
Claims (27)
1.一种衬底结构,其包括:
载体,其具有第一表面和第二表面;
第一金属层,其安置于所述载体的所述第一表面上;
电路层,其安置于所述第一金属层上;以及
电介质层,其覆盖所述电路层,且界定多个开口,以暴露所述电路层的若干部分和所述第一金属层的若干部分。
2.根据权利要求1所述的衬底结构,其中所述第一金属层包含基底金属层和导电金属层,所述基底金属层安置于所述载体的所述第一表面上,所述导电金属层安置于所述基底金属层上,且所述电路层安置于所述导电金属层上。
3.根据权利要求1所述的衬底结构,其中所述电路层的第一表面从所述电介质层的第一表面凹入。
4.根据权利要求1所述的衬底结构,其中所述电介质层的第二表面的表面粗糙度Ra大于约0.15微米(μm)。
5.根据权利要求1所述的衬底结构,其中所述电路层的厚度在约10μm到约15μm的范围内,且所述电路层的线宽和线距(L/S)在约5μm/约5μm到约12μm/约12μm的范围内。
6.根据权利要求1所述的衬底结构,其中所述电介质层的所述多个开口的至少一个开口的大小在约40μm*约40μm到约80μm*约80μm的范围内。
7.根据权利要求1所述的衬底结构,其进一步包括安置于所述载体的所述第二表面上的第二金属层。
8.一种半导体封装结构,其包括:
电路层;
电介质层,其覆盖所述电路层的第一表面,且具有第一表面和第二表面,其中所述电介质层界定开口以暴露所述电路层的一部分,且所述开口延伸穿过所述电介质层;
半导体裸片,其通过倒装芯片接合附接到所述电路层;以及
连接元件,其电连接所述半导体裸片与所述电路层,其中所述连接元件的至少一部分安置于所述电介质层的所述开口中,且从所述电介质层的所述第二表面暴露。
9.根据权利要求8所述的半导体封装结构,其中所述电路层的第二表面从所述电介质层的所述第二表面暴露,且所述电路层并不从所述电介质层的所述第二表面突出。
10.根据权利要求8所述的半导体封装结构,其中所述连接元件的材料包含锡,所述连接元件的底部部分从所述电介质层的所述第二表面暴露,且所述连接元件的所述底部部分包含金属间化合物(IMC)。
11.根据权利要求10所述的半导体封装结构,其中所述IMC包含铜和锡的组合。
12.根据权利要求8所述的半导体封装结构,其中所述连接元件的表面与所述电介质层的所述第二表面共面,且所述电路层的第二表面从所述电介质层的所述第二表面凹入。
13.根据权利要求8所述的半导体封装结构,其中所述连接元件的表面的表面粗糙度(Ra)大于所述电路层的第二表面的表面粗糙度(Ra)。
14.根据权利要求8所述的半导体封装结构,其进一步包括安置于所述电介质层的所述第二表面上以覆盖所述电路层的保护层,其中所述保护层界定多个开口,以暴露所述电路层的第二表面的若干部分。
15.根据权利要求14所述的半导体封装结构,其中所述保护层接触所述连接元件的内侧表面。
16.根据权利要求14所述的半导体封装结构,其中所述保护层的材料与所述电介质层的材料相同。
17.根据权利要求8所述的半导体封装结构,其进一步包括覆盖所述半导体裸片和所述电介质层的封装体。
18.根据权利要求8所述的半导体封装结构,其中所述电介质层的所述第二表面的表面粗糙度(Ra)大于约0.15μm。
19.一种半导体封装结构,其包括:
电路层;
电介质层,其覆盖所述电路层的第一表面,且界定多个开口以暴露所述电路层的若干部分;
半导体裸片,其通过倒装芯片接合附接到所述电路层;以及
多个连接元件,其电连接所述半导体裸片与所述电路层的由所述开口暴露的所述部分,其中所述连接元件中的每一者的至少一部分分别安置于所述电介质层的所述开口中,且从所述电介质层的表面暴露,其中所述连接元件的所述暴露部分的形状分别由所述电介质层的所述开口界定。
20.根据权利要求19所述的半导体封装结构,其中所述连接元件中的至少一者接触所述电介质层的所述开口中的一者的侧壁。
21.根据权利要求19所述的半导体封装结构,其中所述连接元件中的至少一者填充所述电介质层的所述开口中的一者。
22.一种用于制造半导体封装结构的方法,其包括:
(a)提供衬底结构,其中所述衬底结构包括载体、金属层、电路层和电介质层,其中所述载体具有第一表面和第二表面,所述金属层安置于所述载体的所述第一表面上,所述电路层安置于所述金属层上,且所述电介质层覆盖所述电路层,且界定多个开口以暴露所述电路层的若干部分和所述金属层的若干部分;以及
(b)通过经由多个连接元件的倒装芯片接合将半导体裸片附接到所述衬底结构,其中所述连接元件分别安置于所述电介质层的所述开口中的所述电路层的所述暴露部分以及所述金属层的所述暴露部分上。
23.根据权利要求22所述的方法,其中所述电路层包括迹线,且在(a)中,所述电介质层的所述开口中的至少一者的宽度大于所述电路层的所述迹线的宽度,以便暴露所述电路层的所述迹线的第一表面和至少两个侧表面。
24.根据权利要求22所述的方法,其中在(b)中,所述连接元件的材料包含锡。
25.根据权利要求22所述的方法,其中在(b)之后,所述方法进一步包括:
(c)形成封装体以覆盖所述半导体裸片和所述衬底结构的所述电介质层;以及
(d)去除所述载体。
26.根据权利要求25所述的方法,其中在(d)之后,所述方法进一步包括:
(e)去除所述金属层以及所述电路层的一部分。
27.根据权利要求26所述的方法,其中在(e)之后,所述方法进一步包括:
(f)在所述电介质层的表面上形成保护层以覆盖所述电路层,其中所述保护层界定多个开口以暴露所述电路层的表面的若干部分。
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US20190259722A1 (en) * | 2018-02-21 | 2019-08-22 | Rohm And Haas Electronic Materials Llc | Copper pillars having improved integrity and methods of making the same |
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US20180240745A1 (en) | 2018-08-23 |
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