CN110571158B - 半导体装置封装及其制造方法 - Google Patents

半导体装置封装及其制造方法 Download PDF

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CN110571158B
CN110571158B CN201910779348.8A CN201910779348A CN110571158B CN 110571158 B CN110571158 B CN 110571158B CN 201910779348 A CN201910779348 A CN 201910779348A CN 110571158 B CN110571158 B CN 110571158B
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insulating layer
disposed
carrier
conductive pillars
substrate
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CN110571158A (zh
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陈天赐
陈光雄
王圣民
李育颖
彭淯慈
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

一种半导体封装及其制造方法，所述半导体封装包括衬底、接垫、第一绝缘层、互连层和预先形成的导电柱。所述第一绝缘层安置于所述衬底上，且包括开口。所述接垫安置于所述衬底上且从所述开口暴露。所述互连层安置于所述接垫上。所述预先形成的导电柱，其包括底部表面，所述底部表面具有安置于所述互连层上的第一部分以及安置于所述第一绝缘层上且接触所述第一绝缘层的第二部分。

Description

半导体装置封装及其制造方法
本申请是中国专利申请号为：201710299264.5，申请日期为：2017年4月28日，以及申请名称为：“半导体装置封装及其制造方法”的申请的分案申请。
相关申请案的交叉参考
本申请案主张2016年6月20日申请的第62/352,299号以及2016年5月11日申请的第62/334,861号美国专利申请案的权益和优先权，其完整内容以引入的方式并入本文中。
技术领域
本发明涉及一种半导体装置封装及其制造方法。明确地说，本发明涉及同时安置在焊膏和阻焊剂两者上的铜柱。
背景技术
对于一些半导体封装(由例如封装上封装(PoP)技术形成)，焊料球用于外部连接或互连。然而，焊料球的间距的长度可妨碍小型化。细间距铜(Cu)柱技术可取而代之用于小型化。此类技术的一种方法是在钝化层中形成孔以接纳Cu柱。然而，归因于Cu柱的相对较小的间距，将Cu柱植入孔中可能具有挑战性。此类技术的间距可受机械加工工具能力限制。另一方法是将Cu柱安置在导电衬接垫上，且接着执行后续操作。在此方法中，Cu柱直接安置在焊膏上(例如传导接垫上)，其中焊膏的面积大于Cu柱的面积。在回焊操作期间，熔化的焊膏(其在加热时可流动)可能无法支撑Cu柱。在这些情况下，Cu柱可能被流动的焊膏移动。
发明内容
在一些实施例中，根据一方面，一种半导体封装包括衬底、接垫、第一绝缘层、互连层和导电柱。所述衬底具有第一表面和与所述第一表面相对的第二表面。所述接垫包含第一部分和第二部分，且安置于所述衬底的第一表面上。所述第一绝缘层安置于所述第一表面上，且覆盖所述接垫的所述第一部分，且所述第一绝缘层具有顶部表面。所述互连层安置于所述接垫的所述第二部分上，且具有顶部表面。所述导电柱安置于所述第一绝缘层的所述顶部表面上以及所述互连层的所述顶部表面上。所述第一绝缘层的所述顶部表面与所述互连层的所述顶部表面大体上共面。
在一些实施例中，根据另一方面，一种半导体封装包括衬底、导电接垫、第一绝缘层、互连层、第二绝缘层和导电柱。所述衬底具有第一表面和与所述第一表面相对的第二表面。所述导电接垫安置于所述衬底的所述第一表面上，且包含第一部分、第二部分和第三部分。所述第一绝缘层安置于所述导电接垫的所述第一部分上。所述互连层安置于所述接垫的所述第二部分上，且具有顶部表面。所述第二绝缘层安置于所述接垫的所述第三部分上。所述导电柱安置于所述互连层上以及所述第一绝缘层上。所述互连层的所述顶部表面与所述第一绝缘层的所述顶部表面大体上共面。
在一些实施例中，根据另一方面，一种制造半导体装置封装的方法包含：提供衬底，其具有第一表面、与所述第一表面相对的第二表面，以及包含所述第一表面上的第一部分和第二部分的导电接垫；形成第一绝缘层以覆盖所述导电接垫的所述第一部分，所述第一绝缘层具有顶部表面；将导电层安置在所述导电接垫的所述第二部分上，所述导电层具有顶部表面；以及将导电元件安置在所述第一绝缘层的所述顶部表面以及所述导电层的所述顶部表面上；其中所述第一绝缘层的所述顶部表面和所述导电层的所述顶部表面大体上共面。
附图说明
图1A是根据本发明的一些实施例的半导体装置封装的透视图。
图1B是根据本发明的一些实施例的半导体装置封装的横截面视图。
图1C是根据本发明的一些实施例的半导体装置封装的横截面视图。
图2A说明根据本发明的一些实施例的半导体装置封装中的导电柱的布局。
图2B说明根据本发明的一些实施例的半导体装置封装的导电柱的布局。
图2C说明根据本发明的一些实施例的半导体装置封装中的导电柱的布局。
图3A是根据本发明的一些实施例的半导体装置封装的透视图。
图3B是根据本发明的一些实施例的半导体装置封装的横截面视图。
图3C为根据本发明的一些实施例的半导体装置封装的横截面视图。
图4A说明根据本发明的一些实施例的半导体装置封装中的接垫的布局。
图4B是根据本发明的一些实施例的半导体装置封装的横截面视图。
图5A说明根据本发明的一些实施例的半导体装置封装中的接垫的布局。
图5B是根据本发明的一些实施例的半导体装置封装的横截面视图。
图6A描绘根据本发明的一些实施例的半导体装置封装中的导电柱的布局。
图6B描绘根据本发明的一些实施例的半导体装置封装中的导电柱的布局。
图6C描绘根据本发明的一些实施例的半导体装置封装中的导电柱的布局。
图6D描绘根据本发明的一些实施例的半导体装置封装中的导电柱的布局。
图6E描绘根据本发明的一些实施例的半导体装置封装中的导电柱的布局。
图6F描绘根据本发明的一些实施例的半导体装置封装中的导电柱的布局。
图6G描绘根据本发明的一些实施例的半导体装置封装中的导电柱的布局。
图7A是根据本发明的一些实施例的半导体装置封装的横截面视图。
图7B是根据本发明的一些实施例的半导体装置封装的横截面视图。
图7C是根据本发明的一些实施例的半导体装置封装的横截面视图。
图7D是根据本发明的一些实施例的半导体装置封装的横截面视图。
图7E是根据本发明的一些实施例的半导体装置封装的横截面视图。
图8A、图8B、图8C、图8D、图8E、图8F和图8G说明根据本发明的一些实施例的制造半导体装置封装的方法。
图9A、图9B、图9C、图9D、图9E和图9F说明根据本发明的一些实施例的制造半导体装置封装的方法。
图10A、图10B、图10C、图10D和图10E说明根据本发明的一些实施例的制造半导体装置封装的方法。
图11是根据本发明的一些实施例的半导体装置封装的横截面视图。
图12A、图12B和图12C说明根据本发明的一些实施例的制造半导体装置封装的方法。
图13A、图13B和图13C说明根据本发明的一些实施例的制造半导体装置封装的方法。
图14是根据本发明的一些实施例的半导体装置封装的横截面视图。
图15A、图15B、图15C和图15D说明根据本发明的一些实施例的制造半导体装置封装的方法。
图16A、图16B、图16C和图16D说明根据本发明的一些实施例的制造半导体装置封装的方法。
具体实施方式
贯穿图式和详细描述使用共同参考数字来指示相同或类似组件。本发明的实施例将容易从结合附图进行的以下详细描述理解。
相对于某一组件或组件群组或组件或组件群组的某一平面而指定空间描述，例如“上方”、“下方”、“向上”、“左”、“右”、“向下”、“顶部”、“底部”、“垂直”、“水平”、“侧”、“较高”“较低”、“上部”、“之上”、“之下”等，以用于定向如相关联图中所示的组件。应理解，本文中所使用的空间描述仅是出于说明的目的，且本文中所描述的结构的实际实施方案可以任何定向或方式在空间上布置，前提是本发明的实施例的优点不因此布置而有偏差。
图1A是根据本发明的一些实施例的半导体装置封装10的透视图。半导体装置封装10包含载体100、接垫104(图1A中未图示)、绝缘层106、互连层108和导电柱110。绝缘层106部分地覆盖接垫104。绝缘层106可界定使接垫104的至少一部分暴露的开口。接垫104的不被绝缘层106覆盖的暴露部分可具有大体上矩形或大体上正方形形状。在其它实施例中，接垫104可具有另一形状，例如大体上圆形或大体上卵形形状。导电柱110安置于绝缘层106上以及互连层108上。在一些实施例中，互连层108的外缘的形状可为大体上矩形或大体上正方形。
图1B是根据本发明的一些实施例的沿图1A中所示的交叉线1B的半导体装置封装10的横截面视图。
载体100具有表面101和与表面101相对的表面102。在本文所述的一些实施例中，载体100的表面101被称作顶部表面或第一表面，且所述衬底的表面102被称作底部表面或第二表面。载体100可为或可包含(例如)印刷电路板，例如基于纸的铜箔层压体、复合铜箔层压体，或聚合物浸染的基于玻璃纤维的铜箔层压体。载体100可包含互连结构，例如再分布层(RDL)或接地元件。在一些实施例中，接地元件是从载体100的侧表面暴露的通孔。在一些实施例中，接地元件是从载体100的侧表面暴露的金属层。在一些实施例中，接地元件是从载体100的侧表面暴露的金属迹线。
接垫104安置于载体100的表面101上。绝缘层106安置于载体100的表面101上，并覆盖接垫104的第一部分。接垫104的第二部分从绝缘层106暴露。互连层108形成于接垫104的暴露部分上，在绝缘层106所界定的开口之上。在一些实施例中，所述开口的面积可在大约0.0125平方毫米(mm2)(例如可由具有大约0.05mm x大约0.25mm的长度的侧界定)到大约0.08mm2(例如可由具有大约0.2mm x大约0.4mm的长度的侧界定)的范围内。互连层108安置于接垫104上，且由绝缘层106包围。绝缘层106具有顶部表面106a。绝缘层106可为阻焊剂，例如钝化材料、树脂或聚合物。互连层108具有顶部表面108a。互连层108可由Sn(锡)和/或其它合适的金属材料制成或可包含所述材料。可酌情设定互连层108的体积和/或重量。导电柱110安置于绝缘层106的顶部表面106a上，以及互连层108的顶部表面108a上。在一些实施例中，导电柱110的宽度(例如如图1B中所描绘的水平方向上的延伸部分)可在大约0.15mm到大约0.3mm的范围内。在一些实施例中，导电柱110可为大体上圆柱形形状，且导电柱110的直径可在大约0.15mm到大约0.3mm的范围内。在一些实施例中，导电柱110的第一直径可沿第一方向延伸，且可在互连层108之上且不在绝缘层106之上延伸，且与第一直径在相同平面内的导电柱110的第二直径可沿与第一方向正交的第二方向延伸，且可部分地在互连层108之上延伸，且可进一步部分地在绝缘层106之上延伸，如图1A中示出。换句话说，可将对应于导电柱110的直径的第一假想线绘制成在互连层108之上且不在绝缘层106之上延伸(例如可沿图1A中所示的线1C-1C绘制)，且可在与第一假想线不同的方向上绘制也对应于导电柱110的直径的第二假想线，且可在互连层108和绝缘层106两者之上延伸(例如沿图1A中所示的线1B-1B)。绝缘层106的顶部表面106a与互连层108的顶部表面108a大体上共面。
导电柱110具有底部表面110b，其具有第一部分和第二部分。导电柱110的底部表面110b的第一部分接触互连层108的顶部表面108a，且导电柱110的底部表面110b的第二部分接触绝缘层106的顶部表面106a。导电柱110的底部表面110b的第一部分的面积与导电柱110的底部表面110b的第二部分大体上相同或大于所述第二部分的面积。导电柱110可由Cu和/或其它合适的金属材料制成。绝缘层106和导电柱110由模制化合物112包覆。在一些实施例中，导电柱110在回焊操作期间大体上保持其原始位置，且导电柱110的位置不受熔化的互连层108的流动显著影响，至少部分地因为导电柱110是由绝缘层106支撑。
图1C是根据本发明的一些实施例的沿交叉线1C的半导体装置封装10的横截面视图。绝缘层106安置于载体100的表面101上。绝缘层106安置于载体100的表面101上，且部分地覆盖接垫104的第一部分。接垫104的第二部分从绝缘层106暴露。互连层108安置于接垫104上，且由绝缘层106包围。导电柱110安置于互连层108上。绝缘层106的顶部表面106a与互连层108的顶部表面108a大体上共面。
图2A说明根据本发明的一些实施例的半导体装置封装10中的导电柱110的布局。绝缘层106部分地覆盖接垫104，从而留下接垫104的从绝缘层106暴露的部分。接垫104的暴露部分具有环形形状。在一些实施例中，环形暴露部分的直径可在大约0.05mm到大约0.2mm的范围内。互连层108安置于接垫104的暴露部分上。互连层108的形状是环形。导电柱110安置于绝缘层106和互连层108上，且大体上由绝缘层106支撑。互连层108大体上完全被导电柱110覆盖。互连层108和导电柱110形式大体上同心的圆。在一些实施例中，导电柱110的直径可在大约0.15mm到大约0.3mm的范围内。
图2B说明根据本发明的一些实施例的半导体装置封装10中的导电柱110的布局。图2B的布局类似于图2A的布局。由绝缘层106界定的使接垫104暴露的开口具有环形形状。互连层108形成于接垫104的暴露部分上。互连层108的形状是环形。导电柱110安置于绝缘层106和互连层108上，且大体上由绝缘层106支撑。互连层108大体上完全被导电柱110覆盖。互连层108的边缘的部分与导电柱110的边缘的部分重叠。导电柱110的中心与互连层108的中心间隔开。
图2C说明根据本发明的一些实施例的半导体装置封装10中的导电柱110的布局。图2C的布局类似于图2B的布局。互连层108的形状是环形。导电柱110安置于绝缘层106上和互连层108上，且大体上由绝缘层106支撑。互连层108部分地被导电柱110覆盖。导电柱110的中心与互连层108的中心间隔开。
图3A是根据本发明的一些实施例的半导体装置封装20的透视图。半导体装置封装20的结构类似于半导体装置封装10的结构。半导体装置封装20包含载体200、绝缘层206、互连层208、导电柱210和模制化合物212。在一些实施例中，互连层208的形状可为环形。互连层208可在回焊操作期间缩小。在回焊操作之后，模制化合物212可施加到半导体装置封装20，且可包覆接垫204(例如，如图3C中示出)、绝缘层206、互连层208和导电柱210。
在一些实施例中，互连层208安置于接垫204上，且导电柱210随后安置于互连层208上。在一些实施例中，互连层208附接到导电柱210，且导电柱210和互连层208随后安置于接垫204上。因此，在一些实施例中，多个导电柱之间的间距将不一定受加工工具能力限制(例如将不一定受用以在小间距配置中在已经附接到半导体装置封装的互连层上形成导电柱210的工具的能力限制)，且灵活性可得以增强。
图3B是根据本发明的一些实施例的沿交叉线2B的半导体装置封装20的横截面视图。载体200具有顶部表面201和与顶部表面201相对的底部表面202。绝缘层206具有顶部表面206a。接垫204安置于载体200的顶部表面201上。绝缘层206安置于载体200的顶部表面201上，且部分地覆盖接垫204。互连层208具有顶部表面208a。类似于图1B的结构，导电柱210具有顶部表面210a和底部表面210b，且导电柱210安置于绝缘层206的顶部表面206a上以及互连层208的顶部表面208a上。绝缘层206的顶部表面206a与互连层208的顶部表面208a大体上共面。导电柱210的底部表面210b具有第一部分和第二部分。第一部分接触互连层208的顶部表面208a，且第二部分接触第一绝缘层206的顶部表面206a。导电柱210的底部表面210b的第一部分的面积与导电柱210的底部表面210b的第二部分大体上相同或大于所述第二部分的面积。
图3C是根据本发明的一些实施例的沿交叉线2C的半导体装置封装20的横截面视图。可酌情设定互连层208的体积和/或重量，且可酌情设定互连层208的顶部表面208a的面积。在一些实施例中，互连层208可为大体上环形形状，且互连层208的直径可在大约0.05mm到大约0.2mm的范围内。互连层208可在回焊操作期间缩小，从而产生或增大绝缘层206与互连层208之间的间隙。可用模制化合物212来填充所述间隙。模制化合物212接触接垫204、绝缘层206、互连层208和导电柱210中的每一者。模制化合物212包覆接垫204、绝缘层206、互连层208和导电柱210中的每一者。
在一些实施例中，接垫204具有第一部分、第二部分和第三部分。绝缘层206覆盖接垫204的第一部分。互连层208接触并覆盖接垫204的第二部分。模制化合物212接触并覆盖所述接垫的第三部分。在一些实施例中，导电柱210在回焊操作期间大体上维持其原始位置，且导电柱210的位置不受熔化的互连层208的流动显著影响，至少部分地因为导电柱210由绝缘层206和模制化合物212两者支撑。
图4A说明根据本发明的一些实施例的半导体装置封装10中的接垫104的布局。绝缘层106安置于载体100上。绝缘层106界定开口。接垫104和迹线116形成于所述开口中。绝缘层106包围接垫104和迹线116。迹线116的一端可接触绝缘层106。互连层108形成于所述开口中。互连层108完全覆盖接垫104和迹线116。
图4B是根据本发明的一些实施例的半导体装置封装10的横截面视图。绝缘层106形成于载体100上。接垫104形成于载体100上。互连层108形成于载体10上，且完全覆盖接垫104。绝缘层106的顶部表面与互连层108的顶部表面共面。导电柱110安置于绝缘层106上和互连层108上，且大体上由绝缘层106支撑。绝缘层106和导电柱110由模制化合物112包覆。
图5A说明根据本发明的一些实施例的半导体装置封装10中的接垫104的布局。图5A的布局类似于图4A的布局。绝缘层106形成于载体100上。绝缘层106界定开口。接垫104形成于载体10上以及额外通孔118上(图5B中所示)。接垫104和开口形成同心圆。
图5B是根据本发明的一些实施例的半导体装置封装10的横截面视图。图5B的结构类似于图4B的结构。额外通孔118形成于载体100中。额外通孔118电连接到接垫104、互连层108和导电柱110。
图6A描绘根据本发明的一些实施例的半导体装置封装10中的导电柱110的布局。接垫104部分地被绝缘层106覆盖。由绝缘层106界定的开口具有环形形状，且暴露接垫104的一部分。互连层108形成于所述开口中。互连层108安置于接垫104上。导电柱110安置于绝缘层106上和互连层108上，且大体上由绝缘层106支撑。包围接垫104、绝缘层106、互连层108和导电柱110的空间可由模制化合物112填充。在一些实施例中，导电柱110的大小可在大约180μm到大约220μm的范围内。举例来说，导电柱110的大小为大约200μm。
图6B描绘根据本发明的一些实施例的半导体装置封装10中的导电柱110的布局。接垫104部分地被绝缘层106覆盖。两个单独的开口由绝缘层106界定，且使接垫104暴露。在一些实施例中，所述开口可大体上为梯形形状。在一些实施例中所述开口可大体上为多边形形状。在一些实施例中，所述开口可具有由在第一方向(例如如图6B中示出的水平方向)上延伸的第一直线和面对所述第一直线并在第一方向上延伸超出所述第一直线的凸弧界定的形状，且所述弧的每一端可分别通过第二直线和第三直线连接到第一直线的相应端。两个互连层108分别形成于所述开口中。导电柱110安置于绝缘层106上和互连层108上，且大体上由绝缘层106支撑。包围接垫104、绝缘层106、互连层108和导电柱110的空间可由模制化合物112填充。在一些实施例中，导电柱110为圆柱形，且导电柱110的直径可在大约180μm到大约220μm的范围内。举例来说，导电柱110的直径为大约200μm。在一些实施例中，所述开口中的至少一者的外部弯曲边缘与同一平面内的导电柱110的外部边缘之间的径向距离可在大约40μm到大约60μm的范围内。举例来说，径向距离为大约50μm。
图6C描绘根据本发明的一些实施例的半导体装置封装10中的导电柱110的布局。接垫104部分地被绝缘层106覆盖。由绝缘层106界定的使接垫104暴露的开口具有不完整的环形形状。举例来说，开口可大体上为三个环形扇区的形状，所述环形扇区一体连接在包含所述扇区空心圆的假想圆的中心部分，如图6C中示出。互连层108形成于所述开口中。导电柱110安置于绝缘层106上和互连层108上，且大体上由绝缘层106支撑。包围接垫104、绝缘层106、互连层108和导电柱110的空间可由模制化合物112填充。举例来说，互连层108大致形成于所述开口的中心。在一些实施例中，导电柱110为圆柱形，且导电柱110的直径可在大约180μm到大约220μm的范围内。举例来说，导电柱110的直径为大约200μm。在一些实施例中，所述开口中的至少一者的外部弯曲边缘与同一平面内的导电柱110的外部边缘之间的径向距离可在大约40μm到大约60μm的范围内。举例来说，径向距离为大约50μm。
图6D描绘根据本发明的一些实施例的半导体装置封装10中的导电柱110的布局。所描绘的布局类似于图6C中描绘的布局，除了由绝缘层106界定的开口为大体上X形。
图6E描绘根据本发明的一些实施例的半导体装置封装10中的导电柱110的布局。所描绘的布局类似于图6D中描绘的布局，除了由绝缘层106界定的开口为大体上Y形。
图6F描绘根据本发明的一些实施例的半导体装置封装10中的导电柱110的布局。所描绘的布局类似于图6A中描绘的布局，除了由绝缘层106界定的开口为大体上矩形形状。在一些实施例中，所述开口的短边缘与同一平面内的导电柱110的外部边缘之间的距离可在大约40μm到大约60μm的范围内。举例来说，径向距离为大约50μm。
图6G描绘根据本发明的一些实施例的半导体装置封装10中的导电柱110的布局。所描绘的布局类似于图6A中描绘的布局，除了由绝缘层106界定的开口为大体上三角形形状。在一些实施例中，三角形开口的一个拐点与同一平面内的导电柱110的外部边缘之间的距离可在大约40μm到大约60μm的范围内。举例来说，径向距离为大约50μm。
图7A是根据本发明的一些实施例的半导体装置封装31的横截面图。半导体装置封装31包含载体300和300'、接垫304、绝缘层306、互连层308、导电柱310、模制化合物312、焊料球314、封装316和316'，以及裝置318和320。导电柱310安置于绝缘层306上以及互连层308上。绝缘层306的顶部表面与互连层308的顶部表面大体上共面。封装316和316'各自经由相应额焊料球314安置于载体300的前侧(图7A中的顶部侧)。模制化合物312包覆接垫304、绝缘层306、导电柱310，以及封装316和316'。装置318安置于载体300的背侧(图7A中的底部侧)。导电柱安置于载体300和300'之间。装置320安置于载体300'的前侧(图7A中的顶部侧)。
载体300可与载体300'相同或类似于载体300'。载体300可不同于载体300'。载体300可为和/或可包含(例如)印刷电路板，例如基于纸的铜箔层压体、复合铜箔层压体，或聚合物浸染的基于玻璃纤维的铜箔层压体。载体300可包含互连结构，例如RDL或接地元件。在一些实施例中，接地元件是从载体300的侧表面暴露的通孔。在一些实施例中，接地元件是从载体300的侧表面暴露的金属层。在一些实施例中，接地元件是从载体300的侧表面暴露的金属迹线。
在一些实施例中，封装316可为倒装封装(例如适合于倒装芯片组合件)。封装316'可为电线绑定的封装。装置318可为无源装置。装置320可为有源装置。在一些实施例中，封装316和316'以及裝置318和320可根据半导体装置封装的不同设计，安置于载体300和300'的不同位置上。其它组合和/或配置中的其它类型的封装和/或裝置也是可能的。
图7B是根据本发明的一些实施例的半导体装置封装32的横截面视图。半导体装置封装32的结构类似于半导体装置封装31的结构。半导体装置封装32与半导体装置封装31之间的不同在于在半导体装置封装32中，存在安置于载体300和300'之间的下填树脂。
图7C是根据本发明的一些实施例的半导体装置封装33的横截面视图。半导体装置封装33的结构类似于半导体装置封装31的结构。半导体装置封装33与半导体装置封装31之间的不同在于在半导体装置封装33中，存在安置于载体300和300'之间的进一步模制化合物，且额外焊料球安置于载体300'的背侧。进一步模制化合物安置于载体300'的前侧，且包覆载体300、接垫304、绝缘层306、导电柱310、焊料球314、封装316和316'，以及裝置318和320。
图7D是根据本发明的一些实施例的半导体装置封装34的横截面视图。半导体装置封装34的结构类似于半导体装置封装33的结构。半导体装置封装34与半导体装置封装33之间的不同在于在半导体装置封装34中，至少一个额外无源装置和/或至少一个额外有源装置安置于载体300'的背侧。
图7E是根据本发明的一些实施例的半导体装置封装35的横截面视图。半导体装置封装35的结构类似于半导体装置封装34的结构。半导体装置封装35与半导体装置封装34之间的不同在于在半导体装置封装35中，互连元件322将载体300电连接到载体300'。
图8A、图8B、图8C、图8D、图8E、图8F和图8G说明根据本发明的一些实施例的制造半导体装置封装的方法。
参看图8A，一种用于制造半导体装置封装的方法包含提供载体300。载体300具有前侧(图8A中的顶部侧)和背侧(图8A中的底部侧)。前侧与背侧相对。接垫304安置于载体300的前侧。绝缘层306安置于载体300的前侧，且可部分地覆盖接垫304。绝缘层306可界定使接垫304暴露的一或多个开口。
参看图8B，导电柱310安置于绝缘层306上和互连层308上。在一些实施例中，互连层308安置于接垫304上，且导电柱310随后安置于互连层308上。在另一实施例中，互连层308附接到导电柱310，且附接有互连层308的导电柱310随后安置于接垫304上。
参看图8C，一或多个焊料球314安置于接垫304上。封装316和316'通孔焊料球314安置于载体300的前侧。在一些实施例中，封装316和316'可为相同种类的封装。在一些实施例中，封装316和316'可为不同种类的封装。
参看图8D，将模制化合物312施加在载体300的前侧。模制化合物312包覆接垫304、绝缘层306、导电柱310，以及封装316和316'。
参看图8E，研磨模制化合物312，以使导电柱310的顶部表面暴露。
参看图8F，额外导电柱安置于载体300的背侧。装置318安置于载体300的背侧。
参看图8G，装置320安置于载体300的背侧。
图9A、图9B、图9C、图9D、图9E和图9F说明根据本发明的一些实施例的制造半导体装置封装的方法。图9A、图9B、图9C、图9D、图9E和图9F中描绘的步骤可但无需在图8A、图8B、图8C、图8D、图8E、图8F和图8G中描绘的步骤之后执行。
参看图9A，一种用于制造半导体装置封装的方法包括提供载体300'。载体300'具有前侧(图9A中的顶部侧)和背侧(图9A中的底部侧)。前侧与背侧相对。接垫304安置于载体300'的前侧。绝缘层306安置于载体300'的前侧，且可部分地覆盖接垫304。装置318安置于载体300'的前侧。
参看图9B，装置320安置于载体300'的前侧。
参看图9C，如图8G中所示的结构安置于载体300'的前侧。
参看图9D，将额外模制化合物312施加在载体300'的前侧。额外模制化合物312包覆载体300、接垫304、绝缘层306、导电柱310、焊料球314、封装316和316'，以及裝置318和320。
参看图9E，研磨所述额外模制化合物312，以使导电柱310的顶部表面暴露。
参看图9F，一或多个额外焊料球安置于载体300'的背侧。
图10A、图10B、图10C、图10D和图10E说明根据本发明的一些实施例的制造半导体装置封装的方法。图10A、图10B、图10C、图10D和图10E中描绘的步骤可但无需在图9A、图9B、图9C、图9D、图9E和图9F中描绘的步骤之后执行。
参看图10A，提供如图9E中所示的结构。额外装置318安置于载体300'的背侧。
参看图10B，额外装置320安置于载体300'的背侧。
参看图10C，一或多个额外焊料球314安置于载体300'的背侧。
参看图10D，执行单一化操作来产生单独的半导体装置封装。
参看图10E，互连元件322的一端安置于模制化合物312的顶部表面上，且接触导电柱310，且互连元件322的另一端安置于载体300'的背侧。互连元件322将载体300电连接到载体300'。
本发明举例描述实现封装尺寸的减小，包含成品半导体封装的厚度的减小的通孔结构和相关联制造技术的实施例。
倒装芯片接合技术得益于较厚的裸片以避免裸片断裂。举例来说，可能要求裸片厚度在研磨之后大于4毫米(mm)，以避免倒装芯片接合期间的断裂。
因此，在其中总封装厚度是关注点的一些结构中，可实施直接裸片结合技术并非倒装芯片接合，其可实现具有约2mm的裸片厚度的令人满意的制造产量。
此外，可能希望致力于减小衬底的厚度，以实现总封装厚度的进一步减小。
根据本发明的实施方案，用减小厚度衬底来实施直接裸片接合技术和凸块技术，以实现总封装厚度的减小。直接裸片接合技术和凸块技术适合于单裸片封装或适合于多(例如堆叠)裸片封装。根据本发明的实施方案，已为具有三个堆叠裸片的封装实现了小于约0.4mm的总封装厚度。
图11说明根据本发明的实施例的半导体封装。在图11中，直接裸片接合技术和凸块技术为具有三个堆叠裸片的封装实现小于约0.4mm的总封装厚度。
图12A说明根据本发明的实施方案的半导体封装技术。如图12A中所示，首先提供虚设晶片，且裸片在单元面积内接合到所述虚设晶片上(其将在后续步骤分成个别单元)。
仍参看图12A，支柱安置于所述裸片上，或所述裸片在裸片接合之前具备支柱。额外裸片是接合到所述接合到虚设晶片的裸片的裸片，且额外支柱安置于所述额外裸片上。如所说明，三个裸片以堆叠方式彼此接合，其中支柱从所述裸片垂直延伸(在示出的定向上)。多于三个或少于三个裸片可通过裸片接合来堆叠。在所述裸片已堆叠之后，在晶片周围构造模具，且在所述模具内部填充封裝材料。举例来说，可在所述模具内填充液体化合物，以填充在经堆叠裸片周围，且向下到虚设晶片。
去除所述模具，且研磨所述封裝材料(在固化之后)，以使封裝材料的表面处的支柱暴露。
例如聚酰亚胺的绝缘层安置于封裝材料的表面之上。绝缘层界定开口，其中的每一者使相应支柱暴露。接着，再分布层(RDL)安置于所述绝缘层之上且安置到所述开口中，从而与所述支柱电接触。例如聚酰亚胺的另一绝缘层安置于RDL之上。
图12B说明下一制造步骤。焊料球安置于RDL上。焊料球可位于支柱之上，或定位成从支柱偏移。因此，焊料球之间的间距可大于支柱之间的间距。
如图12B中所示，在安置所述焊料球之后，研磨虚设晶片。在一些实施例中，可将虚设晶片完全研磨掉，从而留下所述裸片堆叠的最顶部裸片暴露。
图12C说明其中将单元面积单一化以分开个别半导体封装的下一制造步骤(在图12C中示出为“完成”)，且如图11中所示。如图12中所示，成品半导体封装的总厚度为约398微米(μm)。
图12C中的成品半导体封装的总厚度包含约175μm的焊料球高度、约28μm的RDL高度，以及约195μm的封裝材料高度。所述支柱中的最长支柱的高度(在示出定向中垂直)为约145μm，中间支柱为约85μm，且所述支柱中的最短支柱为约25μm。所述裸片中的每一者的厚度为约10μm，绝缘层各自的厚度为约9μm，且RDL的厚度为约5μm，三个裸片的总堆叠裸片高度为约50-60μm。
所述支柱可为或可包含铜。在一或多个实施例中，将所述支柱中的一或多者电镀到相应裸片上。在一或多个实施例中，所述支柱中的一或多者引脚安裝到相应裸片。所述支柱可具有类似直径，或所述支柱中的支柱可具有不同直径。
图13A说明根据本发明的实施方案的半导体封装技术。如图13A中所示，首先提供虚设载体，且裸片在单元面积内接合到所述载体上(其将在后续步骤分成个别单元)。
仍参看图13A，支柱安置于所述裸片上，或所述裸片在裸片接合之前具备支柱。额外裸片是接合到所述接合到所述载体的裸片的裸片，且额外支柱安置于所述额外裸片上。如所说明，三个裸片以堆叠方式彼此接合，其中支柱从所述裸片垂直延伸(在示出的定向上)。多于三个或少于三个裸片可通过裸片接合来堆叠。在所述裸片已堆叠之后，在晶片周围构造模具，且在所述模具内部填充封裝材料。举例来说，可在所述模具内填充液体化合物，以填充在经堆叠裸片周围，且向下到载体。
去除所述模具，且研磨所述封裝材料(在固化之后)，以使封裝材料的表面处的支柱暴露。
例如聚酰亚胺的绝缘层安置于封裝材料的表面之上。绝缘层界定开口，其中的每一者使相应支柱暴露。接着，再分布层(RDL)安置于所述绝缘层之上且安置到所述开口中，从而与所述支柱电接触。例如聚酰亚胺的另一绝缘层安置于RDL之上。
图13B说明下一制造步骤。焊料球安置于RDL上。焊料球可位于支柱之上，或定位成从支柱偏移。因此，焊料球之间的间距可大于支柱之间的间距。
如图13B中所示，在安置所述焊料球之后，去除载体。
图13C说明其中将单元面积单一化以分开个别半导体封装的下一制造步骤(在图13C中示出为“完成”)，且如图11中所说明。如图13C中所示，成品半导体封装的总厚度为约398μm。
图13C中的成品半导体封装的总厚度包含约175μm的焊料球高度、约28μm的RDL高度，以及约195μm的封裝材料高度。所述支柱中的最长支柱的高度(在示出定向中垂直)为约145μm，中间支柱为约85μm，且所述支柱中的最短支柱为约25μm。所述裸片中的每一者的厚度为约10μm，绝缘层各自的厚度为约9μm，且RDL的厚度为约5μm，三个裸片的总堆叠裸片高度为约50-60μm。
所述支柱可为或可包含铜。在一或多个实施例中，将所述支柱中的一或多者电镀到相应裸片上。在一或多个实施例中，所述支柱中的一或多者引脚安裝到相应裸片。所述支柱可具有类似直径，或所述支柱中的支柱可具有不同直径。
图14说明根据本发明的实施例的半导体封装。
图15A说明根据本发明的实施方案的半导体封装技术。如图15A中所示，首先提供虚设晶片，且在单元面积(其将在后续步骤分成若干个别单元)内将裸片结合到虚设晶片上。
仍参看图15A，支柱安置于所述裸片上，或所述裸片在裸片接合之前具备支柱。额外裸片是接合到所述接合到虚设晶片的裸片的裸片，且额外支柱安置于所述额外裸片上。如所说明，三个裸片以堆叠方式彼此接合，其中支柱从所述裸片垂直延伸(在示出的定向上)。多于三个或少于三个裸片可通过裸片接合来堆叠。在所述裸片已堆叠之后，在晶片周围构造模具，且在所述模具内部填充封裝材料。举例来说，可在所述模具内填充液体化合物，以填充在经堆叠裸片周围，且向下到虚设晶片。
去除所述模具，且研磨所述封裝材料(在固化之后)，以使封裝材料的表面处的支柱暴露。
焊膏安置于暴露的支柱上，例如通过焊膏印刷技术。
如图15中所示，在安置所述焊膏之后，研磨虚拟晶片。在一或多个实施例中，将虚设晶片完全研磨掉，从而留下裸片堆叠的最顶部裸片暴露。
图15B说明下一制造步骤，其中将单元面积单一化，以分开个别的半导体封装单元。在图15B中，举例来说，将个别半导体封装单元标记为“存储器立方体”，但所描述的技术不限于存储器。
图15C说明下一制造步骤，其中个别半导体封装单元中的一或多者倒装芯片接合到载体(例如具有RDL的衬底)，底填充料施加在半导体封装单元与所述载体之间。
图15D说明下一制造步骤，其中半导体封装单元以及载体的表面由封裝材料(例如由模制材料)包覆，且施加焊料球。随后，如果适用，那么可将载体和封裝材料单一化为个别裝置，例如图14中所示的半导体封装。
图16A说明根据本发明的实施方案的半导体封装技术。如图16A中所示，首先提供虚设载体，且裸片在单元面积内接合到所述载体上(其将在后续步骤分成个别单元)。
仍参看16A，支柱安置于所述裸片上，或所述裸片在裸片接合之前具备支柱。额外裸片是接合到所述接合到所述载体的裸片的裸片，且额外支柱安置于所述额外裸片上。如所说明，三个裸片以堆叠方式彼此接合，其中支柱从所述裸片垂直延伸(在示出的定向上)。多于三个或少于三个裸片可通过裸片接合来堆叠。在所述裸片已堆叠之后，在晶片周围构造模具，且在所述模具内部填充封裝材料。举例来说，可在所述模具内填充液体化合物，以填充在经堆叠裸片周围，且向下到载体。
在所述裸片已堆叠之后，在晶片周围构造模具，且在所述模具内部填充封裝材料。举例来说，可在所述模具内填充液体化合物，以填充在经堆叠裸片周围，且向下到虚设晶片。
去除所述模具，且研磨所述封裝材料(在固化之后)，以使封裝材料的表面处的支柱暴露。
焊膏安置于暴露的支柱上，例如通过焊膏印刷技术。如图16A中所示，在安置所述焊膏之后，去除载体。
图16B说明下一制造步骤，其中将单元面积单一化，以分开个别的半导体封装单元。在图16B中，举例来说，将个别半导体封装单元标记为“存储器立方体”，但所描述的技术不限于存储器。
图16C说明下一制造步骤，其中个别半导体封装单元中的一或多者倒装芯片接合到载体(例如具有RDL的衬底)，底填充料施加在半导体封装单元与所述载体之间。
图16D说明下一制造步骤，其中半导体封装单元以及载体的表面由封裝材料(例如由模制材料)包覆，且施加焊料球。随后，如果适用，那么可将载体和封裝材料单一化为个别裝置，例如图14中所示的半导体封装。
如本文中所使用且不另外定义，术语“基本上”、“实质上”、“大致”和“约”是用于描述并考虑较小变化。当与事件或情形结合使用时，所述术语可包含事件或情形明确发生的情况以及事件或情形极近似于发生的情况。举例来说，当结合数值使用时，术语可包含小于或等于所述数值的±10％的变化范围，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％、或小于或等于±0.05％。术语“大体上共面”可指两个表面在数微米内处于沿同一平面，例如在40μm内、30μm内、20μm内、10μm内或1μm内处于沿同一平面。
如本文所用，除非上下文另外明确规定，否则单数术语“一(a/an)”和“所述(the)”包括多个参考物。在一些实施例的描述中，提供于另一组件“上”或“之上”的组件可涵盖前者组件直接在后者组件上(例如，与后者组件物理接触)上的情况，以及一或多个介入组件位于前者组件与后者组件之间的情况。
虽然已参考本发明的特定实施例描述和说明本发明，但这些描述和说明并非限制性的。所属领域的技术人员应理解，可在不脱离如由所附权利要求书界定的本发明的真实精神和范围的情况下，作出各种改变且取代等效物。所述说明可能未必按比例绘制。归因于制造工艺和容差，本发明中的艺术再现与实际设备之间可存在区别。可存在并未特定说明的本发明的其它实施例。应将本说明书和图式视为说明性的而非限制性的。可做出修改，以使具体情况、材料、物质组成、方法或工艺适应于本发明的目标、精神和范围。所有所述修改都既定在所附权利要求书的范围内。虽然本文中所揭示的方法已参考按特定次序执行的特定操作加以描述，但应理解，可在不脱离本发明的教示的情况下组合、细分或重新排序这些操作以形成等效方法。因此，除非在本文中具体指示，否则操作的次序和分组并非限制。

Claims (18)

1.一种半导体封装，其包括：
衬底；
第一绝缘层，其安置于所述衬底上，所述第一绝缘层包括开口；
接垫，其安置于所述衬底上且从所述开口暴露；
互连层，其安置于所述接垫上；以及
预先形成的导电柱，其包括底部表面，所述底部表面具有安置于所述互连层上的第一部分以及安置于所述第一绝缘层上且接触所述第一绝缘层的第二部分。
2.根据权利要求1所述的半导体封装，其中所述第一部分接触所述互连层，且所述第二部分接触所述第一绝缘层。
3.根据权利要求1所述的半导体封装，其中所述互连层的外侧部分与所述第一绝缘层接触。
4.根据权利要求1所述的半导体封装，其进一步包括至少一个无源装置和至少一个有源装置，其中所述衬底包括顶部侧以及底部侧，所述预先形成的导电柱、至少一个无源装置和至少一个有源装置安置于所述衬底的底部侧。
5.根据权利要求4所述的半导体封装，其进一步包括第二绝缘层，其包覆所述预先形成的导电柱、至少一个无源装置、至少一个有源装置以及所述衬底的底部侧。
6.根据权利要求5所述的半导体封装，其进一步包括裝置及模制化合物，其中所述裝置安置于衬底的顶部侧，所述模制化合物安置于衬底的顶部侧且包覆所述裝置。
7.根据权利要求4所述的半导体封装，其进一步包括封装、模制化合物、预先形成的导电柱及绝缘层分別安置于所述衬底的顶部侧，其中所述模制化合物包覆所述封装、所述预先形成的导电柱及所述绝缘层，所述预先形成的导电柱接触所述绝缘层。
8.根据权利要求7所述的半导体封装，其进一步包括载体及装置，其中所述载体包括前侧及背侧，所述装置安置于所述载体的前侧，所述衬底的底部侧的预先形成的导电柱安置于所述载体的前侧。
9.根据权利要求8所述的半导体封装，其进一步包括额外模制化合物安置于所述载体的前侧，其中所述额外模制化合物包覆所述载体、所述绝缘层、所述预先形成的导电柱、所述装置、所述封装及所述模制化合物。
10.根据权利要求9所述的半导体封装，其进一步包括焊料球安置于所述载体的背侧。
11.根据权利要求10所述的半导体封装，其进一步包括额外装置安置于所述载体的背侧。
12.根据权利要求10所述的半导体封装，其进一步包括互连元件一端安置于模制化合物的顶部表面上，且接触预先形成的导电柱，且互连元件的另一端安置于载体的背侧，所述互连元件将所述载体电连接到所述衬底。
13.根据权利要求5所述的半导体封装，其中所述第二绝缘层安置于所述接垫上且包覆所述互连层。
14.根据权利要求13所述的半导体封装，其中所述互连层与所述第一绝缘层通过所述第二绝缘层间隔开。
15.一种半导体封装，其包括：
衬底；
第一绝缘层，其安置于所述衬底上，所述第一绝缘层包括开口；
接垫，其安置于所述衬底上且从所述开口暴露；
互连层，其安置于所述接垫上；以及
导电柱，其包括底部表面，所述底部表面具有安置于所述互连层上的第一部分以及安置于所述第一绝缘层上且接触所述第一绝缘层的第二部分，
其中所述互连层的部分的顶部表面从所述导电柱暴露且所述部分与所述第一绝缘层接触。
16.一种半导体封装，其包括：
衬底；
第一绝缘层，其安置于所述衬底上，所述第一绝缘层包括开口；
接垫，其安置于所述衬底上且从所述开口暴露；
互连层，其安置于所述接垫上；
第二绝缘层，其安置于所述接垫上并与所述接垫接触，且所述第二绝缘层包覆所述互连层；以及
导电柱，其安置于所述互连层上以及所述第二绝缘层上。
17.根据权利要求16所述的半导体封装，其中所述导电柱具有包含第一部分和第二部分的底部表面，且所述第一部分接触所述互连层的顶部表面，且所述第二部分接触所述第一绝缘层。
18.根据权利要求16所述的半导体封装，其中所述第二绝缘层包覆所述第一绝缘层和所述导电柱。
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CN104253058A (zh) * 2013-06-28 2014-12-31 新科金朋有限公司 在扇出型wlcsp上堆叠半导体小片的方法及半导体装置

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