CN114005799A - 半导体封装及用于制造半导体封装的方法 - Google Patents

半导体封装及用于制造半导体封装的方法 Download PDF

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CN114005799A
CN114005799A CN202111292890.4A CN202111292890A CN114005799A CN 114005799 A CN114005799 A CN 114005799A CN 202111292890 A CN202111292890 A CN 202111292890A CN 114005799 A CN114005799 A CN 114005799A
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package
bump
semiconductor
circuit
pillar
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博恩·卡尔·艾皮特
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

本申请实施例涉及半导体封装及用于制造半导体封装的方法。本发明揭示一种半导体封装，其包含至少一个半导体元件、封装体、第一电路、第二电路及至少一个第一柱状凸块。所述封装体覆盖所述半导体元件的至少一部分。所述封装体具有第一表面以及与所述第一表面相对的第二表面。所述第一电路安置成邻近于所述封装体的所述第一表面。所述第二电路安置成邻近于所述封装体的所述第二表面。所述第一柱状凸块安置在所述封装体中，且电连接所述第一电路及所述第二电路。所述第一柱状凸块直接接触所述第二电路。

Description

半导体封装及用于制造半导体封装的方法
分案申请的相关信息
本申请是申请日为2017年9月12日，申请号为“201710815735.3”，发明名称为“半导体封装及用于制造半导体封装的方法”的发明专利申请的分案申请。
技术领域
本发明涉及一种半导体封装及一种半导体工艺，且更特定来说，涉及一种包含安置在封装体(encapsulant)中的至少一个柱状凸块(stud bump)的半导体封装以及一种用于制造所述半导体封装的半导体工艺。
背景技术
在一些半导体封装中，顶部电路及/或底部电路可安置在封装体外部。延伸穿过封装体的导电通道(conductive vias)将顶部电路及/或底部电路电连接到封装体内部的电子组件。导电通道可通过对封装体进行钻孔并在所钻孔洞中电镀金属材料来形成。然而，此些技术增加制造工艺的困难及成本。
发明内容
在根据一些实施例的一个方面中，半导体封装包含至少一个半导体元件、封装体、第一电路、第二电路以及至少一个第一柱状凸块。所述封装体覆盖所述半导体元件的至少一部分。所述封装体具有第一表面以及与所述第一表面相对的第二表面。所述第一电路安置成邻近于所述封装体的所述第一表面。所述第二电路安置成邻近于所述封装体的第二表面。所述第一柱状凸块安置在所述封装体中，且电连接所述第一电路及所述第二电路。所述第一柱状凸块直接接触所述第二电路。
在根据一些实施例的另一方面中，半导体封装包含至少一个半导体元件、封装体、第一电路及第二电路。所述封装体覆盖所述半导体元件的至少一部分。所述封装体具有第一表面以及与所述第一表面相对的第二表面。所述第一电路安置成邻近于所述封装体的所述第一表面。所述第二电路安置成邻近于所述封装体的所述第二表面，且电连接到所述第一电路。所述第二电路包含由金属板形成的基层(base layer)。
在根据一些实施例的另一方面中，用于制造半导体封装的方法，包括：(a)将金属板安置在载体上；(b)将至少一个半导体元件附接到所述金属板；(c)在所述金属板上形成至少一个第一柱状凸块；(d)形成封装体以覆盖所述半导体元件及所述第一柱状凸块的至少一部分；(e)将所述载体去除；以及(f)图案化所述金属板的至少一部分。
附图说明
当与附图一起阅读时，可从以下详述描述最佳理解本发明的一些实施例的方面。应注意，各种结构可能并未按比例绘制，且为论述的清晰性可任意增加或减小各种结构的尺寸。
图1描绘根据本发明的一些实施例的半导体封装的实例的截面图。
图2描绘根据本发明的一些实施例的半导体封装的实例的截面图。
图3描绘根据本发明的一些实施例的半导体封装的实例的截面图。
图4描绘根据本发明的一些实施例的半导体封装的实例的截面图。
图5描绘根据本发明的一些实施例的半导体封装的实例的截面图。
图6描绘根据本发明的一些实施例的半导体封装的实例的截面图。
图7描绘根据本发明的一些实施例的半导体封装的实例的截面图。
图8描绘根据本发明的一些实施例的半导体封装的实例的截面图。
图9描绘根据本发明的一些实施例的半导体封装的实例的截面图。
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图11描绘根据本发明的一些实施例的半导体封装的实例的截面图。
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图16描绘根据本发明的一些实施例的半导体封装的实例的截面图。
图17描绘根据本发明的一些实施例的半导体封装的实例的截面图。
图18描绘根据本发明的一些实施例的半导体封装的实例的截面图。
图19描绘根据本发明的一些实施例的半导体封装的实例的截面图。
图20描绘根据本发明的一些实施例的半导体封装的实例的截面图。
图21描绘根据本发明的一些实施例的半导体封装的实例的截面图。
图22描绘根据本发明的一些实施例的半导体封装的实例的截面图。
图23描绘根据本发明的一些实施例的半导体封装的实例的截面图。
图24描绘根据本发明的一些实施例的半导体封装的实例的截面图。
图25描绘根据本发明的一些实施例的半导体封装的实例的截面图。
图26描绘根据本发明的一些实施例的半导体封装的实例的截面图。
图27描绘根据本发明的一些实施例的半导体封装的实例的截面图。
图28描绘图1的半导体封装的第一电路的部分的实例的俯视图。
图29描绘图1的半导体封装的第一电路的部分的实例的俯视图。
图30A描绘图1的半导体封装的第一电路的部分的实例的俯视图。
图30B描绘图1的半导体封装的第一电路的部分的实例的俯视图。
图31描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的一或多个阶段处的实例性半导体封装的截面图。
图32描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的一或多个阶段处的实例性半导体封装的截面图。
图33描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的一或多个阶段处的实例性半导体封装的截面图。
图33A描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的一或多个阶段处的实例性半导体封装的截面图。
图34描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的一或多个阶段处的实例性半导体封装的截面图。
图35描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的一或多个阶段处的实例性半导体封装的截面图。
图36描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的一或多个阶段处的实例性半导体封装的截面图。
图37描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的一或多个阶段处的实例性半导体封装的截面图。
图38描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的一或多个阶段处的实例性半导体封装的截面图。
图39描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的一或多个阶段处的实例性半导体封装的截面图。
图40描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的一或多个阶段处的实例性半导体封装的截面图。
图41描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的一或多个阶段处的实例性半导体封装的截面图。
图42描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的一或多个阶段处的实例性半导体封装的截面图。
图43描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的一或多个阶段处的实例性半导体封装的截面图。
图44描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的一或多个阶段处的实例性半导体封装的截面图。
图45描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的一或多个阶段处的实例性半导体封装的截面图。
图46描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的一或多个阶段处的实例性半导体封装的截面图。
图47描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的一或多个阶段处的实例性半导体封装的截面图。
图48描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的一或多个阶段处的实例性半导体封装的截面图。
图49描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的一或多个阶段处的实例性半导体封装的截面图。
图50描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的一或多个阶段处的实例性半导体封装的截面图。
图51描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的一或多个阶段处的实例性半导体封装的截面图。
图51A描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的一或多个阶段处的实例性半导体封装的截面图。
图52描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的一或多个阶段处的实例性半导体封装的截面图。
图53描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的一或多个阶段处的实例性半导体封装的截面图。
图54描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的一或多个阶段处的实例性半导体封装的截面图。
图55描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的一或多个阶段处的实例性半导体封装的截面图。
图56描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的一或多个阶段处的实例性半导体封装的截面图。
图57描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的一或多个阶段处的实例性半导体封装的截面图。
图58描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的一或多个阶段处的实例性半导体封装的截面图。
图59描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的一或多个阶段处的实例性半导体封装的截面图。
图60描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的一或多个阶段处的实例性半导体封装的截面图。
图61描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的一或多个阶段处的实例性半导体封装的截面图。
图62描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的一或多个阶段处的实例性半导体封装的截面图。
贯穿图式及详细描述使用共用参考编号来指示相同或类似组件。从结合附图进行的以下详细描述将更佳地理解本发明。
具体实施方式
在包含半导体裸片及/或一或多个电子组件(例如，无源组件)的半导体封装中，可形成封装体以覆盖半导体裸片及/或电子组件。顶部电路可形成在封装体的顶部表面上。顶部电路通过多个第一导电互连件(conductive interconnectors)电连接到半导体裸片及/或电子组件以便形成扇出型晶片级封装(fan-out wafer level package)。为了增加多个外部连接(external connections)，底部电路可形成在封装体的底部表面上。底部电路通过多个第二导电互连件电连接到顶部电路。第一导电互连件及/或第二导电互连件可为导电通道(例如，柱类型的通道(vias of pillar type))。导电通道可通过对封装体进行钻孔以形成延伸穿过封装体的多个通孔且接着在通孔中电镀金属材料来形成。然而，用于形成导电通道的此些技术增加制造工艺的困难及成本。此外，顶部电路及/或底部电路可通过在封装体的表面上形成晶种层，将金属层图案电镀(pattern-plating)于晶种层上以及快速蚀刻(flash-etching)晶种层来形成。应注意，此些技术也增加制造工艺的困难及成本。因此，期望研发解决上述问题的半导体封装及半导体工艺。
本发明中描述包含作为导电互连件的一或多个柱状凸块的半导体封装。在一些实施例中，半导体封装的封装体的顶部表面上的顶部电路通过多个第一柱状凸块电连接到封装体内部的半导体裸片及/或一或多个电子组件以便形成扇出型晶片级封装。封装体的底部表面上的底部电路通过多个第二柱状凸块电连接到顶部电路。第一柱状凸块及/或第二柱状凸块可通过例如线接合设备(wire bonding apparatus)形成。因此，减少制造工艺的困难及成本。另外，顶部电路及/或底部电路可通过图案化金属板来形成，在制造工艺的初始阶段将半导体裸片及/或电子组件及封装体安置在金属板上。即，在初始阶段提供的金属板在制造工艺的稍后阶段期间可能未被完全去除，且金属板的至少一部分可能仍存在成品中。换句话说，顶部电路及/或底部电路可包含经图案化金属板的至少一部分。因此，进一步减少制造工艺的困难及成本。
图1描绘根据本发明的一些实施例的半导体封装1的实例的截面图。半导体封装1包含至少一个半导体元件2、封装体3、粘合剂层12、第一电路4、第二电路5、至少一个第一柱状凸块6、至少一个导电互连件(例如，第二柱状凸块7)、第一保护层82、第二保护层84以及至少一个外部连接器(external connector)(例如，焊料凸块86)。
半导体元件2可为例如半导体裸片或电子组件(例如，无源组件)。半导体元件2具有有源表面21、与有源表面21相对的背部表面22以及多个垫(pads)23。有源表面21依图1中所展示的定向面朝上。背部表面22可被粘合剂层12覆盖，且依图1中所展示的定向面朝下。垫23安置成邻近于半导体元件2的有源表面21。
封装体3覆盖(covers)或囊封(encapsulates)半导体元件2的至少一部分。如本文中所使用，覆盖对象或囊封对象的术语意指封围(enclosing)或环绕(surrounding)对象的至少一部分，例如覆盖对象的横向侧(lateral sides)中的至少全部或一些。封装体3的材料可包含模制化合物(molding compound)(例如含填料的环氧树脂(epoxy resin))、光致成像电介质(photo-imageable dielectric)(例如焊料掩模(solder mask)或其它合适的介电材料)或其组合。封装体3具有第一表面31以及与第一表面31相对的第二表面32。如图1中所展示，封装体3覆盖半导体元件2的有源表面21、半导体元件2的侧表面(lateralsurface)、第一柱状凸块6及导电互连件(例如，第二柱状凸块7)的至少一部分。因此，半导体元件2至少部分地嵌入在封装体3中。半导体元件2的厚度小于封装体3的厚度。在一个实施例中，半导体元件2的有源表面21面朝向封装体3的第一表面31。半导体元件2的背部表面22安置成邻近于封装体3的第二表面32。应注意，粘合剂层12的底部表面可与封装体3的第二表面32大致上共面。
第一电路4(例如，重布层(redistribution layer,RDL)；也被称作顶部电路)安置成邻近于封装体3的第一表面31。如图1中所展示，第一电路4安置于封装体3的第一表面31上并接触所述第一表面31。第一电路4安置在半导体元件2的有源表面21上方。因此，半导体元件2的有源表面21面向第一电路4。应注意，第一电路4可包含多个扇出型迹线(fan-outtraces)及/或通过例如电镀(plating)或喷墨印刷(ink jet printing)形成的多个凸块垫(bump pads)。在一个实施例中，第一电路4可通过将晶种层形成在封装体3的第一表面31上，将金属层图案电镀在晶种层上及快速蚀刻晶种层来形成。晶种层的材料可为或可包含例如钛铜(TiCu)，且电镀金属层的材料可为或包含例如Cu。
第二电路5(例如，重布层(RDL)，也被称作底部电路)安置成邻近于封装体3的第二表面32，且电连接到第一电路4。如图1中所展示，第二电路5安置在封装体3的第二表面32上并接触所述第二表面32。第二电路5安置在半导体元件2的背部表面22下方。因此，半导体元件2的背部表面22面向第二电路5。粘合剂层12可插置在半导体元件2的背部表面22与第二电路5之间。因此，至少在一些实施例中，半导体元件2的背部表面22可不与封装体3的第二表面32共面。
第二电路5可经配置以包含多个迹线及/或多个凸块垫。在一个实施例中，第二电路5可包含基层52及表面层54。表面层54安置在基层52上。因此，基层52插置在表面层54与封装体3的第二表面32之间。替代地，基层52可插置在表面层54与黏合剂层12之间。基层52可由金属板形成。在一个实施例中，第二电路5可通过以下步骤来形成：薄化金属板，将表面层54图案电镀在经薄化金属板上，及快速蚀刻薄金属板以变成基层52，以使得基层52经图案化且与表面层54共形。金属板可为或包含例如铜(Cu)箔。因此，基层52可为铜箔的部分。表面层54可为或包含例如电镀铜(plated Cu)或其它合适的材料。基层52的厚度可为例如约0.1μm到约200μm，约0.5μm到约200μm，约1μm到约100μm，或约1.5μm到约50μm。
第二电路5具有第一表面51(例如，基层52的顶部表面)，其接触封装体3的第二表面32及/或粘合剂层12的底部表面。第二电路5的第一表面51的表面粗糙度(Rz)可为例如约0.1μm到约10.0μm、约0.5μm到约5.0μm，或约1.0μm到约3.0μm。第二电路5的第一表面51的均匀度(uniformity)可小于例如约10％、约8％、约5％，或约3％。在一些实施例中，可基于表面的点而确定或测量均匀度。例如，表面的多个点(例如，5个点)可为随机选择。测量每一点处的层或薄膜的厚度(例如，第二电路5的厚度)。表面的均匀度可定义为例如最大厚度与最小厚度之间的差除以所选择点处的厚度值的平均数的两倍：
Figure BDA0003335278570000081
第二电路5的第一表面51的总厚度偏差(total thickness variation,TTV)可小于例如约20μm、约10μm，或约5μm。在一些实施例中，由于第二电路5的基层52是通过图案化金属板形成，第一表面51的表面状况(例如，Rz、均匀度及/或TTV)可不相依于(dependupon)封装体3的第二表面32的表面状况及/或粘合剂层12的底部表面。因此，第二电路5的基层52的表面状况(例如，Rz、均匀度及TTV)可优于电镀(plated)或溅镀(sputtered)电路的表面状况。
第一柱状凸块6安置在封装体3中。即，第一柱状凸块6的至少一部分被封装体3覆盖或囊封。第一柱状凸块6电连接第一电路4及第二电路5。第一柱状凸块6的材料可为或包含例如金、铜、银、涂铂铜(platinum coated copper)、其中两者或多于两者的组合，或另一金属或金属的组合。如图1中所展示，第一柱状凸块6直接接触第二电路5。在一个实施例中，第一柱状凸块6包含柱状部分(stud portion)62及凸块部分(bump portion)60，其中柱状部分62的宽度小于凸块部分60的宽度。应注意，柱状部分62可大致上呈柱状形状(pillarshape)，且凸块部分60可大致上呈盘形形状(disk shape)。柱状部分62及凸块部分60可通过线接合设备同时地且整体地形成。第一柱状凸块6的凸块部分60直接接触第二电路5。由于第二电路5的第一表面51具有合适的表面状况(例如，Rz、均匀度及TTV)，第一柱状凸块6的凸块部分60可牢固地附接到第二电路5的第一表面51。即，第一柱状凸块6的凸块部分60不容易从第二电路5的第一表面51剥离。相比之下，电镀或溅镀电路可能具有不合适表面状况，这是因为其表面状况可能相依于封装体3的第二表面32及/或粘合剂层12的底部表面的表面状况。因此，如果柱状凸块的凸块部分附接到电镀或溅镀电路的表面，那么柱状凸块的凸块部分可容易从电镀或溅镀电路的表面剥离。
柱状部分62包含第一端621及第二端622。柱状部分62的第二端622连接凸块部分60，且柱状部分62的第一端621接触第一电路4。如图1中所展示，第一柱状凸块6的柱状部分62的第一端621从封装体3的第一表面31突出。即，柱状部分62的第一端621延伸越过封装体3的第一表面31，且延伸到第一电路4且嵌入其中。柱状部分62的第一端621可被第一电路4环绕。在制造工艺中，凸块部分60可通过线接合设备的接合头(bonding head)形成在金属板(其稍后将变成基层52)上。接合头可进一步向上移动以形成柱状部分62。将柱状部分62的顶部部分切掉以形成第一端621。因此，形成导电通道的工艺(其可包含对封装体进行钻孔以形成延伸穿过封装体的多个通孔且接着电镀通孔中的金属材料)被线接合工艺(wirebonding process)替换。因此，减少制造工艺的困难及成本。
导电互连件(例如，第二柱状凸块7)电连接半导体元件2及第一电路4。如图1中所展示，导电互连件可为至少一个第二柱状凸块7。第二柱状凸块7的至少一部分安置在封装体3中。即，第二柱状凸块7的至少一部分被封装体3覆盖或囊封。第二柱状凸块7电连接半导体元件2的垫23及第一电路4。第二柱状凸块7的材料可为或包含例如金、铜、涂铂铜、银、其中两者或多于两者的组合或另一金属或金属的组合。在一个实施例中，第二柱状凸块7包含柱状部分72及凸块部分70，柱状部分72的宽度小于凸块部分70的宽度。应注意，柱状部分72可大致上呈柱状形状，且凸块部分70可大致上呈盘形形状。柱状部分72及凸块部分70可通过例如线接合设备同时地且整体地形成。
柱状部分72包含第一端721及第二端722。柱状部分72的第二端722连接凸块部分70，且柱状部分72的第一端721接触第一电路4。如图1中所展示，第二柱状凸块7的柱状部分72的第一端721从封装体3的第一表面31突出。即，柱状部分72的第一端721延伸越过封装体3的第一表面31，且延伸到第一电路4且嵌入其中。柱状部分72的第一端721可被第一电路4环绕。
在一些实施例中，如图1中所展示，第二柱状凸块7的柱状部分72及凸块部分70的宽度可分别小于第一柱状凸块6的柱状部分62及凸块部分60的宽度。然而，在其它实施例中，第二柱状凸块7的柱状部分72及凸块部分70的宽度可分别与第一柱状凸块6的柱状部分62及凸块部分60的宽度大致上相同或大于所述宽度。
在一些实施例中，如图1中所展示，第二柱状凸块7的柱状部分72可大致上垂直于半导体元件2的有源表面21。类似地，第一柱状凸块6的柱状部分62可大致上垂直于封装体3的第二表面32。然而，在一些其它实施例中，第二柱状凸块7的柱状部分72可不垂直于半导体元件2的有源表面21，或第一柱状凸块6的柱状部分62可不垂直于封装体3的第二表面32。应注意，半导体元件2、封装体3、粘合剂层12、第一电路4、第二电路5、第一柱状凸块6以及导电互连件(例如，第二柱状凸块7)可通过例如晶片级封装技术及其类似技术而形成。
第一保护层82(例如，焊料掩模或其它光致介电材料)覆盖第一电路4以及封装体3的第一表面31，且第一保护层82界定一或多个开口821，其暴露第一电路4的至少一部分以用于外部连接。外部连接器(例如，焊料凸块(solder bump)86)安置在第一电路4上的开口821中。开口821中的第一电路4的顶部表面可被例如镍金(NiAu)或OSP(有机焊料保护剂(organic solder preservative))覆盖以促进焊料湿润及形成焊料凸块86。第二保护层84(例如，焊料掩模)覆盖第二电路5、封装体3的第二表面32以及粘合剂层12。第二保护层84界定多个开口841，其暴露第二电路5的至少一部分以用于外部连接。开口841中的铜可由例如NiAu、钯(Pd)、镍钯金(NiPdAu)或OSP保护以促进外部连接。金属表面保护(metallicsurface protection)可通过例如电镀工艺(electroplating process)或无电极电镀工艺(electroless plating process)来形成。为简洁起见，图1中省略电路4及5上的保护涂层。
图2描绘根据本发明的一些实施例的半导体封装1a的实例的截面图。半导体封装1a类似于图1中所展示的半导体封装1，且类似特征经以相同方式编号且不关于图2进一步描述。在图2的半导体封装1a中，第一柱状凸块6的柱状部分62的第一端621及第二柱状凸块7的柱状部分72的第一端721不从封装体3的第一表面31突出。即，柱状部分62的第一端621以及柱状部分72的第一端721并未延伸越过封装体3的第一表面31。柱状部分62的第一端621的顶部表面以及柱状部分72的第一端721的顶部表面与封装体3的第一表面31大致上共面，且接触第一电路4的底部表面。
另外，在一些实施例中，图1的第二电路5的表面层54可被省略。因此，图2的第二电路5a可包含直接从金属板图案化而无需薄化阶段的基层52a。即，图2的第二电路5a可为具有整体结构的单层(a single layer with a monolithic structure)。图2的基层52a的厚度可大于图1的基层52的厚度。
图3描绘根据本发明的一些实施例的半导体封装1b的实例的截面图。半导体封装1b类似于图1中所展示的半导体封装1，且类似特征经以相同方式编号且不关于图3进一步描述。在图3的半导体封装1b中，图1的粘合剂层12可被省略。因此，半导体元件2的背部表面22可与封装体3的第二表面32大致上共面，且第二保护层84覆盖半导体元件2的背部表面22。
另外，图3的第二电路5b的基层52a的厚度可大于图1的第二电路5的基层52的厚度。基层52a可由金属板形成而无需薄化阶段。此外，图3的第二电路5b的表面层54a的厚度可大于图1的第二电路5的表面层54的厚度。
图4描绘根据本发明的一些实施例的半导体封装1c的实例的截面图。半导体封装1c类似于图1中所展示的半导体封装1，且类似特征以相同方式编号且不关于图4进一步描述。在图4的半导体封装1c中，底部封装9可进一步附接到图1的半导体封装1。即，底部封装9附接到半导体封装1，且图4的半导体封装1c为层叠封装(package-on-package,POP)结构。在一个实施例中，底部封装9通过连接元件83电连接到在第二保护层84的开口841中暴露的第二电路5的部分。
图5描绘根据本发明的一些实施例的半导体封装1d的实例的截面图。半导体封装1d类似于图1中所展示的半导体封装1，且类似特征以相同方式编号且不关于图5进一步描述。在图5的半导体封装1d中，外部连接器可为例如第三柱状凸块88。在一个实施例中，第三柱状凸块88包含柱状部分882及凸块部分880，其中柱状部分882的宽度小于凸块部分880的宽度。应注意，柱状部分882可大致上呈柱形形状，且凸块部分880可大致上呈盘形形状。柱状部分882及凸块部分880可通过例如线接合设备同时地且整体地形成。第三柱状凸块88的凸块部分880接触在第一保护层82的开口821中暴露的第一电路4。
图6描绘根据本发明的一些实施例的半导体封装1e的实例的截面图。半导体封装1e类似于图1中所展示的半导体封装1，且类似特征以相同方式编号且不关于图6进一步描述。在图6的半导体封装1e中，半导体元件2的有源表面21依图6中所展示的定向面朝下。此外，半导体元件2的背部表面22可被封装体3覆盖，且依图6中所展示的定向面朝上。在一个实施例中,半导体元件2的背部表面22安置成邻近于封装体3的第一表面31，且半导体元件2的有源表面21面向封装体3的第二表面32。
如图6中所展示，第一柱状凸块6的柱状部分62的第一端621并不从封装体3的第一表面31突出。即，柱状部分62的第一端621并未延伸越过封装体3的第一表面31。柱状部分62的第一端621的顶部表面与封装体3的第一表面31大致上共面，且接触第一电路4的底部表面。另外，第二柱状凸块7电连接半导体元件2的垫23及第二电路5。在一个实施例中，第二柱状凸块7的柱状部分72的第一端721通过焊料74电连接到第二电路5的基层52。
图7描绘根据本发明的一些实施例的半导体封装1f的实例的截面图。半导体封装1f类似于图1中所展示的半导体封装1，且类似特征经以相同方式编号且不关于图7进一步描述。在图7的半导体封装1f中，导电互连件可为例如导电柱(conductive pillar)75而非第二柱状凸块7(如图1中所展示)。导电柱75可通过例如电镀或其它手段形成。导电柱75电连接且物理接触半导体元件2的垫23及第一电路4。
图8描绘根据本发明的一些实施例的半导体封装1g的实例的截面图。半导体封装1g类似于图5中所展示的半导体封装1d，且类似特征以相同方式编号且不关于图8进一步描述。图8的半导体封装1g包含至少一个接合线76，其电连接半导体元件2的有源表面21的垫23及第二电路5的基层52。接合线76可使用例如线接合工具(wire bonding tool)形成，且可在垫23上开始且在垫32上终止或反之亦然。
图9描绘根据本发明的一些实施例的半导体封装1h的实例的截面图。半导体封装1h类似于图1中所展示的半导体封装1，且类似特征以相同方式编号且不关于图9进一步描述。在图9的半导体封装1h中，第二柱状凸块7(例如，导电互连件)的至少一者的柱状部分72可不垂直于半导体元件2的有源表面21。即，锐角形成在第二柱状凸块7(例如，导电互连件)的柱状部分72与半导体元件2的有源表面21之间的。另外，导电互连件中的至少一者可为接合线77。
图10描绘根据本发明的一些实施例的半导体封装1i的实例的截面图。半导体封装1i类似于图9中所展示的半导体封装1h，且类似特征经以相同方式编号且不关于图10进一步描述。在图10的半导体封装1i中，第一柱状凸块6的柱状部分62的第一端621及第二柱状凸块7的柱状部分72的第一端721不从封装体3的第一表面31突出。即，柱状部分62的第一端621以及柱状部分72的第一端721并未延伸越过封装体3的第一表面31。柱状部分62的第一端621的顶部表面及柱状部分72的第一端721的顶部表面与封装体3的第一表面31大致上共面，且接触第一电路4的底部表面。
另外，图10的半导体封装1i在封装体3中进一步包含第一线段781、第二线段782、第三线段791以及第四线段792。第一线段781电连接第一电路4及半导体元件2。例如，第一线段781的一端通过凸块部分780连接半导体元件2的垫23，且第一线段781的另一端连接第一电路4的底部表面。第二线段782的一端连接第一电路4的底部表面，且第二线段782的另一端连接第二电路5的第一表面51。应注意，第一线段781及第二线段782为彼此分离的个别段，且其由单个接合线(a single bonding wire)形成。
第三线段791及第四线段792皆电连接第一电路4及第二电路5。第三线段791的一端连接第一电路4的底部表面，且第三线段791的另一端通过凸块部分790连接第二电路5的第一表面51。类似地，第四线段792的一端连接第一电路4的底部表面，且第四线段792的另一端连接第二电路5的第一表面51。应注意，第三线段791及第四线段792可为彼此分离的个别段，且其可由单个接合线形成。
图11描绘根据本发明的一些实施例的半导体封装1j的实例的截面图。半导体封装1j类似于图10的半导体封装1i，且类似特征以相同方式编号且不关于图11进一步描述。在图11的半导体封装1j中，第二电路5c嵌入于封装体3中，且第二电路5c的底部表面55与封装体3的第二表面32大致上共面。即，第二电路5c的底部表面55从封装体3的第二表面32暴露。应注意，粘合剂层12的厚度可大于第二电路5c的厚度以便防止半导体元件2接触安置在半导体元件2下方的第二电路5c的部分。
图12描绘根据本发明的一些实施例的半导体封装1k的实例的截面图。半导体封装1k类似于图5中所展示的半导体封装1d，且类似特征以相同方式编号且不关于图12进一步描述。图12的半导体封装1k包含散热器87，所述散热器87附接到对应于半导体元件2的位置(例如，在下方或在顶部)以便消散由半导体元件2产生的热。如图12中所展示，散热器87附接到邻近于半导体元件2的背部表面22的位置。散热器87可附接到半导体元件2的背部表面22上的粘合剂层12，或散热器87可直接地附接到半导体元件2的背部表面22。粘合剂层12可为热增强粘合剂(thermally enhanced adhesive)、金属膏、焊料或其中两者或多于两者的组合。散热器87可为鳍型散热器(fin-type heat sink)(包含鳍片)以便增加散热面积。应注意，半导体封装1k可为例如电源封装(power package)，其包含金属氧化物半导体场效晶体管(metal-oxide-semiconductor field-effect transistor,MOSFET)。
图13描绘根据本发明的一些实施例的半导体封装1m的实例的截面图。半导体封装1m类似于图12中所展示的半导体封装1k，且类似特征以相同方式编号且不关于图13进一步描述。图13的半导体封装1m包含左部分及右部分。图13的半导体封装1m的左部分与图12中所展示的半导体封装1k相同。图13的半导体封装1m的右部分包含半导体元件2'、粘合剂层12'以及散热器87'。
半导体元件2'具有有源表面21'以及与有源表面21'相对的背部表面22'。第一电路4电连接到半导体元件2'的有源表面21'。粘合剂层12'安置在半导体元件2'的背部表面22'上。散热器87'附接到邻近于半导体元件2'的背部表面22'的位置。散热器87'可附接到安置在半导体元件2'的背部表面22'上的粘合剂层12'。替代地，散热器87'可直接附接到半导体元件2'的背部表面22'。散热器87'可为鳍型散热器(包含鳍片)以便增加散热面积。应注意，半导体封装1m可包含例如金属氧化物半导体场效晶体管(MOSFET)，其中半导体元件2可为功率裸片(power die)，且半导体元件2'可为控制裸片(controller die)。
图14描绘根据本发明的一些实施例的半导体封装1n的实例的截面图。半导体封装1n类似于图1中所展示的半导体封装1，且类似特征以相同方式编号且不关于图14进一步描述。图14的半导体封装1n包含顶部部分及底部部分。图14的半导体封装1n的顶部分与图1中所展示的半导体封装1相同。图14的半导体封装1n的底部部分包含至少一个底部半导体元件2a、底部封装体3a、底部粘合剂层12a、第三电路42、至少一个第三柱状凸块6a及至少一个导电互连件(例如，第四柱状凸块7a)。
底部半导体元件2a可为半导体裸片或电子组件(例如，无源组件)，且安置在半导体元件2下方。底部半导体元件2a具有有源表面21a、与有源表面21a相对的背部表面22a及多个垫23a。底部半导体元件2a的有源表面21a依图14中所展示的定向面朝下。底部半导体元件2a的背部表面22a可被底部粘合剂层12a覆盖，且依图14中所展示的定向面朝上。底部半导体元件2a的背部表面22a面朝向半导体元件2的背部表面22。底部半导体元件2a的垫23a安置成邻近于底部半导体元件2a的有源表面21a。
底部封装体3a覆盖或囊封底部半导体元件2a的至少一部分。底部封装体3a的材料可包含模制化合物(例如含填料的环氧树脂)、光致成像电介质(例如焊料掩模或其它合适的介电材料)或其组合。底部封装体3a的材料可与封装体3的材料相同或不同。底部封装体3a具有第一表面31a及与第一表面31a相对的第二表面32a。如图14中所展示，底部封装体3a覆盖底部半导体元件2a的有源表面21a、底部半导体元件2a的侧表面、第三柱状凸块6a以及导电互连件(例如，第四柱状凸块7a)的部分。因此，底部半导体元件2a至少部分地嵌入于底部封装体3a中。在一个实施例中，底部半导体元件2a的有源表面21a面朝向底部封装体3a的第二表面32a，且底部半导体元件2a的背部表面22a安置成邻近于底部封装体3a的第一表面31a。应注意，底部封装体3a安置在封装体3上。即，底部封装体3a的第一表面31a接触封装体3的第二表面32，第二电路5嵌入于底部封装体3a。
第三电路42(例如，重布层(RDL))安置成邻近于底部封装体3a的第二表面32a。如图14中所展示，第三电路42安置在底部封装体3a的第二表面32a上并接触所述第二表面32a。第三电路42安置在底部半导体元件2a的有源表面21a下方。因此，底部半导体元件2a的有源表面21a面向第三电路4。应注意，第三电路42可包含通过例如电镀或喷墨印刷形成的多个扇出型迹线及/或多个凸块垫。
第三柱状凸块6a安置在底部封装体3a中。即，第三柱状凸块6a由底部封装体3a覆盖或囊封。第三柱状凸块6a电连接第三电路42以及第二电路5。第三柱状凸块6a的材料可为或包含例如金、铜、银或其中的两者或多于两者的组合。如图14中所展示，第三柱状凸块6a直接接触第二电路5。如图14中所展示，第三柱状凸块6a的一端从底部封装体3a的第二表面32a突出。即，第三柱状凸块6a的所述端延伸越过底部封装体3a的第二表面32a，且延伸到且嵌入于第三电路42中。
导电互连件(例如，第四柱状凸块7a)电连接底部半导体元件2a以及第三电路42。如图14中所展示，导电互连件可为或包含例如至少一个第四柱状凸块7a。第四柱状凸块7a安置在底部封装体3a中。第四柱状凸块7a电连接底部半导体元件2a的垫23a以及第三电路42。第四柱状凸块7a的材料可为或包含例如金、铜、银或其中的两者或多于两者的组合。如图14中所展示，第四柱状凸块7a的一端从底部封装体3a的第二表面32a突出。即，第四柱状凸块7a的所述端延伸越过底部封装体3a的第二表面32a，且延伸到且嵌入于第三电路42中。
第二保护层84(例如，焊料掩模)覆盖底部封装体3a的第二表面32a以及第三电路42。第二保护层84界定多个开口841，其暴露第三电路42的至少一部分以用于外部连接。
图15描绘根据本发明的一些实施例的半导体封装1p的实例的截面图。半导体封装1p类似于图1中所展示的半导体封装1，且类似特征以相同方式编号且不关于图15进一步描述。图15的半导体封装1p包含顶部部分及底部部分。图15的半导体封装1p的底部部分与图1中所展示的半导体封装1相同。图15的半导体封装1p的顶部部分包含至少一个顶部半导体元件2b、顶部封装体3b、顶部粘合剂层12b、第四电路44、至少一个第五柱状凸块6b以及至少一个导电互连件(例如，第六柱状凸块7b)。
顶部半导体元件2b可为半导体裸片或电子组件(例如，无源组件)，且可安置在半导体元件2上方。顶部半导体元件2b具有有源表面21b、与有源表面21b相对的背部表面22b以及多个垫23b。顶部半导体元件2b的有源表面21b依图15中所展示的定向面朝上。顶部半导体元件2b的背部表面22b可被顶部粘合剂层12b覆盖，且依图15中所展示的定向面朝下。顶部半导体元件2b的背部表面22b面朝向半导体元件2的有源表面21。顶部半导体元件2b的垫23b安置成邻近于顶部半导体元件2b的有源表面21b。
顶部封装体3b覆盖或囊封顶部半导体元件2b的至少一部分。顶部封装体3b的材料可包含模制化合物(例如含填料的环氧树脂)、光致成像电介质(例如焊料掩模或其它合适的介电材料)或其组合。顶部封装体3b的材料可与封装体3的材料相同或不同。顶部封装体3b具有第一表面31b及与第一表面31b相对的第二表面32b。如图15中所展示，顶部封装体3b覆盖顶部半导体元件2b的有源表面21b、顶部半导体元件2b的侧表面、第五柱状凸块6b以及导电互连件(例如，第六柱状凸块7b)的部分。因此，顶部半导体元件2b至少部分地嵌入顶部封装体3b中。在一个实施例中，顶部半导体元件2b的有源表面21b面朝向顶部封装体3b的第一表面31b，且顶部半导体元件2b的背部表面22b安置成邻近于顶部封装体3b的第二表面32b。应注意，顶部封装体3b安置在封装体3上。即，顶部封装体3b的第二表面32b接触封装体3的第一表面31，顶部粘合剂层12b覆盖第一电路4的另一部分，且第一电路4的另一部分嵌入于顶部封装体3b中。
第四电路44(例如，重布层(RDL))安置成邻近于顶部封装体3b的第一表面31b。如图15中所展示，第四电路44安置在顶部封装体3b的第一表面31b上并接触所述第一表面31b。第四电路44安置在顶部半导体元件2b的有源表面21b上方，因此，顶部半导体元件2b的有源表面21b面向第四电路44。应注意，第四电路44可包含通过例如电镀或喷墨印刷形成的多个扇出型迹线及/或多个凸块垫。
第五柱状凸块6b安置在顶部封装体3b中。即，第五柱状凸块6b由顶部封装体3b覆盖或囊封。第五柱状凸块6b电连接第四电路44以及第一电路4。第五柱状凸块6b的材料可为或包含例如金、铜、银或其中的两者或多于两者的组合。如图15中所展示，第五柱状凸块6b直接接触第一电路4。如图15中所展示，第五柱状凸块6b的一端从顶部封装体3b的第一表面31b突出。即，第五柱状凸块6b的所述端延伸越过顶部封装体3b的第一表面31b，且延伸到且嵌入于第四电路44中。
导电互连件(例如，第六柱状凸块7b)电连接顶部半导体元件2b以及第四电路44。如图15中所展示，导电互连件可为至少一个第六柱状凸块7b。第六柱状凸块7b安置在顶部封装体3b中。第六柱状凸块7b电连接顶部半导体元件2b的垫23b以及第四电路44。第六柱状凸块7b的材料可为或包含例如金、铜、银或其中的两者或多于两者的组合。如图15中所展示，第六柱状凸块7b的一端从顶部封装体3b的第一表面31b突出。即，第六柱状凸块7b的所述端延伸越过顶部封装体3b的第一表面31b，且延伸到且嵌入于第四电路44中。
第一保护层82(例如焊料掩模)覆盖顶部封装体3b的第一表面31b以及第四电路44。第一保护层82界定多个开口821，其暴露第四电路44的部分以用于外部连接。
图16描绘根据本发明的一些实施例的半导体封装1q的实例的截面图。半导体封装1q类似于图1中所展示的半导体封装1，且类似特征以相同方式编号且不关于图16进一步描述。图16的半导体封装1q包含三个堆叠式半导体元件(例如，半导体元件2、中间半导体元件2c以及下部半导体元件2d)。另外，图16的半导体封装1q进一步包含多个内部线(internalwires)81、第三保护层85以及第五电路45。半导体元件2通过粘合剂层12附接到中间半导体元件2c。中间半导体元件2c通过粘合剂层12c附接到下部半导体元件2d。三个堆叠式半导体元件(例如，半导体元件2、中间半导体元件2c以及下部半导体元件2d)的大小可不同。堆叠式半导体元件的位置及/或大小可相对于彼此移位。
内部线81中的一部分连接半导体元件2以及中间半导体元件2c，且内部线81中的一部分连接中间半导体元件2c以及下部半导体元件2d。另外，第一柱状凸块6中的一部分连接中间半导体元件2c以及第一电路4，且第一柱状凸块6中的一部分连接下部半导体元件2d以及第一电路4。第三保护层85(例如焊料掩模)覆盖第一电路4以及封装体3的第一表面31。第三保护层85界定多个开口851以暴露第一电路4的部分。第五电路45安置在第三保护层85上且开口851中以电连接第一电路4。第一保护层82(例如，焊料掩模)覆盖第五电路45以及第三保护层85。第一保护层82界定多个开口821，其暴露第五电路45的部分以用于外部连接。外部连接器(例如，焊料凸块86)安置在第五电路45上的开口821中。每一级的第一柱状凸块6的直径可不同以确保制造期间的机械刚性或满足电设计规范。
图17描绘根据本发明的一些实施例的半导体封装1r的实例的截面图。半导体封装1r类似于图1中所展示的半导体封装1，且类似特征以相同方式编号且不关于图17进一步描述。根据一些实施例，在图17的半导体封装1r中，粘合剂层12、第二电路5、第一柱状凸块6以及第二保护层84可被省略。半导体元件2的背部表面22与封装体3的第二表面32大致上共面。下部粘结层13(例如，胶带)可安置在半导体元件2的背部表面22及封装体3的第二表面32上。在一些其它实施例中，下部黏合层13可被省略。
图18描绘根据本发明的一些实施例的半导体封装1s的实例的截面图。半导体封装1s类似于图17中所展示的半导体封装1r，且类似特征以相同方式编号且不关于图18进一步描述。在图18的半导体封装1s中，下部粘合层13可被替换为例如金属层14。金属层14的材料可为或包含例如铜。金属层14可用作散热器，所述散热器可消散由半导体元件2产生的热。在一个实施例中，下部粘合层13可仍然存在且金属层14可安置在下部粘合层13上。
图19描绘根据本发明的一些实施例的半导体封装1t的实例的截面图。半导体封装1t类似于图17中所展示的半导体封装1r，且类似特征以相同方式编号且不关于图19进一步描述。在图19的半导体封装1t中，第二柱状凸块7的柱状部分72的长度可缩短，且第一保护层82可接触凸块部分70。因此，图19的半导体封装1t的总厚度小于图17中所展示的半导体封装1r的总厚度。此凸块结构可避免经电镀柱工艺，所述电镀柱工艺涉及光致光刻、溅镀晶种层及电镀，以及伴随掩模及工具。
图20描绘根据本发明的一些实施例的半导体封装1u的实例的截面图。半导体封装1u类似于图19中所展示的半导体封装1t，且类似特征以相同方式编号且不关于图20进一步描述。图20的半导体封装1u包含第三保护层85及第五电路45。
第三保护层85(例如焊料掩模)覆盖第一电路4以及封装体3的第一表面31。第三保护层85界定暴露第一电路4的部分的多个开口851。第五电路45安置在第三保护层85上且开口851中以电连接第一电路4。第一保护层82(例如，焊料掩模)覆盖第五电路45以及第三保护层85。第一保护层82界定暴露第五电路45的部分用于外部连接的多个开口821。外部连接器(例如，焊料凸块86)安置在第五电路45上的开口821中。
图21描绘根据本发明的一些实施例的半导体封装1v的实例的截面图。半导体封装1v类似于图17中所展示的半导体封装1r，且类似特征以相同方式编号且不关于图21进一步描述。图21的半导体封装1v包含第一部分15及第二部分16。第一部分15及第二部分16中的每一者大致上等于图17的半导体封装1r。即，图21的半导体封装1v可作为并排安置的图17的两个半导体封装1r的组合出现。第一部分15及第二部分16通过第一电路4彼此电连接。半导体元件2中的一者或两者可实质上为无源组件。
图22描绘根据本发明的一些实施例的半导体封装1w的实例的截面图。半导体封装1w类似于图21中所展示的半导体封装1v，且类似特征以相同方式编号且不关于图22进一步描述。图22的半导体封装1w包含内部线89用于电连接两个半导体元件2。
图23描绘根据本发明的一些实施例的半导体封装1x的实例的截面图。半导体封装1x类似于图19中所展示的半导体封装1t，且类似特征经以相同方式编号且不关于图23进一步描述。在图23的半导体封装1x中，第二柱状凸块7的柱状部分72可被去除或可在接合工艺期间不形成。凸块部分70可继续存在。因此，第一电路4可接触凸块部分70。因此，图23半导体封装1x的总厚度小于图19的半导体封装1t的总厚度。
图24描绘根据本发明的一些实施例的半导体封装1y的实例的截面图。半导体封装1y类似于图17中所展示的半导体封装1r，且类似特征以相同方式编号且不关于图24进一步描述。在图24的半导体封装1y中，下部粘合层13可被替换为散热器87。散热器87附接到对应于半导体元件2(例如，在其下面或顶部)的位置以便消散由半导体元件2产生的热。如图24中所展示，散热器87附接到半导体元件2的背部表面22。散热器87可为鳍形散热器(包含鳍片)以便增加散热面积。
图25描绘根据本发明的一些实施例的半导体封装1z的实例的截面图。半导体封装1z类似于图6中所展示的半导体封装1e，且类似特征以相同方式编号且不关于图25进一步描述。在图25的半导体封装1z中，根据一些实施例，图6的第一电路4、第一柱状凸块6、第一保护层82、第二保护层84以及外部连接器(例如，焊料凸块86)可被省略。半导体元件2的背部表面22与封装体3的第一表面3大致上共面。
图26描绘根据本发明的一些实施例的半导体封装1'的实例的截面图。半导体封装1'类似于图17中所展示的半导体封装1r，且类似特征以相同方式编号且不关于图26进一步描述。图26的半导体封装1'包含两个堆叠式半导体元件(即，半导体元件2以及下部半导体元件2e)。半导体元件2通过粘合剂层12附接到底部半导体元件2e。另外，图26的半导体封装1'包含安置在封装体3中的至少一个第七柱状凸块6c。即，第七柱状凸块6c被封装体3覆盖或囊封。第七柱状凸块6c电连接底部半导体元件2e以及第一电路4。
图27描绘根据本发明的一些实施例的半导体封装1”的实例的截面图。半导体封装1”类似于图17中所展示的半导体封装1r，且类似特征以相同方式编号且不关于图27进一步描述。图27的半导体封装1”包含三个堆叠式半导体元件(即，半导体元件2、中间半导体元件2f以及下部半导体元件2g)。半导体元件2通过粘合剂层12附接到中间半导体元件2f，且中间半导体元件2f通过粘合剂层12d附接到下部半导体元件2g。另外，图27的半导体封装1”包含安置在封装体3中的至少一个第八柱状凸块6d及至少一个第九柱状凸块6e。即，第八柱状凸块6d以及第九柱状凸块6e被封装体3覆盖或囊封。第八柱状凸块6d电连接中间半导体元件2f以及第一电路4。第九柱状凸块6e电连接下部半导体元件2g以及第一电路4。
图28描绘图1的半导体封装1的第一电路4的部分的实例的俯视图。如图28中所展示，第一电路4包含至少一个迹线41以及多个凸块连接盘(bump lands)43。凸块连接盘43可封围第二柱状凸块7(图1)的柱状部分72的第一端721。凸块连接盘43的尺寸(例如，直径)可能大于第二柱状凸块7的柱状部分72的第一端721的尺寸(例如，直径)，且凸块垫43的尺寸(例如，直径)可与第二柱状凸块7的柱状部分72的第一端721的尺寸(例如，直径)大致上成比例。迹线41连接具有不同尺寸(例如，直径)的凸块连接盘43。
图29描绘图1的半导体封装1的第一电路4的部分的实例的俯视图。如图29中所展示，两个迹线41a连接一个凸块连接盘43a(封围第二柱状凸块7的柱状部分72的第一端721a)。
图30A描绘图1的半导体封装1的第一电路4的部分的实例的俯视图。如图30A中所展示，一个迹线41b连接两个凸块连接盘43b。凸块连接盘43b中的每一者封围第二柱状凸块7的柱状部分72的第一端721b。迹线41b的宽度大致上等于第一端721b的直径。
图30B描绘图1的半导体封装1的第一电路4的部分的实例的俯视图。如图30B中所展示，一个迹线41c连接两个凸块连接盘43c。凸块连接盘43c中的每一者封围第二柱状凸块7的柱状部分72的第一端721c。迹线41c的宽度大于第一端721b的直径，且迹线41c的宽度大致上等于凸块垫43c的直径。
图31到40描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的各种阶段处的实例性半导体封装的截面图。应注意，图31到40中所公开的方法可用于制造图1的半导体封装1。参考图31，在裸片面朝上工艺(die face-up process)中，提供载体53，其中金属板50安置在载体53的表面上。载体53可为圆形(例如，晶片或其类似者)或矩形(例如，条带或面板)，且可包含具有低热膨胀系数(CTE)以使机械应力及翘曲最小化的材料。载体53的材料可为例如硅、玻璃、金属(例如，铜、不锈钢、铜-殷钢-铜(copper-invar-copper)或其中两者或多于两者的组合)、层压结构(例如，FR4级层压板)或树脂(例如，双马来酰亚胺三嗪(bismaleimide-triazine,BT))。金属板50(例如，铜箔)可根据层压工艺通过粘合材料附接到载体53。金属板50的厚度可为例如约1μm到约500μm，约2μm到约200μm，或约3μm到约100μm。金属板50的第一表面51(其最终形成第二电路5的第一表面51)及第二表面(其与第一表面51相对)具有合适的均匀性(例如，均匀性小于约10％、约5％或约3％且TTV小于约15μm、约10μm、约5μm)，且金属板50的顶部表面的表面粗糙度(Rz)可为约0.1μm到约10.0μm、约0.5μm到约7.0μm、约1.0μm到约3.0μm，此对于第一柱状凸块及下文所描述裸片附接的形成来说可为优点。
至少一个半导体元件2附接到金属板50的第一表面51。半导体元件2可为例如半导体裸片或电子组件(例如，无源组件)。半导体元件2具有有源表面21、与有源表面21相对的背部表面22，及多个垫23。有源表面21依图31中所展示的定向面朝上。背部表面22通过粘合剂层12附接到金属板50的第一表面51，且依图31中所展示的定向面朝下。垫23安置成邻近于半导体元件2的有源表面21。
参考图32，至少一个第一柱状凸块6形成在金属板50上。另外，至少一个导电互连件(例如，第二柱状凸块7)形成在半导体元件2上。第一柱状凸块6的材料可为例如金、铜、银、涂铂铜或其组合。如图32中所展示，第一柱状凸块6直接接触金属板50。在一个实施例中，第一柱状凸块6包含柱状部分62及凸块部分60，其中柱状部分62的宽度小于凸块部分60的宽度。应注意，柱状部分62可大致上呈柱状形状，且凸块部分60可大致上呈盘形形状。柱状部分62及凸块部分60可通过例如线接合设备同时地且整体地形成。第一柱状凸块6的凸块部分60直接接触金属板50。
柱状部分62包含第一端621及第二端622。柱状部分62的第二端622连接凸块部分60。在一个实施例中，凸块部分60通过线接合设备的接合头形成在金属板50上。接合头向上移动以形成柱状部分62。柱状部分62的顶部部分被切除以形成第一端621。
如图32中所展示，导电互连件可为至少一个第二柱状凸块7。第二柱状凸块7电连接且物理接触半导体元件2的垫23。第二柱状凸块7的材料可为金、铜、涂铂铜、银或其中的两者或多于两者的组合。在一个实施例中，第二柱状凸块7包含柱状部分72及凸块部分70，其中柱状部分72的宽度小于凸块部分70的宽度。应注意，柱状部分72可大致上呈柱状形状，且凸块部分70可大致上呈盘形形状。柱状部分72及凸块部分70可通过例如线接合设备同时地且整体地形成。
柱状部分72包含第一端721及第二端722。柱状部分72的第二端722连接凸块部分70。第二柱状凸块7的柱状部分72及凸块部分70的宽度分别小于第一柱状凸块6的柱状部分62及凸块部分60的宽度。在其它实施例中，第二柱状凸块7的柱状部分72及凸块部分70的宽度可分别与第一柱状凸块6的柱状部分62及凸块部分60的宽度大致上相同所述宽度。此外，第二柱状凸块7的柱状部分72可大致上垂直于半导体元件2的有源表面21。类似地，第一柱状凸块6的柱状部分62可大致上垂直于金属板50的第一表面51。在其它实施例中，第二柱状凸块7的柱状部分72可不垂直于半导体元件2的有源表面21，且第一柱状凸块6的柱状部分62可不垂直于金属板50的第一表面51。
参考图33，提供顶部盖55，其中缓冲层56安置在顶部盖55的表面上。顶部盖55可为圆形(例如，晶片或其类似者)或矩形(例如，条带或面板)，且可包含具有低热膨胀系数(CTE)以使机械应力及翘曲最小化的材料。顶部盖55的材料可为例如硅、玻璃、金属(例如，铜或不锈钢)、层压结构(例如，FR4型层压板)、树脂(例如，双马来酰亚胺三嗪(BT))或其中的两者或多于两者的组合。顶部盖55的大小及/或材料可与载体53的大小及/或材料大致上相同或不同。缓冲层56的材料可包含例如塑料的软材料。接着，具有缓冲层56的顶部盖55覆盖第一柱状凸块6及导电互连件(例如，第二柱状凸块7)。因此，缓冲层56接触并按压第一柱状凸块6的柱状部分62的第一端621及第二柱状凸块7的柱状部分72的第一端721。在一个实施例中，第一柱状凸块6的柱状部分62的第一端621及第二柱状凸块7的柱状部分72的第一端721可支持并维持缓冲层56及顶部盖55。在缓冲层56与金属板50之间界定空间57。
参考图33A，在一些实施例中，第一柱状凸块6可具有不同高度，且第一柱状凸块6中的一部分在被缓冲层56及顶部盖55覆盖及按压之后弯曲。
参考图34，封装体3形成在缓冲层56与金属板50之间的空间57中。封装体3的材料可包含例如模制化合物(例如，含填料的环氧树脂)、可光致成像电介质(例如，焊料掩模或其它合适的介电材料)或其组合。封装体3具有第一表面31以及与第一表面31相对的第二表面32。如图34中所展示，封装体3覆盖半导体元件2的有源表面21、半导体元件2的侧表面、第一柱状凸块6及导电互连件(例如，第二柱状凸块7)的部分。因此，半导体元件2至少部分地嵌入在封装体3中。半导体元件2的厚度小于封装体3的厚度。在一个实施例中，半导体元件2的有源表面21面朝向封装体3的第一表面31，且半导体元件2的背部表面22安置成邻近于封装体3的第二表面32。应注意，粘合剂层12的底部表面与封装体3的第二表面32大致上共面。
参考图35，在一些实施例中，缓冲层56及顶部盖55可被去除以便从封装体3暴露第一柱状凸块6及导电互连件(例如，第二柱状凸块7)。如图35中所展示，第一柱状凸块6的柱状部分62的第一端621及第二柱状凸块7的柱状部分72的第一端721从封装体3的第一表面31突出。即，第一柱状凸块6的柱状部分62的第一端621及第二柱状凸块7的柱状部分72的第一端721延伸越过封装体3的第一表面31。第一柱状凸块6的柱状部分62的第一端621及第二柱状凸块7的柱状部分72的第一端721的暴露部分可在进一步处理之前被清洁并进行微蚀刻。
参考图36，第一电路4(例如，重布层)形成在封装体3的第一表面31上。第一电路4安置在半导体元件2的有源表面21上方。因此，半导体元件2的有源表面21面向第一电路4。第一柱状凸块6的柱状部分62的第一端621接触第一电路4以使得第一电路4电连接到金属板50。第二柱状凸块7的柱状部分72的第一端721接触第一电路4以使得第一电路4电连接到半导体元件2。在一个实施例中，第一电路4可通过将晶种层形成在封装体3的第一表面31上，在晶种层上图案电镀金属层及快速蚀刻晶种层来形成。晶种层的材料可为例如钛铜(TiCu)，且电镀金属层的材料可为例如铜(Cu)。
参考图37，将载体53从金属板50去除。如果需要的话，可将暂时载体接合到顶部侧以在后续处理期间提供所要机械强度。在一个实施例中，金属板50可继续存在且经图案化以形成电路的部分。即，金属板50可未被完全去除，且金属板50的部分可继续存在成品中。因此，减少制造工艺的困难及成本。
参考图38，金属板50通过例如蚀刻被薄化以形成薄金属板50a。此薄化阶段的优点如下描述。首先，由薄金属板50a形成的第二电路5(如图40中所展示)的厚度较低。因此，与不具有薄化阶段的电路相比，第二电路5(如图40中所展示)具有小节距(fine pitch)。其次，在薄化阶段期间，被去除的金属板50的量相对小。因此，薄化阶段的处理时间减少。
参考图39，图案化表面层54通过例如图案电镀形成在薄金属板50a上。
参考图40，薄金属板50a的至少一部分被去除并经图案化。即，薄金属板50a通过例如快速蚀刻经图案化以形成基层52以使得基层52与表面层54共形。同时，形成第二电路5。第二电路5(例如，重布层(RDL))安置在封装体3的第二表面32上，且电连接到第一电路4。第二电路5安置在半导体元件2的背部表面22下方。因此，半导体元件2的背部表面22面向第二电路5。粘合剂层12插置在半导体元件2的背部表面22与第二电路5之间。第二电路5包含基层52及表面层54。表面层54安置在基层52上。因此，基层52插置在表面层54与封装体3的第二表面32之间。替代地，基层52可插置在表面层54与粘合剂层12之间。金属板50可为例如铜(Cu)箔。因此，基层52可为铜箔的部分。表面层54可为或包含例如电镀铜或其它合适的材料。基层52的厚度可为例如约0.5μm到约200μm，约1.0μm到约100μm，或约1.5μm到约50μm。
第二电路5具有第一表面51(例如，基层52的顶部表面)，其接触封装体3的第二表面32及/或粘合剂层12的底部表面。由于第二电路5的基层52是通过图案化薄金属板50a形成，因此表面状况(例如，Rz、均匀性及/或TTV)可不相依于封装体3的第二表面32及/或粘合剂层12的底部表面的表面状况。因此，第二电路5的基层52的表面状况(例如，Rz、均匀性及/或TTV)的可能比电镀或溅镀电路的表面状况更适于制造工艺。
第一保护层82及第二保护层84经形成以便获得如图1中所展示的半导体封装1。第一保护层82(例如，焊料掩模)经形成以覆盖第一电路4以及封装体3的第一表面31。第一保护层82界定暴露第一电路4的部分以用于外部连接的多个开口821。至少一个外部连接器(例如，焊料凸块86)安置在第一电路4上的开口821中。第二保护层84(例如焊料掩模)经形成以覆盖第二电路5、封装体3的第二表面32以及粘合剂层12。第二保护层84界定暴露第二电路5的部分以用于外部连接的多个开口841。
图41到46描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的各种阶段处的实例性半导体封装的截面图。应注意，图41到46中所公开的方法可用于制造例如图2的半导体封装1a。参考图41，在裸片面朝上的工艺中，半导体元件2的背部表面22附接到载体53上的金属板50的第一表面51。接着，第一柱状凸块6形成在金属板50上，且导电互连件(例如，第二柱状凸块7)形成在半导体元件2上。应注意，图41的阶段可与图32的阶段大致上相同。
参考图42，封装体3经形成以覆盖半导体元件2的有源表面21、半导体元件2的侧表面、第一柱状凸块6以及导电互连件(例如，第二柱状凸块7)的部分。在一个实施例中，封装体3可通过例如包覆模制工艺(over-molding process)形成。封装体3具有第一表面31以及与第一表面31相对的第二表面32。如图42中所展示，依图42中所展示的定向，封装体3的第一表面31高于第一柱状凸块6的柱状部分62的第一端621以及第二柱状凸块7的柱状部分72的第一端721。
参考图43，封装体3通过例如研磨从其第一表面31经薄化以从封装体3的第一表面31暴露第一柱状凸块6的柱状部分62的第一端621以及第二柱状凸块7的柱状部分72的第一端721。因此，柱状部分62的第一端621的顶部表面以及柱状部分72的第一端721的顶部表面与封装体3的第一表面31大致上共面。
参考图44，第一电路4形成在封装体3的第一表面31上。第一柱状凸块6的柱状部分62的第一端621的顶部表面接触第一电路4以使得第一电路4电连接到金属板50。第二柱状凸块7的柱状部分72的第一端721的顶部表面接触第一电路4以使得第一电路4电连接到半导体元件2。
参考图45，将载体53从金属板50去除。在一些实施例中，可将暂时载体附接到顶部侧以在后续处理期间提供所要机械刚性。
参考图46，金属板50通过例如选择性蚀刻经图案化以形成基层52a。同时，形成第二电路5a。因此，第二电路5a可包含直接从金属板50图案化而无需薄化阶段的基层52a。即，第二电路5a为具有整体结构的单层。
第一保护层82及第二保护层84经形成以便获得如图2中所展示的半导体封装1a。
图47到54描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的各种阶段处的实例性半导体封装的截面图。应注意，图47到54中所公开的方法可用于制造例如图6的半导体封装1e。参考图47，在裸片面朝下的工艺中，半导体元件2的有源表面21及导电互连件(例如，第二柱状凸块7)面向载体53上的金属板50的第一表面51。
参考图48，半导体元件2的有源表面21通过导电互连件(例如，第二柱状凸块7)电连接到载体53上的金属板50的第一表面51。在一个实施例中，第二柱状凸块7的柱状部分72的第一端721通过焊料74电连接到金属板50。在一些实施例中，位于金属板50上的焊料目标(solder target)可通过例如镍金(NiAu)或其类似者预形成(pre-formed)以促进控制焊料湿润(solder wetting)。
参考图49，第一柱状凸块6形成在金属板50上。如图49中所展示，第一柱状凸块6直接接触金属板50。
参考图50，封装体3经形成以覆盖半导体元件2、第一柱状凸块6以及导电互连件(例如，第二柱状凸块7)的部分。在一个实施例中，封装体3可通过例如包覆模制工艺形成。如图50中所展示，依图50中所展示的定向，封装体3的第一表面31可能高于第一柱状凸块6的柱状部分62的第一端621以及半导体元件2的背部表面22。
参考图51，封装体3通过例如研磨从其第一表面31经薄化以从封装体3的第一表面31暴露第一柱状凸块6的柱状部分62的第一端621。因此，柱状部分62的第一端621的顶部表面与封装体3的第一表面31大致上共面。在一个实施例中，封装体3从其第一表面31经进一步薄化以暴露半导体元件2的背部表面22以使得半导体元件2的背部表面22与封装体3的第一表面31大致上共面(如图51A中所展示)。
参考图52，第一电路4形成在封装体3的第一表面31上。第一柱状凸块6的柱状部分62的第一端621的顶部表面接触第一电路4以使得第一电路4电连接到金属板50。
参考图53，将载体53从金属板50去除。可将牺牲载体接合到顶部侧(包含第一电路4)以在后续处理期间提供所要机械强度。
参考图54，在一些实施例中，第二电路5可通过与图38到40中所说明的相同阶段形成。
接着，第一保护层82及第二保护层84经形成以便获得如图6中所展示的半导体封装1e。
图55到58描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的各种阶段处的实例性半导体封装的截面图。应注意，图55到58中所公开的方法可用于制造例如图10的半导体封装1i。参考图55，在裸片面朝上的工艺中，半导体元件2的背部表面22附接到载体53上的金属板50的第一表面51。接着，第一柱状凸块6形成在金属板50上，且导电互连件(例如，第二柱状凸块7)形成在半导体元件2上。应注意，第二柱状凸块7中的一些的柱状部分72不垂直于半导体元件2的有源表面21。即，锐角形成在第二柱状凸块7的柱状部分72与半导体元件2的有源表面21之间。
另外，形成单个接合线78、79。单个接合线78连接半导体元件2的有源表面21及金属板50，且包含第一线段781、第二线段782及中间线段783。单个接合线79的两端连接金属板50。单个接合线79包含第三线段791、第四线段792以及中间线段793。
封装体3经形成以覆盖半导体元件2的有源表面21、半导体元件2的侧表面、第一柱状凸块6、导电互连件(例如，第二柱状凸块7)以及单个接合线78、79的部分。在一个实施例中，封装体3可通过例如包覆模制工艺形成。封装体3具有第一表面31以及与第一表面31相对的第二表面32。如图55中所展示，依图55中所展示的定向，封装体3的第一表面31高于第一柱状凸块6的柱状部分62的第一端621、第二柱状凸块7的柱状部分72的第一端721以及中间线段783、793。
参考图56，封装体3通过例如研磨从其第一表面31经薄化以从封装体3的第一表面31暴露第一柱状凸块6的柱状部分62的第一端621、第二柱状凸块7的柱状部分72的第一端721以及单个接合线78、79的部分。因此，柱状部分62的第一端621的顶部表面以及柱状部分72的第一端721的顶部表面与封装体3的第一表面31大致上共面。此外，将中间线段783、793去除以使得第一线段781及第二线段782为彼此分离的个别段，且第三线段791及第四线段792为彼此分离的个别段。
参考图57，第一电路4形成在封装体3的第一表面31上。第一柱状凸块6的柱状部分62的第一端621的顶部表面接触第一电路4以使得第一电路4电连接到金属板50。第二柱状凸块7的柱状部分72的第一端721的顶部表面接触第一电路4以使得第一电路4电连接到半导体元件2。此外，第一线段781电连接第一电路4以及半导体元件2。第一线段781的一端通过凸块部分780连接半导体元件2的垫23，且第一线段781的另一端连接第一电路4的底部表面。第二线段782的一端连接第一电路4的底部表面，且第二线段782的另一端连接金属板50的第一表面51。另外，第三线段791的一端连接第一电路4的底部表面，且第三线段791的另一端通过凸块部分790连接金属板50的第一表面51。类似地，第四线段792的一端连接第一电路4的底部表面，且第四线段792的另一端连接金属板50的第一表面51。
参考图58，将载体53从金属板50去除。牺牲载体可附接在顶部侧上以为随后处理提供所要强度。
接着，第二电路5可通过与图38到40中所说明的相同阶段形成。第一保护层82及第二保护层84经形成以便获得如图10中所展示的半导体封装1i。
图59到62描绘根据本发明的一些实施例的在用于制造半导体封装的实例性方法期间的各种阶段处的实例性半导体封装的截面图。应注意，图59到62中所公开的方法可用于制造例如图11的半导体封装1j。参考图59，提供载体53，其中金属板57安置在载体53的表面上。金属层57可为例如图31的金属板50或晶种层。
参考图60，第二电路5c通过例如图案电镀形成在金属层57上。
参考图61，在裸片面朝上工艺中，半导体元件2的背部表面22通过粘合剂层12附接到载体53上的金属层57。应注意，粘合剂层12的厚度大于第二电路5c的厚度以便防止半导体元件2接触安置在半导体元件2下方的第二电路5c的部分。
形成第一柱状凸块6、导电互连件(例如，第二柱状凸块7)、单个接合线78、79以及封装体3如图55中所展示。
参考图62，薄化封装体3如图56中所展示。接着，第一电路4形成在封装体3的第一表面31上，如图57中所展示。接着，将载体53从金属层57去除。接着，可将金属层57或金属层47的部分去除以使得从封装体3的第二表面32暴露第二电路5c。第一保护层82及第二保护层84经形成以便获得如图11中所展示的半导体封装1j。
如本文中所使用，除非上下文另有明确指示，否则单数术语“一个(a)”、“一个(an)”和“所述”可包含复数对象。
除非另有规定，例如“在…上面”、“在…下面”、“上”、“左”、“右”、“下”、“顶部”、“底部”、“垂直”、“水平”、“侧”、“较高”、“下部”、“上部”、“在…上方”、“在…下方”等等的空间描述是相对于图中所展示的定向指示。应理解，本文中所使用的空间描述是仅出于说明的目的，且本文中所描述的结构的实际实施方案可以任一定向或方式进行空间布置，只要此布置不背离本发明的实施例的优点。
如本文中所使用，术语“大约”、“大致上”、“基本”、及“约”被用于描述及考虑小变化。在结合事件或情形使用时，所述术语可是指其中确切地发生事件或情形的例子以及其中近似地发生事件或情形的例子。举例来说，当结合数值使用时，所述术语可是指小于或等于所述数值的±10％的变化范围，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％，或小于或等于±0.05％。举例来说，如果两个数值之间的差小于或等于所述值的平均值的±10％(例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％，或小于或等于±0.05％)，那么所述值可被认为大致上相同或相等。
如果两个表面之间的位移不大于5μm，不大于2μm，不大于1μm，或不大于0.5μm，那么两个表面可被认为共面或大致上共面。如果两个表面及/或对象之间的角度为从80度到100度，从85度到95度，从88度到92度或从89度到91度，那么可认为两个表面及/或对象大致上垂直。
在一些实施例的描述中，提供在另一组件的“上”、“上方”或“顶部”的组件可囊括其中后一组件直接在前一组件上(例如，物理或直接接触)的状况，以及其中一或多个介入组件可位于前一组件与后一组件之间的状况。
另外，数量、比率及其它数值有时在本文中以范围格式呈现。应理解，此范围格式是出于便利及简洁起见而使用且应灵活地理解为包含明确规定为范围的限制的数值，而且还包含所述范围内囊括的所有个别数值或子范围，犹如每一数值及子范围是明确规定的。
虽然已参考本发明的特定实施例描述并说明本发明，但这些描述及说明并不限制本发明。所属领域的技术人员应理解，在不背离如随附权利要求书所界定的本发明的真实精神及范围的情况下，可做出各种改变且可替代等效物。说明可不必按比例绘制。由于制造工艺及容差，因此本发明中的精巧呈现与实际设备之间可存在差异。可存在本发明的未具体说明的其它实施例。说明书及图式应视为说明性而非限制性。可进行修改以使特定情况、材料、物质组合物、方法或过程适应本发明的目的、精神及范围。所有此些修改意欲属于随附的权利要求书的范围内。虽然已参考以特定次序执行的特定操作来描述本文中所公开的方法，但应理解，可在不背离本发明的教示的情况下将这些操作组合、细分或重新排序以形成等效方法。因此，除非本文中特别指明，否则操作的次序及分组并非本发明的限制。

Claims (20)

1.一种半导体封装，其包括：
半导体元件，包含至少一个导电互连件，其突出所述半导体元件的有源表面；
至少一个柱状凸块，其安置成邻近于所述半导体元件的侧表面；及
封装体，其封装所述半导体元件及所述柱状凸块；
其中所述导电互连件的宽度小于所述柱状凸块的宽度。
2.根据权利要求1所述的半导体封装，其中所述封装体封装所述半导体元件的所述有源表面及所述侧表面。
3.根据权利要求2所述的半导体封装，其包含多个所述柱状凸块和多个所述导电互连件，且相邻的二个所述柱状凸块之间的间距大于相邻的二个所述导电互连件之间的间距。
4.根据权利要求2所述的半导体封装，其中所述封装体具有第一表面，所述半导体元件的所述有源表面朝向所述封装体的所述第一表面,所述柱状凸块的所述宽度朝向所述第一表面渐增，且所述导电互连件的所述宽度朝向所述第一表面渐缩。
5.根据权利要求4所述的半导体封装，其中所述导电互连件的侧表面包含曲面，且所述曲面的一端邻接所述封装体的第一表面。
6.根据权利要求5所述的半导体封装，其中所述导电互连件包含柱状部分及凸块部分，所述柱状部分的宽度小于所述凸块部分的宽度，所述凸块部分的一端邻接所述封装体的所述第一表面，且所述凸块部分的另一端电连接所述半导体组件。
7.根据权利要求2所述的半导体封装，其中所述柱状凸块的一端、所述导电互连件的一端及所述封装体的第一表面大致上共面。
8.根据权利要求7所述的半导体封装，其进一步包括第一电路，其安置成邻近于所述封装体的所述第一表面，且所述第一电路电连接所述柱状凸块及所述导电互连件。
9.根据权利要求1所述的半导体封装，其中所述柱状凸块的侧表面包含曲面，且所述曲面的一端邻接所述封装体的第一表面。
10.根据权利要求9所述的半导体封装，其中所述柱状凸块包含柱状部分及凸块部分，所述柱状部分的宽度小于所述凸块部分的宽度，所述凸块部分的一端邻接所述封装体的所述第一表面。
11.一种半导体封装，其包括：
封装件，包括：
半导体元件，其包括导电互连件，所述导电互连件突出所述半导体元件的有源表面；
封装体，其封装所述半导体元件的所述有源表面及侧表面，所述封装体具有第一表面及与所述第一表面相对的第二表面，且所述第一表面与所述导电互连件的表面大致上对齐；及
基板，其安置成邻近于所述封装体的所述第二表面，且电连接所述封装件。
12.根据权利要求11所述的半导体封装，其中所述基板通过连接元件电连接所述封装件。
13.根据权利要求12所述的半导体封装，其中所述封装件包括保护层，所述保护层安置成设于所述封装体的所述第二表面与基板之间，所述保护层包括开口，且所述连接元件设于所述开口中。
14.根据权利要求13所述的半导体封装，其中所述保护层接触所述连接元件。
15.根据权利要求13所述的半导体封装，其进一步包括柱状凸块，其安置成邻近于所述半导体元件的所述侧表面，所述连接组件与所述柱状凸块重迭。
16.根据权利要求15所述的半导体封装，其中所述导电互连件的一端、所述柱状凸块的一端及所述封装体的所述第一表面大致上共面。
17.根据权利要求16所述的半导体封装，其进一步包括第一电路，其安置成邻近于所述封装体的所述第一表面，且所述第一电路通过述柱状凸块电连接所述连接元件。
18.根据权利要求11所述的半导体封装，其进一步包括第二电路，其安置成邻近于所述封装体的所述第二表面，所述第二电路电连接所述柱状凸块。
19.根据权利要求18所述的半导体封装，其中所述封装件包括保护层，所述保护层安置成邻近于所述封装体的所述第二表面，所述保护层包括开口，所述开口暴露所述第二电路的至少一部分。
20.根据权利要求19所述的半导体封装，所述暴露的第二电路包括一表面低于保护层一表面。
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