CN110299351A - 半导体封装件及其形成方法 - Google Patents

半导体封装件及其形成方法 Download PDF

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Publication number
CN110299351A
CN110299351A CN201910220583.1A CN201910220583A CN110299351A CN 110299351 A CN110299351 A CN 110299351A CN 201910220583 A CN201910220583 A CN 201910220583A CN 110299351 A CN110299351 A CN 110299351A
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China
Prior art keywords
dielectric layer
hole
layer
conductive
integrated circuit
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CN201910220583.1A
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CN110299351B (zh
Inventor
蔡仲豪
林佳加
吴凯强
王垂堂
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明的实施例是半导体器件及其形成方法，半导体器件包括具有有源侧和背侧的集成电路管芯，背侧与有源侧相对；密封集成电路管芯的模塑料以及位于集成电路管芯和模塑料上面的第一再分布结构，第一再分布结构包括第一金属化图案和第一介电层，第一金属化图案电连接至集成电路管芯的有源侧，第一金属化图案的至少部分形成电感器。

Description

半导体封装件及其形成方法
技术领域
本发明的实施例总体涉及半导体领域，更具体地，涉及半导体封装件及其形成方法。
背景技术
由于各个电组件(例如，晶体管、二极管、电阻器、电容器等)的集成度的持续改进，半导体工业已经经历了快速增长。对于大部分而言，这种集成密度的改进来自于最小特征尺寸的连续减小，这使得更多的组件集成到给定的区域。随着对缩小电子器件的需求的增长，对半导体管芯的更小且更具创造性的封装技术的需求也已经出现。这种封装系统的实例是叠层封装(PoP)技术。在PoP器件中，顶部半导体封装件堆叠在底部半导体封装件的顶部上以提供高集成度和组件密度。PoP技术通常能够在印刷电路板(PCB)上产生具有增强的功能和较小的封装区域的半导体器件。
发明内容
根据本发明的一个方面，提供了一种半导体器件，包括：集成电路管芯，具有有源侧和背侧的，所述背侧与所述有源侧相对；模塑料，密封所述集成电路管芯；以及第一再分布结构，位于所述集成电路管芯和所述模塑料上面，所述第一再分布结构包括第一金属化图案和第一介电层，所述第一金属化图案电连接至所述集成电路管芯的有源侧，所述第一金属化图案的至少部分形成电感器。
根据本发明的另一个方面，提供了一种形成半导体器件的方法，包括：用模塑料密封集成电路管芯；在所述集成电路管芯和所述模塑料上方形成第一介电层；在所述第一介电层中形成第一导电通孔，所述第一导电通孔电连接至所述集成电路管芯的第一管芯连接件；在所述第一介电层中形成第二导电通孔，所述第二导电通孔位于邻近所述集成电路管芯的所述模塑料上方；在所述第一介电层上方形成第一金属化图案；在所述第一介电层、所述第一导电通孔、所述第二导电通孔和所述第一金属化图案上方形成第二介电层；在所述第二介电层中形成第三导电通孔，所述第三导电通孔电连接至所述第一金属化图案，其中，所述第一导电通孔、所述第二导电通孔、所述第一金属化图案和所述第三导电通孔形成电感器或变压器；以及在所述第三导电通孔和所述第二介电层上方形成绝缘层，所述绝缘层覆盖所述第三导电通孔。
根据本发明的又一个方面，提供了一种形成半导体器件的方法，包括：形成第一封装件，包括：在载体衬底上方形成电连接件；使用粘合层将第一管芯的背侧附接至所述载体衬底，所述第一管芯邻近所述电连接件；用模塑料密封所述第一管芯和所述电连接件；在所述第一管芯、所述模塑料和所述电连接件上方形成第一再分布结构，所述电连接件电连接至所述第一再分布结构，所述第一再分布结构包括第一集成组件，所述第一集成组件是电感器或变压器；以及去除所述载体衬底。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1、图2、图3、图4、图5、图6、图7、图8、图9、图10、图11、图12、图13、图14A、图15、图16、图17、图18A-1、图18A-2、图18B-1、图18B-2、图18B-3、图18B-4、图19、图20、图21和图22示出了根据一些实施例的在用于形成封装结构的工艺期间的中间步骤的截面图和平面图。
图14B-1、图14B-2、图14B-3、图14B-4、图14B-5、图14B-6、图14B-7和图14B-8示出了根据一些实施例的开关电路的示例性示意图，其中，电感器/变压器连接至开关电路的开关。
图23、图24、图25和图26示出了根据一些实施例的在用于形成封装件结构的工艺期间的中间步骤的截面图。
图27示出了根据一些实施例的在用于形成封装件结构的工艺期间的中间步骤的截面图。
图28示出了根据一些实施例的在用于形成封装件结构的工艺期间的中间步骤的截面图。
图29、图30、图31、图32、图33和图34示出了根据一些实施例的在用于形成封装件结构的工艺期间的中间步骤的截面图。
图35、图36和图37示出了根据一些实施例的在用于形成封装件结构的工艺期间的中间步骤的截面图。
图38示出了根据一些实施例的在用于形成封装件结构的工艺期间的中间步骤的截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参照标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，此处可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地做出相应的解释。
电感器是无源电子组件，可以在由流过电感器的电流所产生的磁场中存储能量。电感器可以构建为缠绕介电或磁性材料芯的导电材料的线圈。电感器的一个可以测量的参数是电感器存储磁能量的能力，也称为电感器的电感系数。可以测量的另一参数是电感器的品质(Q)因数。电感器的Q因数是对电感器的效率的衡量并且可以计算为在给定频率下电感器的感抗与电感器的电阻的比率。
可以在具体背景(即，具有集成至再分布结构的组件(诸如电感器、变压器或两者)的封装结构(例如，集成扇出(InFO)封装结构))下讨论本文讨论的实施例。集成至再分布结构的组件可以提供低成本和高性能组件以改进射频开关器件的性能。改进的射频天线开关的性能可以包括改进的插入损耗和改进的隔离。例如，电感器能够消除CMOS器件的寄生/耦合效应。此外，公开的实施例包括保护层以防止电感器的导电材料的氧化。而且，公开的实施例包括将形成在再分布结构的通孔沟槽中的电感器的导电材料，以使电感器具有更高的品质(Q)因数，并且也可以改进变压器的性能。此外，在一些实施例中，可以去除邻近组件的再分布结构的介电材料(例如，邻近组件形成的气隙)，以减小组件的寄生电容。包括气隙的实施例可以改进电感器的Q因数并且也可以提高电感器的自谐振频率。与没有电感器和/或变压器的射频开关器件相比，包括连接至射频器件开关的电感器的公开的实施例可以允许射频开关器件具有更低的功率损耗和更高的隔离度。
此外，本发明的教导适用于包括再分布结构的任何封装结构。其它实施例考虑了其它应用，诸如本领域普通技术人员在阅读本发明之后将显而易见的不同封装件类型或不同配置。应该注意，本文讨论的实施例不必示出可能存在于结构中的每一个组件或部件。例如，可从附图中省略多个组件，诸如当讨论一个组件可能足以表达实施例的各个方面时。此外，本文中讨论的方法实施例可能讨论为以特定顺序实施；然而，可以以任何逻辑顺序实施其它方法实施例。
图1、图2、图3、图4、图5、图6、图7、图8、图9、图10、图11、图12、图13、图14A、图15、图16、图17、图18A-1、图18A-2、图18B-1、图18B-2、图18B-3、图18B-4、图19、图20、图21和图22示出了根据一些实施例的在用于形成封装结构的工艺期间的中间步骤的截面图和平面图。图1示出了载体衬底100和形成在载体衬底100上的释放层102。分别示出用于形成第一封装件和第二封装件的第一封装件区域600和第二封装件区域602。
载体衬底100可以是玻璃载体衬底、陶瓷载体衬底等。载体衬底100可以是晶圆，从而使得可以同时在载体衬底100上形成多个封装件。释放层102可以由基于聚合物的材料形成，其可以与载体衬底100一起从在随后的步骤中形成的上覆结构处去除。在一些实施例中，释放层102是诸如光热转换(LTHC)释放涂层的基于环氧树脂的热释放材料，该材料在加热时失去其粘合性。在其它实施例中，释放层102可以是紫外(UV)胶，当暴露于UV光时失去其粘合性。释放层102可以以液体形式分配并且被固化，可以是层压在载体衬底100上的层压膜等。释放层102的顶面可以是齐平的并且可以具有高度的共面性。
在图2中，形成介电层104和金属化图案106(有时称为再分布层或再分布线)。介电层104形成在释放层102上。介电层104的底面可以与释放层102的顶面接触。在一些实施例中，介电层104由诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的聚合物形成。在其它实施例中，介电层104由氮化物，诸如氮化硅；氧化物，诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)等；等形成。可以通过诸如旋涂、化学汽相沉积(CVD)、层压等或它们的组合的任何可接受的沉积工艺形成介电层104。
金属化图案106形成在介电层104上。作为形成金属化图案106的实例，在介电层104上方形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。之后，在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案106。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。之后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成金属化图案106。
在图3中，在金属化图案106和介电层104上形成介电层108。在一些实施例中，介电层108由聚合物形成，聚合物可以是可以使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的感光材料。在其它实施例中，介电层108由氮化物，诸如氮化硅；氧化物，诸如氧化硅、PSG、BSG、BPSG；等形成。可以通过旋涂、层压、CVD等或它们的组合形成介电层108。之后，图案化介电层108以形成暴露金属化图案106的部分的开口。可以通过可接受的工艺图案化，诸如当介电层是感光材料时通过将介电层108暴露于光或通过例如使用各向异性蚀刻的蚀刻。
介电层104和108以及金属化图案106可以称为背侧再分布结构110。在所示的实施例中，背侧再分布结构110包括两个介电层104和108以及一个金属化图案106。在其它实施例中，背侧再分布结构110可以包括任何数量的介电层、金属化图案和导电通孔。通过重复用于形成金属化图案106和介电层108的工艺，可以在背侧再分布结构110中形成一个或多个额外的金属化图案和介电层。可以在通过在下面的介电层的开口中形成金属化图案的晶种层和导电材料的金属化图案的形成期间形成导电通孔(未示出)。因此，导电通孔可以互连并且电连接各个金属化图案。
在图4中，形成电连接件112。电连接件112将延伸穿过随后形成的密封剂130(见图7)，并且在下文中可以称为通孔112。作为形成通孔112的实例，在背侧再分布结构110上方(例如，在如图所示的介电层108和金属化图案106的暴露部分上方)形成晶种层。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于通孔。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成通孔112。
在图5中，通过粘合剂116将集成电路管芯114粘合至介电层108。虽然两个集成电路管芯114示出为粘合在第一封装区域600和第二封装区域602的每个中，但是应该理解，可以在每个封装区域中粘合更多或更少的集成电路管芯114。例如，可以在每个区域中粘合两个或三个集成电路管芯114。集成电路管芯114可以是逻辑管芯(例如，中央处理单元、微控制器等)、存储器管芯(例如，动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯等)、电源管理管芯(例如，电源管理集成电路(PMIC)管芯)、射频(RF)管芯、传感器管芯、微电子机械系统(MEMS)管芯、信号处理管芯(例如，数字信号处理(DSP)管芯)、前端管芯(例如，模拟前端(AFE)管芯)等或它们的组合。而且，在一些实施例中，集成电路管芯114可以具有不同的尺寸(例如，不同的高度和/或表面积)，并且在其它实施例中，集成电路管芯114可以具有相同的尺寸(例如，相同的高度和/或表面积)。
在粘合至介电层108之前，可以根据可应用的制造工艺处理集成电路管芯114以在集成电路管芯114中形成集成电路。例如，集成电路管芯114每个均包括半导体衬底118，半导体衬底118诸如掺杂或未掺杂的硅或绝缘体上半导体(SOI)衬底的有源层。半导体衬底可以包括其它半导体材料，诸如锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或它们的组合。也可以使用诸如多层衬底或梯度衬底的其它衬底。诸如晶体管、二极管、电容器、电阻器等的器件可以形成在半导体衬底118中和/或上，并且可以通过互连结构120互连以形成集成电路，互连结构120由例如半导体衬底118上的一个或多个介电层中的金属化图案形成。
集成电路管芯114还包括制成外部连接的焊盘122，诸如铝焊盘。焊盘122位于可以称为集成电路管芯114的相应的有源侧的位置上。钝化膜124位于集成电路管芯114上并且位于焊盘122的部分上。开口穿过钝化膜124至焊盘122。诸如导电柱(例如，包括诸如铜的金属)的管芯连接件126位于穿过钝化膜124的开口中并且机械地和电连接至相应的焊盘122。可以通过例如镀等形成管芯连接件126。管芯连接件126电连接集成电路管芯114的相应的集成电路。
介电材料128位于集成电路管芯114的有源侧上，诸如位于钝化膜124和管芯连接件126上。介电材料128横向密封管芯连接件126，并且介电材料128与相应的集成电路管芯114横向共末端。介电材料128可以是聚合物，诸如PBO、聚酰亚胺、BCB等；氮化物，诸如氮化硅等；氧化物，诸如氧化硅、PSG、BSG、BPSG等；等或它们的组合，并且可以例如通过旋涂、层压、CVD等形成。
粘合剂116位于集成电路管芯114的背侧上并且将集成电路管芯114粘合至背侧再分布结构110，诸如介电层108。粘合剂116可以是任何合适的粘合剂、环氧树脂、管芯附着膜(DAF)等。粘合剂116可以施加至集成电路管芯114的背侧(诸如相应的半导体晶圆的背侧)或可以施加在载体衬底100的表面上方。集成电路管芯114可以诸如通过锯切或切割被分割并且使用例如拾取和放置工具通过粘合剂116粘合至介电层108。
在图6中，在各个组件上形成密封剂130。密封剂130可以是模塑料、环氧树脂等，并且可以通过压缩模塑、转移模塑等施加。密封剂130可以形成在载体衬底100上方，从而掩埋或覆盖通孔112和/或集成电路管芯114的管芯连接件126。在一些实施例中，省略介电材料128并且密封剂130围绕并且钝化管芯连接件126。之后，固化密封剂130。
在图7中，对密封剂130实施平坦化工艺以暴露通孔112和管芯连接件126。平坦化工艺也可以研磨介电材料128。在平坦化工艺之后，通孔112、管芯连接件126、介电材料128和密封剂130的顶面共面。平坦化工艺可以是例如化学机械抛光(CMP)、研磨工艺等。在一些实施例中，例如，如果已经暴露通孔112和管芯连接件126，则可以省略平坦化。
在图8至图13中，形成前侧再分布结构132。前侧再分布结构132包括集成组件150，诸如电感器、变压器或两者(见图14A和图15)。前侧再分布结构132包括介电层136和140以及金属化图案138和142。
前侧再分布结构132的形成可以通过在密封剂130、通孔112和管芯连接件126上沉积介电层136开始。在一些实施例中，介电层136由聚合物形成，聚合物可以是可以使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的感光材料。在其它实施例中，介电层136由氮化物，诸如氮化硅；氧化物，诸如氧化硅、PSG、BSG、BPSG；等形成。可以通过旋涂、层压、CVD等或它们的组合形成介电层136。
在图9中，图案化介电层136。图案化形成暴露通孔112和管芯连接件126的部分的开口。可以通过可接受的工艺图案化，诸如当介电层136是感光材料时通过将介电层136暴露于光或通过例如使用各向异性蚀刻的蚀刻。如果介电层136是感光材料，则可以在曝光之后显影介电层136。
在图10中，在介电层136上形成具有通孔的金属化图案138。作为形成金属化图案138的实例，在介电层136上方和穿过介电层136的开口中形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。之后，在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案138。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。之后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成金属化图案138和通孔。在穿过介电层136至例如通孔112和/或管芯连接件126的开口中形成通孔。
在图11中，在介电层136和金属化图案138上方沉积介电层140。用于形成介电层140的材料和工艺可以与介电层136类似，并且此处不再重复描述。
在图12中，之后，图案化介电层140。图案化形成暴露金属化图案138的部分的开口。可以通过可接受的工艺图案化，诸如当介电层140是感光材料时通过将介电层140暴露于光或通过例如使用各向异性蚀刻的蚀刻。如果介电层140是感光材料，则可以在曝光之后显影介电层140。
在图13中，在介电层140和金属化图案138上形成焊盘142。焊盘142包括焊盘142A和焊盘142B。焊盘142A用于连接至导电连接件144(见图14A)并且可以称为凸块下金属(UBM)142A。焊盘142B是集成组件150(见图15和图16)的一部分并且可以称为组件焊盘142B。在示出的实施例中，焊盘142形成为穿过介电层140至金属化图案138。作为形成焊盘142的实例，在介电层140上方形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。之后，在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于焊盘142。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。之后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成焊盘142。在实施例中，在不同地形成焊盘142的实施例中，可以使用更多的光刻胶和图案化步骤。
前侧再分布结构132示出为实例。可以在前侧再分布结构132中形成更多或更少的介电层和金属化图案。如果要形成更少的介电层和金属化图案，则可以省略以上讨论的步骤和工艺。如果要形成更多的介电层和金属化图案，则可以重复以上讨论的步骤和工艺。本领域普通技术人员将容易理解，可以省略或重复哪些步骤和工艺。
在图14A中，在UBM 142A上形成并且未在组件焊盘142B上形成导电连接件144。在一些实施例中，在导电连接件144的形成期间，组件焊盘142B由掩模(未示出)覆盖。导电连接件144可以是球栅阵列(BGA)连接件、焊球、金属柱、可控塌陷芯片连接(C4)凸块、微凸块、化学镀镍-化学镀钯浸金技术(ENEPIG)形成的凸块等。导电连接件144可以包括诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合的导电材料。在一些实施例中，可以通过首先由诸如蒸发、电镀、印刷、焊料转移、球植等常用的方法形成焊料层来形成导电连接件144。一旦已经在结构上形成焊料层，则可以实施回流以将材料成形为期望的凸块形状。在另一实施例中，导电连接件144是通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如铜柱)。金属柱可以是无焊料的并且具有基本垂直的侧壁。在一些实施例中，在金属柱连接件144的顶部上形成金属覆盖层(未示出)。金属覆盖层可以包括镍、锡、锡铅、金、银、钯、铟、镍-钯-金、镍-金等或它们的组合，并且可以通过镀工艺形成。
如图14A和图15所示，区域600和602的每个中的前侧再分布结构132包括至少一个集成组件150。在该实施例中，集成组件150是电感器。图15是示出集成组件150的区域600或602的一个中的集成组件150的平面图，其中，图14A中的截面图沿着图15的线A-A。集成组件150由金属化图案和通孔138和组件焊盘142B形成。金属化图案和通孔138以及组件焊盘142B形成多个同心环，其中，外环环绕内环。环具有断裂以允许外环通过桥152连接至内环，并且多个环(有时称为线圈)串联连接至两个端口155。
在示出的实施例中，组件焊盘142B在金属化图案和通孔138上方形成桥152，但是在其它实施例中，这种关系可以颠倒。桥152可以由不包括延伸穿过介电层140的通孔部分的组件焊盘142B的上部(介电层140的顶面上的线部分)形成。
图14B-1、图14B-2、图14B-3、图14B-4、图14B-5、图14B-6、图14B-7和图14B-8示出了开关电路的实施例的示例性示意图，该开关电路包括连接至开关电路的开关的电感器/变压器。在实施例中，集成电路管芯114包括射频器件开关157，电感器150通过管芯连接件126连接至射频器件开关157。集成至前侧再分布结构132的电感器150可以提供低成本和高性能电感器150以改进射频开关器件157的性能。射频器件开关157的改进性能可以包括改进的插入损耗和改进的隔离。例如，电感器150能够消除CMOS器件的寄生/耦合效应。此外，电感器150的导电材料形成为包括前侧再分布结构的通孔沟槽，其允许用于电感器环的较厚导体，这然后使得能够增加电感器的性能(例如，更高的Q因数)。
图14B-1示出了示例性开关电路，并且图14B-2示出了图14B-1中的电路的发送(Tx)模式和接收(Rx)模式的操作，其中，图14B-1中的顶部电路示出了Tx模式并且底部电路示出了Rx模式。
图14B-3示出了示例性开关电路，并且图14B-4示出了图14B-3中的电路的Tx模式和Rx模式的操作，其中，图14B-4中的顶部电路示出了Tx模式并且底部电路示出了Rx模式。
图14B-5示出了示例性开关电路，并且图14B-6示出了图14B-5中的电路的Tx模式和Rx模式的操作，其中，图14B-6中的顶部电路示出了Tx模式并且底部电路示出了Rx模式。
对于图14B-1、图14B-3和图14B-5中的每个电路，在Tx模式中，晶体管157-1导通并且晶体管157-2截止。对于这些电路的Rx模式，晶体管157-1截止并且晶体管157-2导通。这些配置在图14B-2、图14B-4和图14B-6中示出。
图14B-7和图14B-8示出了具有变压器配置的开关电路，而不是先前实例的电感器配置。对于图14B-7和图14B-8，在Tx模式中，晶体管157导通，并且在Rx模式中，晶体管157截止。
虽然图14B-1至图14B-8和图15示出了2匝电感器(即，具有两个环的电感器)，但是应当理解，可以在每个区域600和602的前侧再分布结构132中形成具有更多匝的电感器。例如，可以在每个区域600和602中形成三匝或四匝电感器。
图16是区域600或602的一个的示出了该区域中的多个电感器150的平面图。该平面图省略了前侧再分布结构132的介电层，并且也省略了前侧再分布结构132中的其它金属化图案。图14A中的截面图沿着图16的线A-A以平面图示出，其中，平面图16仅示出了一个集成电路管芯114。虽然图16示出了五个电感器150，但是在其它实施例中，可以根据集成电路和/或封装件的设计需要具有更多或更少的电感器150。此外，在一些实施例中，组件150中的一个或多个也可以是变压器(见例如图18A-1、图18A-2、图18B-1、图18B-2、图18B-3和图18B-4)。
在图17中，绝缘层146(有时称为保护层146)形成在前侧分布结构132、UBM 142A、组件焊盘142B上方，并且邻接和围绕导电连接件144。保护层146可以防止组件焊盘142B的氧化，并且可以在随后的回流期间为导电连接件144提供横向支撑。在实施例中，保护层146是非导电材料，诸如环氧树脂、树脂、聚酰亚胺、聚苯并恶唑(PBO)、苯并环丁烯(BCB)、硅树脂、丙烯酸酯、添加或没有添加硅基或玻璃填料的聚合物等或它们的组合。在一些实施例中，保护层146包括液态模塑料(LMC)，其在施加时为凝胶型液体。保护层146在施加时可以是液体或固体。可选地，保护层146可以包括其它绝缘和/或密封材料。在一些实施例中，使用晶圆级模塑工艺来施加保护层146。保护层146可以形成为具有在导电连接件144的顶点上方的顶面，与导电连接件144的顶点基本齐平的顶面或位于导电连接件144的顶点之下的顶面。保护层146可以使用例如压缩模塑、转移模塑或其它方法来模塑。
接下来，在一些实施例中，使用固化工艺来固化保护层146。固化工艺可以包括使用退火工艺或其它加热工艺将保护层146加热至预定温度预定时间段。固化工艺也可包括紫外(UV)曝光工艺、红外(IR)能量曝光工艺、它们的组合或它们与加热工艺的组合。可选地，可以使用其它方法固化保护层146。在一些实施方案中，不包括固化工艺。
在保护层146不是聚合物的实施例中，保护集成组件150免受氧化的成本减小，因为其它保护层材料比聚合物便宜。
在一些实施例中，组件150可以包括变压器，电感器或两者。图18A-1是区域600或602中的一个的示出多个组件150的平面图，其中，一个集成组件是电感器150A，并且另一组件是变压器150B。该平面图省略了前侧再分布结构132的介电层，并且也省略了前侧再分布结构132中的其它金属化图案。图18B-1中的截面图沿着图18A-1的线B-B。虽然图18A-1示出了一个电感器150A和一个变压器150B，但是在其它实施例中，可以根据集成电路和/或封装件的设计需要具有更多或更少的电感器150A和更多或更少的变压器150B。
图18A-2是区域600或602中的一个的示出多个组件150的平面图，其中，两个集成组件是变压器。该平面图省略了前侧再分布结构132的介电层，并且也省略了前侧再分布结构132中的其它金属化图案。图18B-2中的截面图沿着图18A-2的线D-D。图18B-3和图18B-4中的截面图是沿着图18A-2的线C-C的不同配置。虽然图18A-2示出了变压器150A和一个变压器150B，但是在其它实施例中，可以存在更多或更少的变压器，并且可以包括集成电路和/或封装件的设计所需的电感器。
图18B-1、图18B-2、图18B-3和图18B-4示出了与上面图17中的描述的工艺类似的工艺的中间阶段，并且此处不再重复该工艺的中间阶段的形成描述。在这些实施例中，组件150A/150B形成为变压器和/或电感器，其中，再分布结构的金属化图案和焊盘形成变压器和/或电感器的线圈。图18B-3中的实施例在再分布结构132中包括比其它实施例更多层级的金属化图案和介电层。但是其它实施例也可以包括与图示不同数量的层。
本发明的任何实施例可以包括再分布结构，该再分布结构包括一个或多个电感器、一个或多个变压器或它们的组合。
图19至图22示出了使用图17中的实施例作为实例的进一步操作和步骤，但是这些步骤也可以对图18B-1至图18B-4的实施例实施。
在图19中，实施载体衬底脱粘以将载体衬底100从背侧再分布结构110(例如，介电层104)分离(脱粘)。从而在第一封装区域600和第二封装区域602的每个中形成第一封装件200。根据一些实施例，脱粘包括将诸如激光或UV光的光投射到释放层102上，使得释放层102在光的热量下分解，并且可以去除载体衬底100。之后，翻转该结构并且放置在带176上。
在图20中，穿过介电层104形成暴露金属化图案106的部分的开口178。可以例如使用激光钻孔、蚀刻等形成开口178。
图21和图22示出了根据一些实施例的在用于形成封装结构的工艺期间的中间步骤的截面图。封装结构可以称为叠层封装(PoP)结构。
在图21中，将第二封装件300附接至第一封装件200。第二封装件300包括衬底302和连接至衬底302的一个或多个堆叠管芯308(308A和308B)。虽然示出了管芯308(308A和308B)的单个堆叠件，但是在其它实施例中，多个堆叠管芯308(每个均具有一个或多个堆叠管芯)可以并排设置为连接至衬底302的同一表面。衬底302可以由诸如硅、锗、金刚石等的半导体材料制成。在一些实施例中，也可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化镓铟、这些的组合等的化合物材料。此外，衬底302可以是绝缘体上硅(SOI)衬底。通常，SOI衬底包括诸如外延硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)或它们的组合的半导体材料层。在一个可选实施例中，衬底302是基于诸如玻璃纤维增强树脂芯的绝缘芯。芯材料的一个实例是诸如FR4的玻璃纤维树脂。芯材料的可选物质包括双马来酰亚胺-三嗪(BT)树脂或者其它印刷电路板(PCB)材料或薄膜。对于衬底302，可以使用诸如味之素积聚膜(ABF)或其它层压材料的积聚膜。
衬底302可以包括有源和无源器件(未示出)。如本领域普通技术人员将意识到，诸如晶体管、电容器、电阻器、这些的组合等的多种器件可以用于生成用于第二封装件300的设计的结构和功能需求。可以使用任何合适的方法形成该器件。
衬底302也可以包括金属化层(未示出)和通孔306。金属化层可以形成在有源和无源器件上方并且被设计为连接各个器件以形成功能电路。金属化层可以由电介质(例如，低k介电材料)和导电材料(例如，铜)(其具有互连导电材料层的通孔)的交替层形成，并且可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成。在一些实施例中，衬底302基本无有源和无源器件。
衬底302可以具有位于衬底302的第一侧上以连接至堆叠管芯308的接合焊盘303，以及位于衬底302的第二侧上以连接至导电连接件314的接合焊盘304，衬底302的第二侧与第一侧相对。在一些实施例中，通过在衬底302的第一侧和第二侧上的介电层(未示出)中形成凹槽(未示出)来形成接合焊盘303和304。凹槽可以形成为允许接合焊盘303和304嵌入至介电层内。在其它实施例中，由于接合焊盘303和304可以形成在介电层上，因此省略凹槽。在一些实施例中，接合焊盘303和304包括由铜、钛、镍、金、钯等或它们的组合制成的薄晶种层(未示出)。可以在薄晶种层上方沉积接合焊盘303和304的导电材料。可以通过电化学镀工艺、化学镀工艺、CVD、ALD、PVD等或它们的组合来形成导电材料。在实施例中，接合焊盘303和304的导电材料是铜、钨、铝、银、金等或它们的组合。
在实施例中，接合焊盘303和304是UBM，其包括三个导电材料层，诸如钛层、铜层和镍层。然而，本领域普通技术人员将意识到，存在适合于形成接合焊盘303和304的许多合适的材料和层布置，诸如铬/铬-铜合金/铜/金的布置、钛/钛钨/铜的布置或铜/镍/金的布置。可以用于接合焊盘303和304的任何合适的材料或材料层均完全旨在包括在本申请的范围内。在一些实施例中，通孔306穿过衬底302延伸并且将至少一个接合焊盘303连接至至少一个接合焊盘304。
在示出的实施例中，通过引线接合310将堆叠管芯308连接至衬底302，但是也可以使用诸如导电凸块的其它连接。在实施例中，堆叠管芯308是堆叠的存储器管芯。例如，堆叠管芯308可以是诸如低功率(LP)双数据率(DDR)存储器模块(诸如LPDDR1、LPDDR2、LPDDR3、LPDDR4等存储器模块)的存储器管芯。
堆叠管芯308和引线接合310可以由模塑材料312密封。可以例如使用压缩模塑将模塑材料312模塑在堆叠管芯308和引线接合310上。在一些实施例中，模塑材料312是模塑料、聚合物、环氧树脂、氧化硅填充材料等或它们的组合。可以实施固化步骤以固化模塑材料312，其中，固化可以是热固化、UV固化等或它们的组合。
在一些实施例中，将堆叠管芯308和引线接合310埋在模塑材料312中，并且在模塑材料312的固化之后，实施诸如研磨的平坦化步骤以去除模塑材料312的过量部分并且为第二封装件300提供基本平坦的表面。
在形成第二封装件300之后，通过导电连接件314、接合焊盘304和金属化图案106将第二封装件300机械和电接合至第一封装件200。在一些实施例中，可以通过引线接合310、接合焊盘303和304、通孔306、导电连接件314和通孔112将堆叠管芯308连接至集成电路管芯114。
导电连接件314可以与以上描述的导电连接件144类似，并且此处不再重复描述，但是导电连接件314和导电连接件144不需要是相同的。导电连接件314可以在开口178中设置在衬底302的与堆叠管芯308相对的侧上。在一些实施例中，焊剂(未单独标记)也可以形成在衬底的与堆叠管芯308相对的侧上。导电连接件314可以设置在焊剂中的开口中以电和机械连接至衬底302中的导电部件(例如，接合焊盘304)。焊剂可以用于保护衬底302的区免受外部损坏。
在一些实施例中，在接合导电连接件314之前，导电连接件314涂覆有焊剂(未示出)，诸如免洗焊剂。导电连接件314可以浸入焊剂中，或可以将焊剂喷射到导电连接件314上。在另一实施例中，可以将焊剂施加至金属化图案106的表面。
在一些实施例中，导电连接件314可以具有在其上形成的可选环氧树脂焊剂(未示出)，然后回流在将第二封装件300附接至第一封装件200之后剩余的环氧树脂焊剂的至少一些环氧树脂部分。
可以在第一封装件200和第二封装件300之间以及围绕导电连接件314形成底部填充物(未示出)。底部填充物可以减小应力并且保护由导电连接件314的回流产生的接头。底部填充物可以在附接第一封装件200之后通过毛细管流动工艺形成，或可以在附接第一封装件200之前通过合适的沉积方法形成。在形成环氧树脂焊剂的实施例中，环氧树脂焊剂可以用作底部填充物。
第二封装件300和第一封装件200之间的接合可以是焊料接合。在实施例中，通过回流工艺将第二封装件300接合至第一封装件200。在该回流工艺期间，导电连接件314与接合焊盘304和金属化图案106接触，以将第二封装件300物理和电连接至第一封装件200。在接合工艺之后，金属间化合物(IMC，未示出)可以形成在金属化图案106和导电连接件314的界面处并且也形成在导电连接件314和接合焊盘304之间的界面(未示出)处。
通过沿着划线区域(例如，在第一封装区域600和第二封装区域602之间)锯切来实施分割工艺。锯切分割第一封装区域600与第二封装区域602。产生来自第一封装区域600或第二封装区域602的一个的分割的第一封装件200和第二封装件300。在一些实施例中，在第二封装件300附接至第一封装件200之后实施分割工艺。在其它实施例(未示出)中，在将第二封装件300附接至第一封装件200之前，诸如在将载体衬底100脱粘并且形成开口178之后，实施分割工艺。
在图22中，使用导电连接件144将第一封装件200安装至封装衬底400。封装衬底400可以由诸如硅、锗、金刚石等的半导体材料制成。可选地，也可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化镓铟、这些的组合等的化合物材料。此外，封装衬底400可以是SOI衬底。通常，SOI衬底包括诸如外延硅、锗、硅锗、SOI、SGOI或它们的组合的半导体材料层。在一个可选实施例中，封装衬底400是基于诸如玻璃纤维增强树脂芯的绝缘芯。芯材料的一个实例是诸如FR4的玻璃纤维树脂。芯材料的可选物质包括双马来酰亚胺-三嗪(BT)树脂或者其PCB材料或薄膜。对于封装衬底400，可以使用诸如ABF或其它层压材料的积聚膜。
封装衬底400可以包括有源和无源器件(未示出)。如本领域普通技术人员将意识到，诸如晶体管、电容器、电阻器、这些的组合等的多种器件可以用于生成用于封装结构的设计的结构和功能需求。可以使用任何合适的方法形成该器件。
封装衬底400也可以包括金属化层和通孔(未示出)以及位于金属化层和通孔上方的接合焊盘402。金属化层可以形成在有源和无源器件上方并且被设计为连接各个器件以形成功能电路。金属化层可以由电介质(例如，低k介电材料)和导电材料(例如，铜)(其具有互连导电材料层的通孔)的交替层形成，并且可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成。在一些实施例中，封装衬底400基本无有源和无源器件。
在一些实施例中，回流导电连接件144以将第一封装件200附接至接合焊盘402。导电连接件144将包括封装衬底400中的金属化层的封装衬底400电和/或物理连接至第一封装件200。在一些实施例中，在安装在封装衬底400上之前，可以将无源器件(例如，未示出的表面安装器件(SMD))附接至第一封装件200(例如，接合至接合焊盘402)。在这种实施例中，无源器件可以与导电连接件144接合至第一封装件200的同一表面。
导电连接件144可以具有在其上形成的可选环氧树脂焊剂(未示出)，然后回流在将第一封装件200附接至封装衬底400之后剩余的环氧树脂焊剂的至少一些环氧树脂部分。该剩余的环氧树脂部分可以用作底部填充物以减小应力并且保护由导电连接件144的回流产生的接头。在一些实施例中，底部填充物(未示出)可以形成在第一封装件200和封装衬底400之间并且围绕导电连接件144。底部填充物可以在附接第一封装件200之后通过毛细管流动工艺形成，或可以在附接第一封装件200之前通过合适的沉积方法形成。
图23至图26示出了根据一些实施例的另一封装结构的截面图。图23至图26中的实施例与图1至图22中示出的实施例类似，除了该实施例包括集成天线，集成天线包括贴片天线和可选的辐射天线。贴片天线包括一条或多条信号线(这里也称为馈电线)、接地元件和一个或多个辐射元件。此处不再重复关于该实施例的与先前实施例的那些类似的细节。
图23示出了与上面图19中描述的工艺类似的工艺的中间阶段，并且此处不再重复该工艺的中间阶段的形成描述。在图23中，背侧再分布结构110包括金属化图案106，其可以是用于贴片天线的接地元件和馈电线。此外，在该实施例中，可以省略和/或去除背侧再分布结构上的介电层104。
在一些实施例中，每个区域600和602中的封装结构202均包括延伸穿过密封剂130的辐射天线216。在一些实施例中，辐射天线216是偶极天线。辐射天线216包括延伸穿过密封剂130的导电部件。这些导电部件可以与电连接件112同时并且通过相同的工艺形成。辐射天线216通过前侧再分布结构132中的金属化图案电连接至相应的集成电路管芯114。选择辐射天线的形状和配置，以能够向封装件202外部的其它器件(未示出)发送无线信号并且从封装件202外部的其它器件接收无线信号。在其它实施例中，可以省略辐射天线。
图24示出了对图23的结构的进一步处理。在图24中，在介电层104(如果存在)上方形成介电层210。在一些实施例中，介电层210包括相对低的消散因数(DF)材料以实现适当有效的贴片天线。例如，在一些实施例中，介电层210的DF可以小于约0.01或甚至小于约0.001。此外，介电层210的k值可以在从约3至约4的范围内。在实施例中，介电层210的厚度与贴片天线214(见图25)的工作频率有关。例如，介电层210的厚度可以与贴片天线214的工作频率成反比。在实施例中，当贴片天线214具有至少60GHz的工作频率时，介电层210的厚度可以在从约200μm至约300μm的范围内。可以使用诸如层压的任何合适的工艺形成介电层210。在其它实施例中，也可以使用其它沉积工艺(例如，PVD、CVD、旋涂技术等)。在包括辐射天线216的实施例中，密封剂130也可以由低DF材料形成。
在图25中，在介电层210上方形成贴片天线214的辐射元件212。在顶视图中，辐射元件212可以具有矩形形状并且与接地元件和馈电线106重叠，但是其它实施例中考虑了其它形状。辐射元件212可以包括诸如铜的任何合适的导电材料，但是在其它实施例中可以使用其它导电材料。可以通过粘合剂(未示出)将辐射元件212粘合在介电层210的表面上。在一些实施例中，粘合剂可以是环氧树脂，其在粘合在介电层210上之前施加至辐射元件212。之后可以将辐射元件212放置在介电层210上(例如，通过拾取和放置工具)，并且可以激活(例如，通过加热)粘合剂以将辐射元件212粘合在介电层210上。在其它实施例中，排除粘合剂并且将辐射元件212直接粘合至介电层210。在其它实施例中，使用不同的方法在介电层210上形成辐射元件212，例如，通过沉积晶种层，在晶种层上方形成图案化掩模以限定辐射元件212的图案，在图案化掩模的开口中镀辐射元件，以及去除图案化掩模和晶种层的过量部分。用于辐射元件212的其它沉积工艺也是可能的。
辐射元件212电连接至下面的接地元件和馈电线106，以用于发送和接收无线信号。因此，形成贴片天线214(包括接地元件和馈电线106、介电层210的部分和辐射元件212)。每个贴片天线214均与集成电路管芯114和电感器150集成在相同的半导体封装件中。介电部件116/108物理分隔开并且有助于将每个集成电路管芯114与相应的贴片天线214隔离以增加贴片天线214的效率。
在图26中，通过沿着划线区域(例如，在第一封装区域600和第二封装区域602之间)锯切来实施分割工艺。锯切分割第一封装区域600与第二封装区域602。产生来自第一封装区域600或第二封装区域602的一个的分割的封装件202。
在图26之后，可以进一步处理封装件202，诸如，如上面在图22中的先前实施例中描述的安装至封装衬底400，并且此处不再重复描述。
图27示出了根据一些实施例的分割的封装结构的截面图。该实施例与图1至图22中示出的实施例类似，除了该实施例省略电连接件112并且可以不包括第二封装件300之外。此处不再重复关于该实施例的与先前实施例的那些类似的细节。
该实施例可以通过图1至图18B-4中描述的类似工艺形成(除了省略电连接件112和背侧再分布结构110之外)，并且此处不再重复描述。封装结构可以类似地形成为晶圆级，并且之后在形成保护层146之后分割。
图28示出了根据一些实施例的另一封装结构的截面图。该实施例与图1至图22中示出的实施例类似，除了该实施例仅用保护层146部分地覆盖晶圆级结构。通过用保护层146仅覆盖组件焊盘142B，可以减小封装结构的成本。此处不再重复关于该实施例的与先前实施例的那些类似的细节。
图28示出了与上面图18B-4中描述的工艺类似的工艺的中间阶段，并且此处不再重复该工艺的中间阶段的形成描述。在图28中，保护层146仅形成为覆盖组件焊盘142B并且不覆盖整个前侧再分布结构132。该实施例仍为集成组件150提供氧化保护，并且与图1至图22的实施例相比也节省了成本。
在图28之后，可以如上面参照图19至图22中描述的进一步处理封装结构，并且此处不再重复描述。
图29至图34示出了根据一些实施例的另一封装结构的截面图。图29至图34中的实施例与图28中示出的实施例类似，除了该实施例包括位于前侧再分布结构132的邻近集成组件150的介电材料中的开口158(例如，气隙)。这些邻近集成组件150的介电材料中的开口158可以减小电感器的寄生电容。包括开口/气隙的实施例可以改进集成组件150的Q因数并且也可以提高集成组件150的自谐振频率。此处不再重复关于该实施例的与先前实施例的那些类似的细节。
图29示出了与上面图8中描述的工艺类似的工艺的中间阶段，并且此处不再重复该工艺的中间阶段的形成描述。
在图30中，图案化介电层136。图案化形成暴露通孔112和管芯连接件126的部分的开口。可以通过可接受的工艺图案化，诸如当介电层136是感光材料时通过将介电层136暴露于光或通过例如使用各向异性蚀刻的蚀刻。如果介电层136是感光材料，则可以在曝光之后显影介电层136。
该图案化步骤与上面在图9中描述的步骤类似，但是在图30的实施例中存在额外的开口154，该开口154将用于在集成组件150周围形成气隙。
图31和图32示出了与上面图10和11中描述的工艺类似的工艺的中间阶段，并且此处不再重复这些工艺的中间阶段的形成描述。在该实施例中，因为在介电层136中形成额外的开口154并且在那些开口154中没有形成金属化图案或通孔，所以在介电层140中存在凹槽156。
在图33中，之后，图案化介电层140。图案化形成暴露金属化图案138的部分的开口和暴露凹槽156的开口158。该同一图案化工艺也图案化了位于凹槽156之下的下面的介电层136以形成开口158。开口158从介电层140的顶面延伸至密封剂130。可以通过可接受的工艺图案化，诸如当介电层140是感光材料时通过将介电层140暴露于光或通过例如使用各向异性蚀刻的蚀刻。如果介电层140是感光材料，则可以在曝光之后显影介电层140。
在图34中，形成保护层146以覆盖焊盘142B。与图28的实施例类似，保护层146仅形成为覆盖焊盘142B并且不覆盖整个前侧再分布结构132。该实施例仍为组件150提供氧化保护并且与图1至图22的实施例相比节省了成本。
在图34之后，可以如上面参照图19至图22中的描述进一步处理封装结构，并且此处不再重复描述。
图35至图37示出了根据一些实施例的另一封装结构的截面图。图35至图37中的实施例与图1至图22中示出的实施例类似，除了在该实施例中，省略了保护层146并且再分布结构132包括覆盖焊盘142B的另一介电层160。此处不再重复关于该实施例的与先前实施例的那些类似的细节。
图35示出了与上面图13中描述的工艺类似的中间阶段，并且此处不再重复该工艺的中间阶段的形成描述。
在图35中，在介电层140上形成具有通孔的金属化图案161。焊盘142B形成为金属化图案161的一部分。作为形成金属化图案161的实例，在介电层140上方并且在穿过介电层140的开口中形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。之后，在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案161。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。之后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成金属化图案161和通孔。在穿过介电层140至例如金属化图案138的开口中形成通孔。
在图36中，在介电层140和金属化图案161上方形成介电层160。用于形成介电层160的材料和工艺可以与介电层140类似，此处不再重复描述。
此外，在图36中，之后图案化介电层160。图案化形成暴露金属化图案161的部分的开口。可以通过可接受的工艺图案化，诸如当介电层160是感光材料时通过将介电层160暴露于光或通过例如使用各向异性蚀刻的蚀刻。如果介电层160是感光材料，则可以在曝光之后显影介电层160。
图37示出了对图36的结构的进一步处理。该工艺与上面图13和图14A中描述的工艺类似，并且此处不再重复描述。在该实施例中，焊盘162在功能上与焊盘142A类似，并且导电连接件164在功能上与导电连接件144类似。
图38示出了根据一些实施例的另一封装结构的截面图。图38中的实施例与图35至图37中示出的实施例类似，除了在该实施例中，组件150不包括金属化图案138处的通孔而仅包括金属化图案138。此处将不再重读关于该实施例的与先前描述的实施例的那些类似的细节。
实施例可以实现许多优势。本文讨论的实施例包括封装结构(例如，InFO封装结构)，该封装结构具有集成至再分布结构的诸如电感器、变压器或两者的组件。集成至再分布结构的组件可以提供低成本和高性能组件，以改进射频开关器件的性能。射频天线开关的改进性能可以包括改进的插入损耗和改进的隔离。例如，电感器能够消除CMOS器件的寄生/耦合效应。此外，公开的实施例包括保护层以防止电感器的导电材料的氧化。而且，公开的实施例包括将形成在再分布结构的通孔沟槽中的电感器的导电材料，以使电感器具有更高的品质(Q)因数，并且也可以改进变压器的性能。此外，在一些实施例中，可以去除邻近组件的再分布结构的介电材料(例如，邻近组件形成气隙)，以减小组件的寄生电容。包括气隙的实施例可以改进电感器的Q因数并且还可以提高电感器的自谐振频率。与没有电感器和/或变压器的射频开关器件相比，包括连接至射频器件开关的电感器的公开的实施例可以允许射频开关器件具有更低的功率损耗和更高的隔离度。
实施例是器件，包括具有有源侧和背侧的集成电路管芯，背侧与有源侧相对；密封集成电路管芯的模塑料以及位于集成电路管芯和模塑料上面的第一再分布结构，第一再分布结构包括第一金属化图案和第一介电层，第一金属化图案电连接至集成电路管芯的有源侧，第一金属化图案的至少部分形成电感器。
实施例可包括以下特征的一个或多个。该器件还包括位于第一再分布结构上方的导电连接件，导电连接件电连接至第一金属化图案，以及位于第一再分布结构上方并且邻近导电连接件的保护层，保护层位于电感器上方并且接触电感器。在该器件中，保护层接触并且围绕导电连接件。在该器件中，保护层延伸横跨整个第一再分布结构。在该器件中，保护层具有与第一介电层不同的材料组分。在该器件中，第一再分布结构的第一金属化图案的至少部分形成变压器。该器件还包括延伸穿过模塑料的第一通孔，第一通孔电连接至第一再分布结构的第一金属化图案。该器件还包括位于集成电路管芯下方的第二再分布结构，第二再分布结构包括第二金属化图案和第二介电层，第二金属化图案电连接至通孔，第二金属化图案的至少部分形成天线。该器件还包括延伸穿过模塑料的第二通孔，第二通孔电连接至第一再分布结构的第一金属化图案，第二通孔是天线的一部分。该器件还包括延伸穿过第一介电层的第一开口，第一开口邻近第一再分布结构中的电感器。
实施例是方法，包括用模塑料密封集成电路管芯，在集成电路管芯和模塑料上方形成第一介电层，在第一介电层中形成第一导电通孔，第一导电通孔电连接至集成电路管芯的第一管芯连接件，在第一介电层中形成第二导电通孔，第二导电通孔位于邻近集成电路管芯的模塑料上方，在第一介电层上方形成第一金属化图案，在第一介电层、第一导电通孔、第二导电通孔和第一金属化图案上方形成第二介电层，在第二介电层中形成第三导电通孔，第三导电通孔电连接至第一金属化图案，其中，第一导电通孔、第二导电通孔、第一金属化图案和第三导电通孔形成电感器或变压器，并在第三导电通孔和第二介电层上方形成绝缘层，绝缘层覆盖第三导电通孔。
实施例可包括以下特征的一个或多个。该方法还包括在第二介电层中形成凸块下金属，以及在凸块下金属上方形成电连接至凸块下金属的导电连接件。在该方法中，绝缘层与凸块下金属和导电连接件接触。在该方法中，绝缘层具有与第二介电层不同的材料组分。该方法还包括形成穿过第一和第二介电层的开口，该开口位于第二和第三导电通孔之间。该方法还包括在第一介电层、第一导电通孔和第二导电通孔上方形成第三介电层，第二介电层位于第三介电层上方，第一金属化图案和第三导电通孔直接位于第二导电通孔上面。该方法还包括在密封集成电路管芯之前，形成第一再分布结构，第一再分布结构包括第二金属化图案和第三介电层，并且在密封集成电路管芯之前，在第一再分布结构的第二金属化图案上方形成电连接至第一再分布结构的第二金属化图案的第一电连接件，模塑料密封第一电连接件，集成电路管芯和模塑料位于第一再分布结构上方，第一电连接件延伸穿过模塑料并且电连接至第一金属化图案。
实施例是方法，包括形成第一封装件，包括在载体衬底上方形成电连接件，使用粘合层将第一管芯的背侧附接至载体衬底，第一管芯邻近电连接件，用模塑料密封第一管芯和电连接件，在第一管芯、模塑料和电连接件上方形成第一再分布结构，电连接件电连接到第一再分布结构，第一再分布结构包括第一集成组件，第一集成组件是电感器或变压器，以及去除载体衬底。
实施例可包括以下特征的一个或多个。该方法还包括使用第一组导电连接件将第二封装件接合至第一封装件，第二封装件靠近第一管芯的背侧，第二封装件包括一个或多个管芯。在该方法中，形成第一封装件还包括在形成电连接件之前，在载体衬底上方形成第二再分布结构，电连接件电连接至第二再分布结构，其中，去除载体衬底暴露第二再分布结构，在去除载体衬底之后，在暴露的第二再分布结构上形成介电层，以及在介电层、第二再分布结构、介电层上形成导电元件，并且导电元件形成贴片天线。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种半导体器件，包括：
集成电路管芯，具有有源侧和背侧的，所述背侧与所述有源侧相对；
模塑料，密封所述集成电路管芯；以及
第一再分布结构，位于所述集成电路管芯和所述模塑料上面，所述第一再分布结构包括第一金属化图案和第一介电层，所述第一金属化图案电连接至所述集成电路管芯的有源侧，所述第一金属化图案的至少部分形成电感器。
2.根据权利要求1所述的器件，还包括：
导电连接件，位于所述第一再分布结构上方，所述导电连接件电连接至所述第一金属化图案；以及
保护层，位于所述第一再分布结构上方并且邻近所述导电连接件，所述保护层位于所述电感器上方并且接触所述电感器。
3.根据权利要求2所述的器件，其中，所述保护层接触并且围绕所述导电连接件。
4.根据权利要求2所述的器件，其中，所述保护层延伸横跨整个所述第一再分布结构。
5.根据权利要求2所述的器件，其中，所述保护层具有与所述第一介电层不同的材料组分。
6.根据权利要求1所述的器件，其中，所述第一再分布结构的所述第一金属化图案的至少部分形成变压器。
7.一种形成半导体器件的方法，包括：
用模塑料密封集成电路管芯；
在所述集成电路管芯和所述模塑料上方形成第一介电层；
在所述第一介电层中形成第一导电通孔，所述第一导电通孔电连接至所述集成电路管芯的第一管芯连接件；
在所述第一介电层中形成第二导电通孔，所述第二导电通孔位于邻近所述集成电路管芯的所述模塑料上方；
在所述第一介电层上方形成第一金属化图案；
在所述第一介电层、所述第一导电通孔、所述第二导电通孔和所述第一金属化图案上方形成第二介电层；
在所述第二介电层中形成第三导电通孔，所述第三导电通孔电连接至所述第一金属化图案，其中，所述第一导电通孔、所述第二导电通孔、所述第一金属化图案和所述第三导电通孔形成电感器或变压器；以及
在所述第三导电通孔和所述第二介电层上方形成绝缘层，所述绝缘层覆盖所述第三导电通孔。
8.根据权利要求7所述的方法，还包括：
在所述第二介电层中形成凸块下金属；以及
在所述凸块下金属上方形成电连接至所述凸块下金属的导电连接件。
9.一种形成半导体器件的方法，包括：
形成第一封装件，包括：
在载体衬底上方形成电连接件；
使用粘合层将第一管芯的背侧附接至所述载体衬底，所述第一管芯邻近所述电连接件；
用模塑料密封所述第一管芯和所述电连接件；
在所述第一管芯、所述模塑料和所述电连接件上方形成第一再分布结构，所述电连接件电连接至所述第一再分布结构，所述第一再分布结构包括第一集成组件，所述第一集成组件是电感器或变压器；以及
去除所述载体衬底。
10.根据权利要求9所述的方法，还包括：
使用第一组导电连接件将第二封装件接合至所述第一封装件，所述第二封装件靠近所述第一管芯的背侧，所述第二封装件包括一个或多个管芯。
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