CN113113382A - 封装结构、封装件及其形成方法 - Google Patents

封装结构、封装件及其形成方法 Download PDF

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Publication number
CN113113382A
CN113113382A CN202110060927.4A CN202110060927A CN113113382A CN 113113382 A CN113113382 A CN 113113382A CN 202110060927 A CN202110060927 A CN 202110060927A CN 113113382 A CN113113382 A CN 113113382A
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redistribution
conductive
layer
die
substrate
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CN202110060927.4A
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吴俊毅
余振华
刘重希
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN113113382A publication Critical patent/CN113113382A/zh
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Abstract

在实施例中，一种结构包括：芯衬底；耦合的再分布结构，该再分布结构包括多个再分布层，该多个再分布层包括介电层和金属化层，该再分布结构还包括嵌入在多个再分布层的第一再分布层中的第一局部互连组件，该第一局部互连组件包括导电连接件，该导电连接件接合至第一再分布层的金属化图案，该第一再分布层的介电层密封第一局部互连组件；耦合至再分布结构的第一集成电路管芯；耦合至再分布结构的第二集成电路管芯，该第一局部互连组件的互连结构将第一集成电路管芯电耦合至第二集成电路管芯；以及耦合至芯衬底的第二侧的一组导电连接件。本申请的实施例还涉及封装结构、封装件及其形成方法。

Description

封装结构、封装件及其形成方法
技术领域
本申请的实施例涉及封装结构、封装件及其形成方法。
背景技术
由于各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的不断提高，半导体工业经历了快速的增长。在大多数情况下，集成密度的提高来自最小部件尺寸的迭代减小，从而可以将更多组件集成至给定区域中。随着对缩小电子器件的需求的增长，对更小且更具创造性的半导体管芯封装技术的需求也随之出现。这种封装系统的实例是叠层封装(PoP)技术。在PoP器件中，顶部半导体封装件堆叠在底部半导体封装件的顶部上，以提供高水平度的集成和组件密度。PoP技术通常能够在印刷电路板(PCB)上产生功能增强且占位面积小的半导体器件。
发明内容
本申请的一些实施例提供了一种封装结构，包括：芯衬底；再分布结构，耦合至所述芯衬底的第一侧，所述再分布结构包括：多个再分布层，所述多个再分布层中的每一个包括介电层和金属化层；以及第一局部互连组件，嵌入所述多个再分布层的第一再分布层中，所述第一局部互连组件包括衬底、所述衬底上的互连结构以及导电连接件，所述导电连接件接合至所述第一再分布层的金属化层，所述第一再分布层的所述金属化层包括第一导线和第一导电通孔，所述第一再分布层的所述介电层密封所述第一局部互连组件；第一集成电路管芯，耦合至所述再分布结构，所述再分布结构插入在所述芯衬底与所述第一集成电路管芯之间；第二集成电路管芯，耦合至所述再分布结构，所述再分布结构插入在所述芯衬底与所述第一集成电路管芯之间，所述第一局部互连组件的所述互连结构将所述第一集成电路管芯电耦合至所述第二集成电路管芯；以及导电连接件组，耦合至所述芯衬底的第二侧。
本申请的另一些实施例提供了一种形成封装件的方法，包括：在第一载体衬底上方形成第一再分布结构，其中，形成所述第一再分布结构包括：在所述第一载体衬底上方形成第一组导线；在所述第一组导线上方形成电耦合至所述第一组导线的第一组导电通孔；将第一互连管芯接合至所述第一组导线，所述第一互连管芯包括衬底、所述衬底上的互连结构以及所述互连结构上的管芯连接件，所述管芯连接件接合至所述第一组导线，所述第一互连管芯在所述第一组导电通孔中的两个之间；在所述第一组导线、所述第一组导电通孔和所述第一互连管芯上方形成第一介电层，所述第一介电层、所述第一组导电通孔、所述第一组导线和所述第一互连管芯形成第一再分布层；以及在所述第一再分布层上方形成第二再分布层，所述第二再分布层包括第二介电层、第二组导电通孔和第二组导线，所述第二组导线中的至少一个电耦合至所述第一组导电通孔中的至少一个；去除所述第一载体衬底；将芯衬底电连接至所述第一再分布结构的第一侧，所述第二再分布层比所述第一再分布层更靠近所述第一再分布层的所述第一侧；以及将第一集成电路管芯和第二集成电路管芯接合至所述第一再分布结构的第二侧，所述第二侧与所述第一侧相对，所述第一集成电路管芯和所述第二集成电路管芯电耦合至所述第一互连管芯。
本申请的又一些实施例提供了一种封装件，包括：第一再分布结构，所述第一再分布结构包括多个再分布层，所述多个再分布层中的每一个包括金属化图案和介电层，所述多个再分布层中的第一再分布层包括第一介电层和第一互连管芯，所述第一互连管芯包括衬底、在所述衬底上的互连结构以及在所述互连结构上的管芯连接件，所述管芯连接件接合至所述第一再分布层的金属化图案，所述第一再分布层的所述金属化图案包括第一导线和第一导电通孔，所述第一介电层密封所述第一互连管芯；芯衬底，使用第一组导电连接件耦合至所述第一再分布结构的第一侧，所述第一再分布结构的宽度大于芯衬底的宽度；以及集成电路管芯封装件，使用第二组导电连接件耦合至所述第一再分布结构的第二侧，所述第二侧与所述第一侧相对。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1示出根据一些实施例的封装组件的截面图。
图2示出根据一些实施例的图1的截面图的一部分的详细视图。
图3示出根据一些实施例的封装组件的平面图。
图4至图18和图21至图23示出根据一些实施例的在形成封装组件的工艺期间的中间步骤的截面图。
图19示出根据一些实施例的封装区在晶圆衬底上的布局的平面图。
图20示出根据一些实施例的封装区在面板衬底上的布局的平面图。
图24至图29示出根据一些实施例的在形成封装组件的工艺期间的中间步骤的截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个组件或部件与另一个(或另一些)组件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
可以在特定的上下文中讨论本文讨论的实施例，即，封装组件具有一个或多个集成电路管芯。在一些实施例中，封装组件是集成衬底上系统(SoIS)封装件。封装组件包括嵌入再分布结构中的局部互连组件。嵌入的局部互连组件在集成电路管芯之间提供电连接。嵌入的局部互连组件增加了集成电路管芯之间的通信带宽，同时保持了低接触电阻和高可靠性。低接触电阻和高可靠性至少部分归因于嵌入的局部互连组件与再分布结构之间的无焊料连接。在一些实施例中，其他组件(诸如，集成稳压器、集成有源器件、静态随机存取存储器等或其组合)也可以以与嵌入的局部互连组件类似的方式来嵌入。
再分布结构连接至集成电路管芯，并在集成电路管芯与芯衬底之间和/或集成电路管芯之间提供电连接。芯衬底还连接至外部导电部件组。以这种方式，集成电路管芯通过芯衬底和再分布结构电连接至芯衬底，并且最终电连接至外部导电部件。
根据一些实施例，在组装完整封装组件之前，可以分别制造和测试再分布结构、嵌入的局部互连组件、芯衬底和集成电路管芯。这进一步提高了组件级和板级可靠性。
由于由局部互连组件提供的集成电路管芯之间的通信带宽的增加，因此在集成电路管芯与再分布结构之间不需要中介层。通过消除中介层的需要，减小了集成电路封装件(包括集成电路管芯)与芯衬底封装件(包括芯衬底和再分布结构)之间的翘曲失配，因为减小了这两种封装结构之间的热膨胀系数(CTE)失配。
根据一些实施例，用于将芯衬底连接至再分布结构的导电连接件可以采取例如球栅阵列(BGA)的形式。此类导电连接件的集成可为诸如集成有源器件(IPD)芯片、集成稳压器(IVR)、有源芯片等半导体器件以及其他电组件的放置提供灵活性，以实现封装组件的芯片上系统类型，从而降低了制造复杂性。此类实施例还可以为各种其他封装件配置提供更大的灵活性。
图1示出根据一些实施例的分割的封装组件100的截面图。图2示出根据一些实施例的图1的截面图的一部分的详细视图。分割的封装组件100包括半导体器件(例如，集成电路封装件500)、具有一个或多个再分布层的再分布结构200、芯衬底300和外部连接件620，以及其他组件。集成电路封装件500可以包括一个或多个管芯，诸如逻辑管芯(例如，中央处理单元(CPU)、图形处理单元(GPU)、片上系统(SoC)、应用处理器(AP)、微控制器等)、存储器管芯(例如，动态随机存取存储器(DRAM)单元、静态随机存取存储器(SRAM)单元等)、电源管理管芯(例如，电源管理集成电路(PMIC)单元)、射频(RF))管芯、传感器管芯、微机电系统(MEMS)管芯、信号处理管芯(例如，数字信号处理(DSP)管芯)、前端管芯(例如，模拟前端(AFE))、模具等或其组合。在一些实施例中，半导体器件可以是集成电路管芯。
集成电路封装件500可以包括多个集成电路管芯。如图所示，出于说明性目的，集成电路封装件500包括一个或多个逻辑管芯512、一个或多个存储器管芯514，以及一个或多个输入/输出(I/O)管芯516(图1中未示出，参见图3)。集成电路管芯可以形成在一个或多个晶圆中，这些晶圆可以包括在后续步骤中分割的不同的器件区。可以使用已知的制造技术将集成电路管芯与其他类似或不同的集成电路管芯封装在一起。在一些实施例中，集成电路管芯512、514和516使用如下参考图7所述的类似工艺和技术形成。
在一些实施例中，集成电路管芯512、514和516中的一个或多个可以是包括多个半导体衬底的堆叠器件。例如，存储器管芯514可以是包括多个存储器管芯的存储器件，诸如混合存储器立方(HMC)模块、高带宽存储器(HBM)模块等。在此类施例中，存储器管芯514包括通过衬底通孔(TSV)互连的多个半导体衬底。每个半导体衬底可以具有(或可以不具有)互连结构。
管芯512、514和516具有接合至导电连接件188的接合焊盘518。在一些实施例中，接合焊盘518由导电材料制成，并且可以类似于下面描述的导线(例如，参见导线110)。
导电连接件188在再分布结构200与集成电路封装件500之间提供电连接。可以包括底部填充物610以将集成电路封装件500牢固地接合至再分布结构200，并提供结构支撑和环境保护。
如下面更详细讨论，再分布结构200通过导电连接件390在集成电路封装件500与芯衬底300之间提供电路径和电连接。在一些实施例中，再分布结构200具有一个或多个包括金属化图案的再分布层，包括例如导线110和116以及导电通孔106和112，以及将导线110和116的相邻层分开的介电层108和114。
如下面更详细地讨论，再分布结构200包括一个或多个局部互连组件120。局部互连组件120在集成电路封装件500的集成电路管芯512、514和516之间提供电布线和电连接，并且可以被称为互连管芯120。局部互连组件120在保持低接触电阻和高可靠性的同时增加了集成电路管芯512-516之间的通信带宽。低接触电阻和高可靠性至少部分归因于嵌入的局部互连组件与再分布结构之间的无焊料连接。如图1和图2所示，局部互连组件120通过无焊料的导电连接件136连接至再分布结构200的金属化图案116。在一些实施例中，局部互连组件120通过铜-铜接合嵌入在再分布结构200内。在一些实施例中，局部互连组件120通过混合接合嵌入在再分布结构200内。
由于由局部互连组件提供的集成电路管芯之间的通信带宽的增加，因此在集成电路管芯与再分布结构之间不需要中介层。通过消除中介层的需要，由于减小了这两种封装结构之间的热膨胀系数(CTE)失配，因此减小了集成电路封装件(包括集成电路管芯)与芯衬底封装件(包括芯衬底和再分布结构)之间的翘曲失配。
再分布结构200可以电气地和机械地附接至芯衬底300。芯衬底300可以包括中央芯310，其中，导电通孔320延伸穿过中央芯310，以及沿着中央芯310的相对侧的附加的可选的再分布结构340。通常，芯衬底300为组件封装提供结构支撑，以及在集成电路封装件与外部连接件80之间提供电信号路由。
密封剂380可以包括在再分布结构200与芯衬底300之间，以牢固地接合相关的组件并提供结构支撑和环境保护。
图3示出根据一些实施例的封装组件的平面图。图3所示的实施例包括两个逻辑管芯512、四个存储器管芯514、两个I/O管芯516和七个局部互连组件120。在该实施例中，每个存储器管芯514和I/O管芯516通过相应的局部互连组件120连接至逻辑管芯512中的至少一个。此外，两个逻辑管芯通过局部互连组件120连接在一起。其他实施例可以包括或多或少的逻辑管芯512、存储器管芯514、I/O管芯516和局部互连组件120。在一些实施例中，每个集成电路管芯通过局部互连组件连接至每个相邻的集成电路管芯。
图4至图16示出根据一些实施例的在制造再分布结构200(参见图16)中的各个中间阶段。示出第一封装区101A和第二封装区101B，其中，每个封装区最终都与其他封装区分离。为了易于说明，在图4至图16中简化了各个部件的图示。
首先参考图4，提供了载体衬底102，在载体衬底102上形成释放层104，并且在释放层104上方形成导电通孔106。载体衬底102可以是玻璃载体衬底、陶瓷载体衬底等。载体衬底102可以是晶圆，使得可以在载体衬底102上同时形成多个再分布结构。
释放层104可以由基于聚合物的材料形成，其可以与载体衬底102一起从将在后续步骤中形成的上覆结构中去除。在一些实施例中，释放层104是基于环氧的热释放材料，其在加热时会失去其粘合特性，诸如光热转换(LTHC)释放涂层。在其他实施例中，释放层104可以是紫外线(UV)胶，当暴露于UV光时其失去粘合性。释放层104可以以液体的形式分配并固化，可以是层压在载体衬底102上的层压膜，或者可以是类似物。在工艺变化内，释放层104的顶面可以是水平的并且基本是平面的。
在图4中，导电通孔106形成在释放层104上。导电通孔106可随后通过载流子脱粘工艺而暴露，并用于提供至再分布结构200的连接。导电通孔106形成用于再分布层90的金属化图案。作为形成导电通孔106的实例，在释放层104上方形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。晶种层可以是例如钛层和在钛层上方的铜层。可以使用例如物理气相沉积(PVD)等形成晶种层。然后，在晶种层上形成光刻胶并对其图案化。可以通过旋涂等形成光刻胶，并且可以将其暴露于光以用于图案化。图案化形成穿过光刻胶的开口以暴露晶种层，其中，光刻胶中的开口对应于导电通孔106。然后在光刻胶的开口中和晶种层的暴露部分上形成导电材料。导电材料可以通过镀覆形成，镀覆诸如电镀、化学镀覆等。导电材料可以包括金属，像铜、钛、钨、铝等。导电材料和晶种层下面的部分的组合形成导电通孔106。去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺，诸如使用氧等离子体等，来去除光刻胶。在去除光刻胶之后，诸如通过使用可接受的蚀刻工艺，诸如通过湿或干蚀刻，去除晶种层的暴露部分。
在图5中，根据一些实施例，在导电通孔106上和周围形成介电层108，并且在介电层108和导电通孔106上形成导线110。形成之后，介电层108围绕导电通孔106。介电层108可以提供电气隔离和环境保护。介电层108和金属化图案(包括导电通孔106)形成再分布层90。介电层108可以是聚合物，诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等；氮化物，诸如氮化硅等；氧化物，诸如氧化硅、磷硅玻璃(PSG)、硼硅玻璃(BSG)、掺硼磷硅玻璃(BPSG)等；类似物；或其组合。介电层108可以例如通过旋涂、层压、化学气相沉积(CVD)等形成。在工艺变化内，介电层108可以具有基本水平的上表面。在一些实施例中，介电层形成为厚度在2μm至50μm的范围内。
在形成介电层108之后，在介电层108和导电通孔106上形成导线110。作为形成导线110的示例，在介电层108和导电通孔106上方形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。晶种层可以是例如钛层和在钛层上方的铜层。可以使用例如PVD等形成晶种层。然后，在晶种层上形成光刻胶并对其图案化。可以通过旋涂等形成光刻胶，并且可以将其暴露于光以用于图案化。图案化形成穿过光刻胶的开口以暴露晶种层，其中，光刻胶中的开口对应于导线110。然后在光刻胶的开口中和晶种层的暴露部分上形成导电材料。导电材料可以通过镀覆形成，镀覆诸如电镀、化学镀覆等。导电材料可以包括金属，像铜、钛、钨、铝等。导电材料和晶种层下面的部分的组合形成导电通孔106。去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺，诸如使用氧等离子体等，来去除光刻胶。在去除光刻胶之后，诸如通过使用可接受的蚀刻工艺，诸如通过湿或干蚀刻，去除晶种层的暴露部分。
在图6中，根据一些实施例，在导线110上形成导电通孔112，并且在导电通孔112和导线110上和周围形成介电层114。导线110和导电通孔112一起形成用于再分布层92的金属化图案。导电通孔112可以类似于上述导电通孔106，并且在此不再重复描述。介电层114可以类似于上述介电层108，并且在此不再重复描述。介电层114和金属化图案(包括导电通孔112和导线110)形成再分布层92。在一些实施例中，导电通孔106和112具有的宽度在2μm至50μm的范围内。
此外，在图6中，形成导线116和导电通孔118。导线116形成在导电通孔112上方并连接至导电通孔112，并且导电通孔118形成在导线116上方并连接至导线116。导线116和导电通孔118一起形成用于再分布层94的金属化图案。导线116和导电通孔118可以类似于上述导线110和导电通孔106，并且在此不再重复描述。在一些实施例中，导电通孔118的高度比导电通孔106和112的高度更大，因为导电通孔118用作邻近随后附接的局部互连组件120的介电质通孔。在一些实施例中，导电通孔118的宽度在5μm至100μm的范围内。
图7示出根据一些实施例的局部互连组件120的截面图。将在再分布结构200中的后续处理中嵌入局部互连组件120。
局部互连组件120可以形成在晶圆中，该晶圆可以包括不同的器件区，这些器件区在后续步骤中被分割以形成多个局部互连组件。可以根据适用的制造工艺来处理局部互连组件120以形成管芯。例如，局部互连组件120包括衬底122，诸如掺杂或未掺杂的硅，或绝缘体上半导体(SOI)衬底的有源层。衬底122可以包括其他半导体材料，诸如锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或其组合。在一些实施例中，衬底122可以由陶瓷材料、聚合物膜、磁性材料等或其组合制成。也可以使用其他衬底，诸如多层或梯度衬底。衬底122具有源表面(例如，在图7中面向上的表面)，有时被称为正面，以及无源表面(例如，在图7中面向下的表面)，有时被称为后侧。
在一些实施例中，局部互连组件120可以包括有源或无源器件。在一些实施例中，局部互连组件120可以没有有源或无源器件，并且可以仅用于电信号的路由。在包括有源或无源器件的实施例中，可以在半导体衬底122的前表面处形成器件(由晶体管表示)124。器件124可以是有源器件(例如，晶体管、二极管等)、电容器、电阻器、电感器等。层间电介质(ILD)126在半导体衬底122的前表面上方。ILD 126围绕器件124并且可以覆盖器件124。ILD126可以包括由诸如磷硅玻璃(PSG)、硼硅玻璃(BSG)、硼掺杂磷硅玻璃(BPSG)、未掺杂硅酸盐玻璃(USG)等材料形成的一个或多个介电层。
导电插塞128延伸穿过ILD 126，以电耦合和物理耦合器件124。例如，当器件124是晶体管时，导电插塞128可以耦合晶体管的栅极和源极/漏极区。导电插塞128可以由钨、钴、镍、铜、银、金、铝等或其组合形成。互连结构130在ILD 126和导电插塞128上方。互连结构130使器件124互连和/或在管芯连接件136之间提供电布线和电连接。互连结构130可以例如使用镶嵌工艺由例如ILD 126上的介电层中的金属化图案形成。金属化图案包括形成在一个或多个低k介电层中的金属线和通孔。在包括器件124的实施例中，互连结构130的金属化图案通过导电插塞128电耦合至器件124。尽管示出的互连结构130仅具有两层导电通孔和两层导线，但是在一些实施例中，根据需要可以包括更多或更少层的导电通孔和导线。例如，由于局部互连组件120用于集成电路封装件500的管芯之间的电连接，因此局部互连组件120的互连结构130通常将具有更多的互连层，以容纳该电连接。
局部互连组件120还包括与外部连接的焊盘132，诸如铝焊盘。焊盘132在局部互连组件120的有源侧上，诸如在互连结构130中和/或上。一个或多个钝化膜134在局部互连组件120上，诸如在互连结构130和焊盘132的部分上。开口穿过钝化膜134延伸至焊盘132。诸如导电柱(例如，由诸如铜等金属形成)的管芯连接件136延伸穿过钝化膜134中的开口，并且物理耦合和电耦合至相应焊盘132。管芯连接件136可以通过例如镀覆等形成。管芯连接件136电耦合局部互连组件120的相应集成电路。
可选地，可以在焊盘132上布置焊料区(例如，焊球或焊料凸块)。焊球可以用于在局部互连组件120上执行芯片探针(CP)测试。可以在局部互连组件120上执行CP测试，以确定局部互连组件120是否是已知良好管芯(KGD)。因此，仅封装经过后续处理的作为KGD的局部互连组件120，并且不封装未通过CP测试的管芯。在测试之后，可以在随后的处理步骤中去除焊料区。
介电层138可以(或可以不)在局部互连组件120的有源侧上，诸如在钝化膜134和管芯连接件136上。介电层138横向密封管芯连接件136，并且介电层138与局部互连组件120横向相接。最初，介电层138可以掩埋管芯连接件136，使得介电层138的最上表面在管芯连接件136的最上表面上方。在焊料区布置在管芯连接件136上的一些实施例中，介电层138也可以掩埋焊料区。可选地，可以在形成介电层138之前去除焊料区。
介电层138可以是聚合物，诸如PBO、聚酰亚胺、BCB等；氮化物，诸如氮化硅等；氧化物，诸如氧化硅、PSG、BSG、BPSG等；类似物；或其组合。介电层138可以例如通过旋涂、层压、化学气相沉积(CVD)等形成。在一些实施例中，在局部互连组件120的形成期间，管芯连接件136通过介电层138暴露。暴露管芯连接件136可以去除管芯连接件136上可能存在的任何焊料区。
在一些实施例中，管芯连接件136和介电层138可以以混合接合配置使用，以将局部互连组件120接合至结构。在其他实施例中，局部互连组件120以金属-金属接合配置(例如，铜-铜接合)接合。在一些实施例中，管芯连接件136的间距在20μm至80μm的范围内。
在图8中，局部互连组件120接合至再分布结构200的导线116。在一些实施例中，局部互连组件120通过混合接合而接合。在混合接合实施例中，介电层139至少横向地围绕导线116形成。介电层139可以在导线116之前或之后形成。介电层139可以类似于介电层138，并且在此不再重复描述。
为了实现混合接合，首先通过将再分布结构200的局部互连组件120和导线116轻压在一起，通过它们的绝缘层(例如，138和129)预接合再分布结构200的局部互连组件120和导线116。
在所有局部互连组件120都被预接合之后，执行加热工艺以引起管芯连接件136的导电材料(例如，铜)和导线116的相互扩散。根据本发明的一些实施例，绝缘层138和139中的一个或两个包括聚合物。因此，退火温度降低到低于约230℃，以避免绝缘层的损伤。例如，退火温度可以在约150℃至约230℃之间的范围内。退火时间可以在约1小时至3小时之间。
通过混合接合，管芯连接件136和导线116通过诸如铜-铜接合的金属-金属接合而彼此接合，以形成接合接头。局部互连组件120的绝缘层138也通过在绝缘层139之间形成的键而接合至绝缘层139。例如，一个绝缘层中的原子(诸如，氧原子)与另一个绝缘层中的原子(诸如，氢原子)形成化学键或共价键(诸如，O-H键)。绝缘层之间的所得键为电介质-电介质键，根据各种实施例，其可以是无机物-聚合物键、聚合物-聚合物键或无机物-无机物键。此外，表面绝缘层138和139可以彼此不同(例如，一个是聚合物层，另一个是无机层)，因此可以存在两种类型的无机物-聚合物、聚合物-聚合物和无机物-无机物键同时存在于同一封装件中。
在一些实施例中，导电通孔118与局部互连组件120间隔开距离D1。在一些实施例中，距离D1为至少5μm。在一些实施例中，距离D1在5μm至2000μm的范围内。
在图9中，根据一些实施例，在导电通孔118和局部互连组件120上和周围形成介电层140。介电层140密封局部互连组件120和导电通孔118。介电层140、局部互连组件120和金属化图案(包括导电通孔118和导线116)形成再分布层94。介电层140(以及再分布层154、158、162、166和170的介电层)的材料可以与介电层108和114的材料不同。
已经观察到，通过将导电通孔118与局部互连120间隔开至少5μm，可以改善介电层140的形成。D1至少为5μm使得在局部互连件120与导电通孔118之间更均匀地形成介电层140(例如，没有空隙、间隙和/或接缝)，这改善了介电层140的介电性质。通过改善介电层140的覆盖率和/或均匀性，改善了封装结构的电性能。
在一些实施例中，介电层140可以由预浸料、味之素堆积膜(ABF)、树脂涂覆的铜(RCC)、模塑料、聚酰亚胺、光可成像电介质(PID)、环氧树脂等形成，并且可以通过压缩模制、传递模制等施加。可以以液体或半液体形式施加密封剂，然后将其固化。在一些实施例中，介电层140形成在介电层114上方，使得导线110、导电通孔118和局部互连组件被掩埋或覆盖，然后在介电层140上执行平坦化工艺以暴露导电通孔118和局部互连组件120的衬底122的背面。介电层140、导电通孔118和局部互连组件120的衬底122的最上表面在平坦化工艺之后在工艺变化内基本是水平的(例如，平面的)。平坦化工艺可以是例如化学机械抛光(CMP)。在一些实施例中，介电层140可以包括其他材料，诸如氧化硅、氮化硅等。在平坦化工艺之后(如果有的话)，局部互连组件的厚度在10μm至100μm的范围内。在一些实施例中，局部互连组件120的衬底122的厚度在2μm至30μm范围内，并且管芯连接件136的高度在1μm至20μm范围内。
局部互连组件120在随后附接的集成电路管芯(例如，512、514和516)之间提供电连接。嵌入的局部互连组件120增加了集成电路管芯之间的通信带宽，同时保持了低接触电阻和高可靠性。低接触电阻和高可靠性至少部分归因于嵌入的局部互连组件与再分布结构之间的无焊料连接。在一些实施例中，其他组件(诸如，集成稳压器、集成有源器件、静态随机存取存储器等或其组合)也可以以与嵌入的局部互连组件类似的方式来嵌入。
在图10中，导线142形成在介电层140和导电通孔118上并连接至导电通孔118。导线142可以类似于上述导线110，并且在此不再重复描述。
在图11中，导电通孔144形成在导线142上并从导线142延伸。导电通孔144可以类似于上述导电通孔106，并且在此不再重复描述。导线142和导电通孔144一起形成用于再分布层150的金属化图案。
在图12中，根据一些实施例，在导线142和导电通孔144上和周围形成介电层146。形成之后，介电层146围绕导电通孔144和导线142。介电层146和金属化图案(包括导电通孔144和导线142)形成再分布层150。介电层146可以类似于上述介电层140，并且在此不再重复描述。在一些实施例中，介电层146形成在介电层140和局部互连组件120上方，使得导线142和导电通孔144被掩埋或覆盖，然后在介电层146上执行平坦化工艺以暴露导电通孔144。介电层146和导电通孔144的最上表面在平坦化工艺之后在工艺变化内基本是水平的(例如，平面的)。平坦化工艺可以是例如CMP。在一些实施例中，介电层146可以包括其他材料，诸如氧化硅、氮化硅等。
在图13中，重复上面讨论的形成再分布层150的步骤和工艺，以形成另外示出的再分布层154、158、162、166和170。在一些实施例中，可以将上述形成再分布层150的工艺重复一次或多次，以提供特定设计150、154、158、162、166和170 140所期望的附加布线层。出于说明的目的，示出了九个再分布层90、92、94、150、154、158、162、166和170。在一些实施例中，可以使用多于或少于九个再分布层。每个再分布层90、92、94、150、154、158、162、166和170的金属化图案可以具有分别形成的导线和导电通孔(如图所示)，或者每个再分布层可以是具有线和通孔部分的单个图案。
在一些实施例中，另一组导线174形成在每个导电通孔171和最上面的再分布层(例如，在所示的实施例中的再分布层170)中的介电层172的一部分上方。该另一组导线174为连接芯衬底提供了更大的尺寸，如下所述。
在使用密封剂和随后的CMP工艺来平坦化再分布层150、154、158、162、166和170的情况下，可以很好地控制相关层的尺寸和粗糙度，并且更容易地将其构建成更大的厚度。在一些实施例中，再分布层150、154、158、162、166和170的厚度分别在5μm和100μm之间。可以通过分别重复或省略上述步骤和工艺来形成更多或更少的再分布层。
尽管图4至图13示出在围绕导线和通孔的介电层之前形成导线和通孔的形成工艺，但是其他形成工艺也在本发明的范围内。例如，在其他实施例中，首先形成介电层，然后形成金属化图案(包括线和通孔两者)。金属化图案包括沿着介电层的主表面延伸并且延伸穿过介电层以物理耦合和电耦合至下面的导电层的导电组件。作为形成金属化图案的实例，在需要通孔的位置形成穿过介电层的开口，并且在介电层上方和穿过介电层延伸的开口中形成晶种层。然后，在晶种层上形成光刻胶并对其图案化。图案化形成穿过光刻胶的开口以暴露晶种层，其中，开口的图案对应于金属化图案。然后在光刻胶的开口中和晶种层的暴露部分上形成导电材料。导电材料可以通过镀覆形成，镀覆诸如电镀、化学镀覆等。导电材料可以包括金属，像铜、钛、钨、铝等。导电材料和晶种层下面的部分的组合形成金属化图案。去除光刻胶和晶种层上未形成导电材料的部分。在去除光刻胶之后，诸如通过使用可接受的蚀刻工艺，诸如通过湿或干蚀刻，去除晶种层的暴露部分。介电层和金属化图案的组合形成再分布层。
在图14中，执行载体衬底脱粘以将载体衬底102与介电层108和导电通孔106分离(或“脱粘”)。根据一些实施例，脱粘包括在释放层104上投射诸如激光或UV光等光，使得释放层104在光的热量下分解并且可以去除载体衬底102。然后将结构翻转并放置在另一个载体衬底180和释放层182上。
如果需要，可以在介电层108和导电通孔106(以及任何剩余的释放层104)上执行平坦化工艺以暴露导电通孔106。介电层108和导电通孔106的最上表面在平坦化工艺之后在工艺变化内基本是水平的(例如，平面的)。平坦化工艺可以是例如化学机械抛光(CMP)、研磨工艺等。在一些实施例中，例如，如果导电通孔106已经暴露，则可以省略平坦化。可以使用其他工艺来实现类似的结果。例如，在脱粘工艺之后，可以在导电通孔106上方形成介电层或钝化层。在这种情况下，可以在后续步骤中对介电层或钝化层进行图案化，以暴露导电通孔106的部分。
在图15中，形成了凸块下金属化(UBM)186(有时称为焊盘186)，用于外部连接至导电通孔106。UBM 186具有在介电层108的主表面上并沿着介电层108的主表面延伸的凸块部分，并且可以具有延伸到介电层108中的通孔部分，以物理耦合导和电耦合导电通孔106。结果，UBM 186通过导线110和局部互连组件120电耦合。UBM 186可以由与导电通孔106相同的材料形成。
在图15中，导电连接件188形成在UBM 186上。导电连接件188允许与管芯或另一封装结构的物理连接和电连接。导电连接件188可以是球栅阵列(BGA)连接件、焊球、金属柱、受控塌陷芯片连接(C4)凸块、微凸块、无电镀钯浸金(ENEPIG)形成的凸块等。导电连接件188可以包括导电材料，诸如焊料、铜、铝、金、镍、银、钯、锡等或其组合。在一些实施例中，通过蒸发、电镀、印刷、焊料转移、焊球放置等首先形成焊料层来形成导电连接件188。在结构上形成焊料层之后，可以执行回流，以将材料成形为期望的凸块形状。在另一实施例中，导电连接件188包括通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如，铜柱)。金属柱可以是无焊料的并且具有基本竖直的侧壁。在一些实施例中，在金属柱的顶部上形成金属保护层。金属保护层可以包括镍、锡、锡铅、金、银、钯、铟、镍-钯-金、镍-金等或其组合，并且可以通过镀覆工艺形成。
在图16中，执行载体衬底脱粘以将载体衬底180与导线174和/或介电层172分离(或“脱粘”)。根据一些实施例，脱粘包括在释放层182上投射诸如激光或UV光等光，使得释放层182在光的热量下分解并且可以去除载体衬底180。然后将该结构翻转并放置在框架190上。
此外，在图16中，可以将集成有源器件(IPD)192接合至导线174。IPD 192可以以与局部互连组件120类似的方式形成，并且可以包括一个或多个无源器件，诸如电容器、电阻器、电感器、类似物，或其组合。在一些实施例中，IPD 192以与以上针对局部互连组件120描述的类似方式混合接合至导线174，并且在此不再重复描述。
在图17中，示出芯衬底300，在图18中，该芯衬底300接合再分布结构200。利用芯衬底300具有使芯衬底300以单独的工艺制造的优点。另外，由于芯衬底300是以单独的工艺形成，因此可以单独地对其进行测试，从而使用已知良好芯衬底300。例如，在一些实施例中，在将芯衬底300接合至再分布结构200之前，可以对芯衬底300进行单独或批量测试、校验和/或验证。
芯衬底300可以是例如有机衬底、陶瓷衬底、硅衬底等。导电连接件365用于将芯衬底300附接至再分布结构200。附接芯衬底300可以包括将芯衬底300放置在再分布结构200上并且使导电连接件365回流，以物理耦合和电气耦合芯衬底300和再分布结构200。
在附接至再分布结构200之前，可以根据适用的制造工艺来处理芯衬底300，以在芯衬底300中形成再分布结构。例如，芯衬底300包括芯310。芯310可以由玻璃纤维、树脂、填料、预浸料、环氧树脂、二氧化硅填料、味之素堆积膜(ABF)、聚酰亚胺、模塑料、其他材料和/或其组合的一层或多层形成。在一些实施例中，例如，两层材料构成芯310。芯310可以由有机和/或无机材料形成。在一些实施例中，芯310包括嵌入在内部的一个或多个无源组件(未示出)。芯310可以包括其他材料或组件。导电通孔320形成为延伸穿过芯310。导电通孔320包括导电材料320A，诸如铜、铜合金或其他导体，并且在一些实施例中，可以包括阻挡层(未示出)、衬垫(未示出)、晶种层(未示出)和/或填充物材料320B。导电通孔320提供从芯310的一侧到芯310的另一侧的竖直电连接。例如，一些导电通孔320耦合在芯310的一侧的导电部件与芯310的相对侧的导电部件之间。例如，可以使用钻孔工艺、光刻、激光工艺或其他方法形成用于导电通孔320的孔，然后用导电材料填充或镀覆导电通孔320的孔。在一些实施例中，导电通孔320是中空的导电通孔，其中心填充有绝缘材料。再分布结构340A和340B形成在芯310的相对侧上。再分布结构340A和340B通过导电通孔320和扇入/扇出电信号电耦合。
再分布结构340A和340B各自包括由ABF、预浸料等形成的介电层以及金属化图案。每个相应的金属化图案具有在相应的介电层的主表面上并沿着其延伸的线部分，并且具有延伸穿过相应的介电层的通孔部分。再分布结构340A和340B各自分别包括用于外部连接的凸块下金属(UBM)330A和330B，以及保护再分布结构340A和340B的部件的阻焊剂350A和350B。如图11所示，UBM 330A通过导电连接件365将再分布结构340A附接至再分布结构200。与图11所示相比，可以在再分布结构340A和340B中形成更多或更少的介电层和金属化图案。
芯衬底300可以包括有源和无源器件(未示出)，或者可以没有有源器件、无源器件或两者。可以使用多种器件，诸如晶体管、电容器、电阻器、电感器，其组合等。可以使用任何合适的方法来形成器件。
导电连接件365可以用于将芯衬底300A和300B接合至再分布结构200，如图18所示。导电连接件365可以首先形成在芯衬底300A和300B或再分布结构200上，然后回流以完成接合。例如，在图18所示的实施例中，在底部再分布结构340A的UBM 330A上以介于150μm至1000μm之间的间距形成导电连接件365。导电连接件365可以是球栅阵列(BGA)连接件、焊球、金属柱、受控塌陷芯片连接(C4)凸块、微凸块、无电镀钯浸金(ENEPIG)形成的凸块等。导电连接件365可以包括导电材料，诸如焊料、铜、铝、金、镍、银、钯、锡等或其组合。在一些实施例中，通过蒸发、电镀、印刷、焊料转移、焊球放置等首先形成焊料层来形成导电连接件365。在结构上形成焊料层之后，可以执行回流，以将材料成形为期望的凸块形状。在另一实施例中，导电连接件365包括通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如，铜柱)。金属柱可以是无焊料的并且具有基本竖直的侧壁。在一些实施例中，在金属柱的顶部上形成金属保护层。金属保护层可以包括镍、锡、锡铅、金、银、钯、铟、镍-钯-金、镍-金等或其组合，并且可以通过镀覆工艺形成。
在图18中，芯衬底300A和300B分别接合至第一封装区101A和第二封装区101B中的再分布结构200(例如，参见图16)。在一些实施例中，芯衬底300A与相邻的芯衬底300B分开的距离D1为约25μm至约1,000μm。该距离在第一封装区101A与第二封装区101B之间提供了空间，用于在随后的工艺中将再分布结构200分割为单独的封装件。在诸如图18所示的实施例中，芯衬底300A和300B的尺寸D3分别小于第一封装区101A和第二封装区101B的尺寸D2，以允许在不损伤芯衬底300A和300B的情况下进行密封和分割。在一些实施例中，在芯衬底300A和300B与再分布结构200之间利用高度为20μm至500μm的支座。
在一些实施例中，可以使用拾取和放置工艺或另一合适的工艺将芯衬底300A和300B放置在再分布结构200上，并且通过倒装芯片接合工艺或其他合适的接合工艺来接合导电连接件365。在一些实施例中，导电连接件365被回流以通过金属化图案174将芯衬底300A和300B附接至再分布结构200。导电连接件365将芯衬底300A和300B电耦合和/或物理耦合至再分布结构200。
导电连接件365可以在其回流之前在其上形成环氧焊剂(未示出)，在将芯衬底300A和300B附接至再分布结构200之后残留环氧焊剂的环氧部分的至少一部分。
如上所述，再分布结构200可以更大并且包括多个封装区，诸如第一封装区101A和第二封装区101B。例如，图19示出具有多个封装区的圆形晶圆形状的再分布结构200。在所示的实施例中，在晶圆上包括四个封装区101A、101B、101C和101D，从而允许在单个晶圆上制造四个最终封装组件，然后将其分割。在其他实施例中，可以在单个晶圆上利用更少或更多的封装区。该工艺中的后续步骤使用晶圆形式框架190上的再分布结构200作为基础，在该基础上继续下面进一步详细描述的制造工艺。如下面进一步详细描述，通过沿着线401并且围绕封装区101A、101B、101C和101D的外边缘进行锯切来分割各个封装区。
图20示出使用具有多个封装区的面板形式的制造工艺来制造再分布结构200。在所示的实施例中，晶圆上包括九个封装区101A至101I，从而允许在单个晶圆或面板上制造九个最终封装组件。在其他实施例中，可以在单个晶圆或面板上利用更少或更多的封装区。该工艺中的后续步骤使用面板形式框架190上的再分布结构200作为基础，在该基础上继续下面进一步详细描述的制造工艺。如下面进一步详细描述，通过沿着线402并围绕封装区101A至101I的周边进行锯切来分割各个封装区。
在图21中，通过在各个组件上和周围形成密封剂380来执行密封。形成之后，密封剂380围绕芯衬底300A和300B，芯衬底300A和300B包括导电连接件365、金属化图案174和介电层172的上暴露表面。密封剂380可以由模塑料、环氧树脂等形成，并且可以通过压缩模制，传递模制等施加。密封剂380可以以液体或半液体形式施加，随后固化。密封剂380可以形成在框架190上方，使得芯衬底300A和300B被掩埋或覆盖。
在图22中，如果需要，可以在密封剂380上执行平坦化工艺以暴露芯衬底300A和300B的UBM 330。密封剂380和UBM 330的最上表面在平坦化工艺之后在工艺变化内基本是水平的(例如，平面的)。平坦化工艺可以是例如化学机械抛光(CMP)、研磨工艺等。在一些实施例中，例如，如果UBM 330已经暴露，则可以省略平坦化。可以使用其他工艺来实现类似的结果。例如，可以在形成密封剂380之前在UBM 330上方形成介电层或钝化层。在这种情况下，可以在后续步骤中对介电层或钝化层进行图案化，以暴露UBM 330的一部分。
在图23中，将该结构从框架190去除，并翻转到框架390上。在一些实施例中，框架190和390是相同的框架。
此外，在图23中，通过沿着例如第一封装区101A与第二封装区101B之间的划线区进行锯切来执行分割处理。锯切将第一封装区101A与包括第二封装区101B(示出)的相邻封装区分开，以形成多个分割的封装组件100。如图23所示，芯衬底300的侧壁被密封剂380覆盖，从而在分割期间和之后保护芯衬底300A和300B的侧壁。
如图1所示，集成电路封装件500可以通过导电连接件188附接至分割的封装组件100。导电连接件188将集成电路封装件500附接至分割的封装组件100的UBM 186和再分布结构200。附接集成电路封装件500可以包括将集成电路封装件500的管芯512、514和516放置在导电连接件188上，并且使导电连接件188回流以将集成电路封装件500和分割的封装组件100物理耦合和电耦合。
在一些实施例中，如图1所示，在集成电路封装件500与再分布结构200之间围绕导电连接件188形成底部填充物610。底部填充物610可以减小应力并保护由导电连接件188的回流形成的接头。底部填充物610可以在附接集成电路封装件500之后通过毛细管流动工艺形成，或者可以通过适当的沉积方法形成。在一些实施例中，单层底部填充物610形成在多个相邻器件下方，并且其他后续底部填充物(未示出)或密封剂(未示出)可以形成在放置在分割的封装组件100顶部上的附加器件下方和/或周围。
如图1所示，外部连接件620形成在芯衬底300的UBM 330B上。外部连接件620可以是球栅阵列(BGA)连接件、焊球、金属柱、受控塌陷芯片连接(C4)凸块、微凸块等。外部连接件620可以包括导电材料，诸如焊料、铜、铝、金、镍、银、钯、锡等或其组合。在一些实施例中，首先通过蒸发、电镀、印刷、焊料转移、焊球放置等在UBM 330上形成可回流材料层来形成外部连接件620。在UBM 330B上形成可回流材料的层之后，可以执行回流以将材料成形为期望的凸块形状。
图24至图29示出根据一些实施例的在制造再分布结构700(参见图29)中的各个中间阶段。再分布结构700类似于再分布结构200，例外是在该实施例中，再分布结构层以不同的顺序形成。例如，在该实施例中，该工艺开始于包括导线116、导电通孔118、局部互连组件120和介电层140的层，而不是再分布层90和92。与先前描述的实施例相似的关于该实施例的细节在此将不再重复。
示出第一封装区101A和第二封装区101B，其中，每个封装区最终都与其他封装区分离。为了易于说明，在图24至图29中简化了各个部件的图示。
在图24至图26中，再分布层94形成在载体衬底102上方的释放层104上方。在图24中，导线116形成在释放层上方，导电通孔118形成在导线116上。这些结构已在上文先前实施例中描述，并且这里不再重复描述。
在图25中，局部互连组件120通过管芯连接件136连接至导线116。局部互连组件120类似于以上在先前实施例中描述的局部互连组件120，并且在此不再重复描述。
在一些实施例中，如先前实施例中所述，通过混合接合来接合局部互连组件120。在一些实施例中，局部互连组件仅通过导线116和管芯连接件136通过金属-金属的接合来接合。在仅金属-金属的实施例中，底部填充物710可以形成在局部互连组件120和释放层104之间并且围绕管芯连接件136和导线116。底部填充物710可以类似于上述的底部填充物610，并且在此不再重复描述。
在图26中，根据一些实施例，在导电通孔118和局部互连组件120上和周围形成介电层140。介电层140密封局部互连组件120和导电通孔118。先前已经描述了介电层140，并且在此不再重复描述。
在一些实施例中，然后在介电层140上执行平坦化工艺以暴露导电通孔118和局部互连组件120的衬底122的背面。介电层140、导电通孔118和局部互连组件120的衬底122的最上表面在平坦化工艺之后在工艺变化内基本是水平的(例如，平面的)。
在图27中，再分布层150、154、158、162、166和170形成在介电层140、局部互连组件120和导电通孔118上方。这些结构已在上文先前实施例中描述，并且这里不再重复描述。
在一些实施例中，另一组导线174形成在每个导电通孔171和最上面的再分布层(例如，在所示的实施例中的再分布层170)中的介电层172的一部分上方。该另一组导线174为连接芯衬底提供了更大的尺寸，如下所述。
在图28中，执行载体衬底脱粘以将载体衬底102与介电层140和导电通孔116分离(或“脱粘”)。根据一些实施例，脱粘包括在释放层104上投射诸如激光或UV光等光，使得释放层104在光的热量下分解并且可以去除载体衬底102。然后将结构翻转并放置在另一个载体衬底180和释放层182上。
在图29中，形成再分布层90和92以形成再分布结构700。具体地，导电通路112、介电层114、导线110、导电通路106、UBM 186和导电连接件188形成在暴露的介电层140、导线116和底部填充物710上方。这些结构已在上文先前实施例中描述，并且这里不再重复描述。
该再分布结构700将按照先前实施例中所述进行后续处理，以实现图1所示的结构，使得将图1中的再分布结构200替换为再分布结构700。
也可以包括其他部件和工艺。例如，可以包括测试结构以辅助3D封装件或3DIC器件的验证测试。测试结构可以包括例如形成在再分布层中或衬底上的测试焊盘，其允许测试3D封装件或3DIC，使用探针和/或探针卡等。验证测试可以在中间结构以及最终结构上执行。另外，本文公开的结构和方法可以与结合了已知良好模具的中间验证的测试方法结合使用，以增加产量并降低成本。
实施例可以实现优点。例如，局部互连组件增加了集成电路管芯之间的通信带宽，同时保持了低接触电阻和高可靠性。低接触电阻和高可靠性至少部分归因于嵌入的局部互连组件与再分布结构之间的无焊料连接。此外，在组装完成的封装组件之前，可以分别制造和测试再分布结构、嵌入局部互连组件、芯衬底和集成电路管芯。这进一步提高了组件级和板级可靠性。由于由局部互连组件提供的集成电路管芯之间的通信带宽增加，因此在集成电路管芯和再分布结构之间不需要中介层。通过消除中介层的需要，减小了集成电路封装件(包括集成电路管芯)与芯衬底封装件(包括芯衬底和再分布结构)之间的翘曲失配，因为减小了这两种封装结构之间的热膨胀系数(CTE)失配。
在实施例中，一种结构包括：芯衬底；再分布结构，耦合至所述芯衬底的第一侧，所述再分布结构包括：多个再分布层，所述多个再分布层中的每一个包括介电层和金属化层；第一局部互连组件，嵌入所述多个再分布层的第一再分布层中，所述第一局部互连组件包括衬底、所述衬底上的互连结构以及导电连接件，所述导电连接件接合至所述第一再分布层的金属化层，所述第一再分布层的所述金属化层包括第一导线和第一导电通孔，所述第一再分布层的所述介电层密封所述第一局部互连组件；第一集成电路管芯，耦合至所述再分布结构，所述再分布结构插入在所述芯衬底与所述第一集成电路管芯之间；第二集成电路管芯，耦合至所述再分布结构，所述再分布结构插入在所述芯衬底与所述第一集成电路管芯之间，所述第一局部互连组件的所述互连结构将所述第一集成电路管芯电耦合至所述第二集成电路管芯；以及一组导电连接件，耦合至所述芯衬底的第二侧。
实施例可包括以下特征中的一个或多个。所述结构，其中，使用第一焊料连接将所述再分布结构耦合至所述芯衬底的所述第一侧。所述结构还包括：密封剂，插入在所述再分布结构与所述芯衬底之间。所述结构，其中，所述密封剂沿着所述芯衬底的侧壁延伸。所述结构还包括：集成有源器件，耦合至所述再分布结构，所述集成有源器件插入在所述再分布结构与所述芯衬底之间。所述第一局部互连组件混合接合至所述第一再分布层的所述金属化图案和介电层。所述第一局部互连组件的所述互连结构在所述第一局部互连组件的所述衬底的第一侧上，所述第一局部互连组件的所述第一侧面向所述第一集成电路管芯。所述第一局部互连组件的所述衬底是硅衬底。
在实施例中，一种方法包括：在第一载体衬底上方形成第一再分布结构，其中，形成所述第一再分布结构包括：在所述第一载体衬底上方形成第一组导线。所述方法还包括：在所述第一组导线上方形成第一组导电通孔，并将所述第一组导电通孔电耦合至所述第一组导线。所述方法还包括：将第一互连管芯接合至所述第一组导线，所述第一互连管芯包括衬底、所述衬底上的互连结构以及所述互连结构上的管芯连接件，所述管芯连接件接合至所述第一组导线，所述第一互连管芯在所述第一组导电通孔中的两个之间。所述方法还包括：在所述第一组导线、所述第一组导电通孔和所述第一互连管芯上方形成第一介电层，所述第一介电层、所述第一组导电通孔、所述第一组导线和所述第一互连管芯形成第一再分布层。所述方法还包括：在所述第一再分布层上方形成第二再分布层，所述第二再分布层包括第二介电层、第二组导电通孔和第二组导线，所述第二组导线中的至少一个电耦合至所述第一组导电通孔中的至少一个。所述方法还包括：去除所述第一载体衬底。所述方法还包括：将芯衬底电连接至所述第一再分布结构的第一侧，所述第二再分布层比所述第一再分布层更靠近所述第一再分布层的所述第一侧。所述方法还包括：将第一集成电路管芯和第二集成电路管芯接合至所述第一再分布结构的第二侧，所述第二侧与所述第一侧相对，所述第一集成电路管芯和所述第二集成电路管芯电耦合至所述第一互连管芯。
实施例可包括以下特征中的一个或多个。所述方法还包括在将所述芯衬底电连接至所述第一再分布结构的所述第一侧之后，在所述芯衬底周围形成第一密封剂。所述方法还包括：在所述芯衬底周围形成所述第一密封剂之后，分割穿过所述第一再分布结构和所述第一密封剂。将所述第一互连管芯接合至所述第一组导线包括混合接合工艺。所述方法还包括：在所述第一载体衬底上方形成第三再分布层，所述第一再分布层在所述第三再分布层上方形成，所述第三再分布层包括第三介电层和第三组导电通孔，所述第三组导电通孔中的至少一个电耦合至所述第一组导线中的至少一个，所述第三再分布层在所述第一集成电路管芯与所述第一再分布层之间。所述第三介电层由与所述第一介电层不同的材料制成。所述方法还包括：在去除所述第一载体衬底之后，在电连接所述芯衬底之前，在所述第一再分布层上形成第三再分布层，所述第一再分布层在所述第三再分布层与所述第二再分布层之间，所述第三再分布层包括第三介电层和第三组导电通孔，所述第三组导线中的至少一条电耦合至所述第一组导线中的至少一条，所述第三再分布层在所述第一集成电路管芯与所述第一再分布层之间。
在实施例中，一种封装件包括：第一再分布结构，所述第一再分布结构包括多个再分布层，所述多个再分布层中的每一个包括金属化图案和介电层，所述多个再分布层中的第一再分布层包括第一介电层和第一互连管芯，所述第一互连管芯包括衬底、在所述衬底上的互连结构以及在所述互连结构上的管芯连接件，所述管芯连接件接合至所述第一再分布层的金属化图案，所述第一再分布层的所述金属化图案包括第一导线和第一导电通孔，所述第一介电层密封所述第一互连管芯。所述封装件还包括：芯衬底，其使用第一组导电连接件耦合至所述第一再分布结构的第一侧，所述第一再分布结构的宽度大于芯衬底的宽度。所述封装件还包括：集成电路管芯封装件，其使用第二组导电连接件耦合至所述第一再分布结构的第二侧，所述第二侧与所述第一侧相对。
实施例可包括以下特征中的一个或多个。所述第一组导电连接件和所述第二组导电连接件各自包括焊料，并且其中，在没有焊料的情况下，所述第一互连管芯的所述管芯连接件接合至所述第一再分布层的所述金属化图案。所述封装件还包括：插入在所述芯衬底与所述第一再分布结构之间的密封剂。所述第一再分布结构还包括：第二再分布层，所述第二再分布层在所述第一再分布层与所述集成电路管芯封装件之间，所述第二再分布层包括第二介电层，所述第二介电层的材料与所述第一介电层的材料不同。所述第一再分布结构还包括：第一组件，在所述多个再分布层中的一个内，所述第一组件是集成稳压器、集成有源器件或静态随机存取存储器。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种封装结构，包括：
芯衬底；
再分布结构，耦合至所述芯衬底的第一侧，所述再分布结构包括：
多个再分布层，所述多个再分布层中的每一个包括介电层和金属化层；以及
第一局部互连组件，嵌入所述多个再分布层的第一再分布层中，所述第一局部互连组件包括衬底、所述衬底上的互连结构以及导电连接件，所述导电连接件接合至所述第一再分布层的金属化层，所述第一再分布层的所述金属化层包括第一导线和第一导电通孔，所述第一再分布层的所述介电层密封所述第一局部互连组件；
第一集成电路管芯，耦合至所述再分布结构，所述再分布结构插入在所述芯衬底与所述第一集成电路管芯之间；
第二集成电路管芯，耦合至所述再分布结构，所述再分布结构插入在所述芯衬底与所述第一集成电路管芯之间，所述第一局部互连组件的所述互连结构将所述第一集成电路管芯电耦合至所述第二集成电路管芯；以及
导电连接件组，耦合至所述芯衬底的第二侧。
2.根据权利要求1所述的封装结构，其中，使用第一焊料连接将所述再分布结构耦合至所述芯衬底的所述第一侧。
3.根据权利要求1所述的封装结构，还包括：
密封剂，插入在所述再分布结构与所述芯衬底之间。
4.根据权利要求3所述的封装结构，其中，所述密封剂沿着所述芯衬底的侧壁延伸。
5.根据权利要求1所述的封装结构，还包括：
集成有源器件，接合至所述再分布结构，所述集成有源器件插入在所述再分布结构与所述芯衬底之间。
6.根据权利要求1所述的封装结构，其中，所述第一局部互连组件混合接合至所述第一再分布层的所述金属化图案和介电层。
7.根据权利要求1所述的封装结构，其中，所述第一局部互连组件的所述互连结构位于所述第一局部互连组件的所述衬底的第一侧上，所述第一局部互连组件的所述第一侧面向所述第一集成电路管芯。
8.根据权利要求1所述的封装结构，其中，所述第一局部互连组件的所述衬底是硅衬底。
9.一种形成封装件的方法，包括：
在第一载体衬底上方形成第一再分布结构，其中，形成所述第一再分布结构包括：
在所述第一载体衬底上方形成第一组导线；
在所述第一组导线上方形成电耦合至所述第一组导线的第一组导电通孔；
将第一互连管芯接合至所述第一组导线，所述第一互连管芯包括衬底、所述衬底上的互连结构以及所述互连结构上的管芯连接件，所述管芯连接件接合至所述第一组导线，所述第一互连管芯在所述第一组导电通孔中的两个之间；
在所述第一组导线、所述第一组导电通孔和所述第一互连管芯上方形成第一介电层，所述第一介电层、所述第一组导电通孔、所述第一组导线和所述第一互连管芯形成第一再分布层；以及
在所述第一再分布层上方形成第二再分布层，所述第二再分布层包括第二介电层、第二组导电通孔和第二组导线，所述第二组导线中的至少一个电耦合至所述第一组导电通孔中的至少一个；
去除所述第一载体衬底；
将芯衬底电连接至所述第一再分布结构的第一侧，所述第二再分布层比所述第一再分布层更靠近所述第一再分布层的所述第一侧；以及
将第一集成电路管芯和第二集成电路管芯接合至所述第一再分布结构的第二侧，所述第二侧与所述第一侧相对，所述第一集成电路管芯和所述第二集成电路管芯电耦合至所述第一互连管芯。
10.一种封装件，包括：
第一再分布结构，所述第一再分布结构包括多个再分布层，所述多个再分布层中的每一个包括金属化图案和介电层，所述多个再分布层中的第一再分布层包括第一介电层和第一互连管芯，所述第一互连管芯包括衬底、在所述衬底上的互连结构以及在所述互连结构上的管芯连接件，所述管芯连接件接合至所述第一再分布层的金属化图案，所述第一再分布层的所述金属化图案包括第一导线和第一导电通孔，所述第一介电层密封所述第一互连管芯；
芯衬底，使用第一组导电连接件耦合至所述第一再分布结构的第一侧，所述第一再分布结构的宽度大于芯衬底的宽度；以及
集成电路管芯封装件，使用第二组导电连接件耦合至所述第一再分布结构的第二侧，所述第二侧与所述第一侧相对。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114501779A (zh) * 2021-12-29 2022-05-13 华为技术有限公司 一种基板、封装结构、板级架构以及基板的制作方法
WO2023038774A1 (en) * 2021-09-09 2023-03-16 Intel Corporation Microelectronic assemblies having backside die-to-package interconnects

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11728273B2 (en) * 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11664315B2 (en) * 2021-03-11 2023-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Structure with interconnection die and method of making same
TWI788099B (zh) * 2021-11-15 2022-12-21 大陸商芯愛科技（南京）有限公司 電子封裝件及其封裝基板
TWI781049B (zh) * 2022-01-24 2022-10-11 欣興電子股份有限公司 電路板結構及其製作方法
CN117377191A (zh) * 2022-07-01 2024-01-09 奥特斯奥地利科技与系统技术有限公司 具有部件承载件、中介层和部件的封装件及其制造方法

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
TWI411073B (zh) 2010-08-13 2013-10-01 Unimicron Technology Corp 嵌埋被動元件之封裝基板及其製法
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US9111949B2 (en) 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
US9768145B2 (en) 2015-08-31 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming multi-die package structures including redistribution layers
US9761571B2 (en) 2015-09-17 2017-09-12 Deca Technologies Inc. Thermally enhanced fully molded fan-out module
TW201843750A (zh) 2017-05-03 2018-12-16 力成科技股份有限公司 晶圓級系統級封裝方法及其半導體封裝結構
US11101209B2 (en) 2017-09-29 2021-08-24 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution structures in semiconductor packages and methods of forming same
US10867954B2 (en) 2017-11-15 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect chips
WO2019132965A1 (en) 2017-12-29 2019-07-04 Intel Corporation Microelectronic assemblies
US10916529B2 (en) 2018-03-29 2021-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Electronics card including multi-chip module
US11075151B2 (en) 2018-06-29 2021-07-27 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package with controllable standoff
US10741498B2 (en) 2018-07-12 2020-08-11 Samsung Electronics Co., Ltd. Semiconductor package
KR102560697B1 (ko) 2018-07-31 2023-07-27 삼성전자주식회사 인터포저를 가지는 반도체 패키지
DE102019113476A1 (de) 2018-08-30 2020-03-05 Taiwan Semiconductor Manufacturing Company, Ltd. Halbleiter-bauelement und verfahren zu dessen herstellung
US11171090B2 (en) 2018-08-30 2021-11-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
KR102163059B1 (ko) * 2018-09-07 2020-10-08 삼성전기주식회사 연결구조체 내장기판

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023038774A1 (en) * 2021-09-09 2023-03-16 Intel Corporation Microelectronic assemblies having backside die-to-package interconnects
CN114501779A (zh) * 2021-12-29 2022-05-13 华为技术有限公司 一种基板、封装结构、板级架构以及基板的制作方法

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