CN112652595A - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN112652595A
CN112652595A CN202011078418.6A CN202011078418A CN112652595A CN 112652595 A CN112652595 A CN 112652595A CN 202011078418 A CN202011078418 A CN 202011078418A CN 112652595 A CN112652595 A CN 112652595A
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China
Prior art keywords
semiconductor chip
chip
semiconductor
redistribution wiring
redistribution
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Pending
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CN202011078418.6A
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English (en)
Inventor
张爱妮
金泳龙
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN112652595A publication Critical patent/CN112652595A/zh
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Abstract

一种半导体封装包括：第一半导体芯片，包括具有彼此相反的第一表面和第二表面的第一基板、在第一基板中的贯通电极、在第一表面上并电连接到贯通电极的第一芯片焊盘、以及在第一表面上并电连接到第一基板中的电路元件的第二芯片焊盘；再分配布线层，在第一半导体芯片的第一表面上，并包括电连接到第一芯片焊盘的第一再分配布线列和电连接到第二芯片焊盘的第二再分配布线列；第二半导体芯片，堆叠在第一半导体芯片的第二表面上并电连接到贯通电极；以及模制构件，在第一和第二半导体芯片的侧表面上。

Description

半导体封装
技术领域
示例实施方式涉及半导体封装以及制造该半导体封装的方法。
背景技术
具有相对短的信号传输长度的扇入式晶片级封装可以具有出色的信号完整性(SI)特性。但是，对于扇入式晶片级封装，再分配布线层直接形成在扇入式晶片上，因此可能不容易应用于堆叠封装。此外，在制造扇入式晶片级封装期间，在使用焊料球作为外部连接端子的测试工艺中可能会出现裂纹。
发明内容
示例实施方式提供了一种能够实现高带宽和高密度并且具有优异的信号完整性特性的半导体封装。
示例实施方式提供了一种制造半导体封装的方法。
根据示例实施方式，一种半导体封装包括：第一半导体芯片，包括具有第一表面和与该第一表面相反的第二表面的第一基板、在第一基板中的贯通电极、在第一表面上并电连接到贯通电极的第一芯片焊盘以及在第一表面上并电连接到第一基板中的电路元件的第二芯片焊盘；再分配布线层，在第一半导体芯片的第一表面上，并包括电连接到第一芯片焊盘的第一再分配布线列和电连接到第二芯片焊盘的第二再分配布线列；第二半导体芯片，堆叠在第一半导体芯片的第二表面上并电连接到贯通电极；以及模制构件，在第一半导体芯片的侧表面和第二半导体芯片的侧表面上。
根据示例实施方式，一种半导体封装包括：第一半导体芯片，具有第一表面和与该第一表面相反的第二表面，并且包括在第一表面中以电连接到第一半导体芯片中的贯通电极的第一芯片焊盘以及在第一表面中以电连接到第一半导体芯片中的电路元件的第二芯片焊盘；第二半导体芯片，堆叠在第一半导体芯片的第二表面上，并通过导电凸块电连接到第一半导体芯片的贯通电极；再分配布线层，在第一半导体芯片的第一表面上，并包括电连接到第一芯片焊盘的第一再分配布线列和电连接到第二芯片焊盘的第二再分配布线列；以及外部连接构件，在再分配布线层的外表面上，并分别电连接到第一和第二再分配布线列。
根据示例实施方式，一种半导体封装包括：再分配布线层，包括第一再分配布线列和第二再分配布线列；第一半导体芯片，在再分配布线层上，并包括电连接到第一再分配布线列的第一芯片焊盘、电连接到第二再分配布线列的第二芯片焊盘以及电连接到第一芯片焊盘的贯通电极；第二半导体芯片，堆叠在第一半导体芯片上并电连接到贯通电极；模制构件，在第一半导体芯片的侧表面和第二半导体芯片的侧表面上；以及外部连接构件，在再分配布线层的外表面上。
根据示例实施方式，在制造半导体封装的方法中，形成第一半导体芯片，该第一半导体芯片包括具有第一表面和与该第一表面相反的第二表面的第一基板、在第一基板中的贯通电极、在第一表面上并电连接到贯通电极的第一芯片焊盘以及在第一表面上并电连接到第一基板中的电路元件的第二芯片焊盘。形成再分配布线层，该再分配布线层在第一半导体芯片的第一表面上，并且包括电连接到第一芯片焊盘的第一再分配布线列和电连接到第二芯片焊盘的第二再分配布线列。第二半导体芯片堆叠在第一半导体芯片上，使得第一半导体芯片的第二表面面对第二半导体芯片，并且第二半导体芯片电连接到贯通电极。在第一半导体芯片的侧表面和第二半导体芯片的侧表面上形成模制构件。
根据示例实施例，作为扇入式晶片级封装和堆叠封装的半导体封装可以包括在第一半导体芯片的第一表面上的再分配布线层和堆叠在第一半导体芯片的第二表面上的第二半导体芯片。第一外部连接构件和第二外部连接构件可以在再分配布线层的封装焊盘上。
第一外部连接构件可以通过作为再分配布线层的第一再分配布线列和第一半导体芯片的贯通电极(其作为第一输入/输出信号线)电连接到第二半导体芯片。第二外部连接构件可以通过再分配布线层的第二再分配布线列(其作为第二输入/输出信号线)电连接到第一半导体芯片。
因此，半导体封装可以提供经由导电凸块堆叠的第一半导体芯片和第二半导体芯片的堆叠封装，从而实现高带宽和高密度。因为输入/输出信号通过彼此分离(例如，彼此电隔离)的第一和第二输入/输出信号线被输入到第一和第二半导体芯片/从第一和第二半导体芯片被输出，所以可以缩短信号传输长度，从而增加/优化信号完整性(SI)。
此外，模制构件可以在第一半导体芯片和第二半导体芯片的侧表面上，从而在使用再分配布线层的外表面上的外部连接构件的封装测试工艺期间抑制/防止裂纹的发生。
附图说明
通过以下结合附图的详细描述，将更清楚地理解示例实施方式。图1至图46表示本文所述的非限制性示例实施方式。
图1是示出根据示例实施方式的半导体封装的剖视图。
图2是示出图1中的部分“A”的放大剖视图。
图3至图20是示出根据示例实施方式的制造半导体封装的方法的剖视图。
图21是示出根据示例实施方式的半导体封装的剖视图。
图22是示出根据示例实施方式的制造半导体封装的方法的剖视图。
图23是示出根据示例实施方式的半导体封装的剖视图。
图24是示出根据示例实施方式的制造半导体封装的方法的剖视图。
图25是示出根据示例实施方式的半导体封装的剖视图。
图26是示出根据示例实施方式的制造半导体封装的方法的剖视图。
图27是示出根据示例实施方式的半导体封装的剖视图。
图28是示出图27中的部分“E”的放大剖视图。
图29至图34是示出根据示例实施方式的制造半导体封装的方法的剖视图。
图35是示出根据示例实施方式的半导体封装的剖视图。
图36是示出图35中的部分“F”的放大剖视图。
图37是示出图35中的部分“G”的放大剖视图。
图38至图46是示出根据示例实施方式的制造半导体封装的方法的剖视图。
具体实施方式
在下文中，将参考附图详细说明示例实施方式。
图1是示出根据示例实施方式的半导体封装的剖视图。图2是示出图1中的部分“A”的放大剖视图。
参照图1和图2，半导体封装10可以包括再分配布线层100、第一半导体芯片200、第二半导体芯片300和模制构件(例如，绝缘模制结构)600。此外，半导体封装10还可以包括用于在第一半导体芯片200和第二半导体芯片300之间电连接的导电凸块360以及用于与外部装置电连接的外部连接构件500。
在示例实施方式中，半导体封装10可以包括第一半导体芯片200和在第一半导体芯片200的第一表面上(例如覆盖第一半导体芯片200的第一表面)的再分配布线层100，以被提供为扇入式晶片级封装(Fan-In WLP)。再分配布线层100可以通过晶片级再分配布线工艺形成在第一半导体芯片200的第一表面上。另外，半导体封装10可以被提供为包括堆叠的第一半导体芯片200和第二半导体芯片300的堆叠封装。
另外，半导体封装10可以被提供为系统级封装(SIP)。例如，第一半导体芯片200可以是包括逻辑电路的逻辑芯片，第二半导体芯片300可以是存储芯片。逻辑芯片可以是用于控制存储芯片的控制器。存储芯片可以包括各种存储电路，诸如DRAM、SRAM、闪存、PRAM、ReRAM、FeRAM、MRAM等。
第一半导体芯片200可以包括第一基板210、绝缘夹层220、第一芯片焊盘230、第二芯片焊盘231、第三芯片焊盘250和贯通电极240。
第一基板210可以包括彼此相反的第一表面和第二表面。第一表面可以是有源表面，第二表面可以是非有源(即无源)表面。电路图案(未示出)可以提供在第一基板210的第一表面中。电路图案可以包括晶体管、二极管等。电路图案可以构成电路元件。因此，第一半导体芯片200可以是包括形成在其中的多个电路元件的半导体器件。
绝缘夹层220可以提供在第一基板210的第一表面上。绝缘夹层220可以包括多个绝缘层220a、220b、220c、220d、220e以及在绝缘层中的第一布线222和第二布线223。第一芯片焊盘230和第二芯片焊盘231可以每个被提供在绝缘夹层220的最外面的绝缘层中。
具体地，第一布线222可以包括分别提供在绝缘层220a、220b、220c、220d、220e中的第一金属布线222a、第一接触222b、第二金属布线222c、第二接触222d和第三金属布线230。第三金属布线230的至少一部分可以用作第一芯片焊盘，作为着陆焊盘。
第二布线223可以包括分别提供在绝缘层220a、220b、220c、220d、220e中的第四金属布线223a、第四接触223b、第五金属布线223c、第五接触223d和第六金属布线231。第六金属布线231的至少一部分可以用作第二芯片焊盘，作为着陆焊盘。第一基板210中的电路元件可以通过第二布线223电连接到第二芯片焊盘231。
可以理解，绝缘夹层220的金属布线层的数量不限于此。作为BEOL(后端工艺)金属布线层的绝缘夹层220可以包括三个或更多个金属布线层。
贯通电极(贯通硅通路，TSV)240可以在第一基板210中从第一基板210的第一表面延伸到第二表面(例如穿透第一基板210)。贯通电极240的端部可以与绝缘夹层220的第一金属布线222a接触。然而，它可以不限于此，例如，贯通电极240可以穿透绝缘夹层220以与第一芯片焊盘230接触。贯通电极240可以通过绝缘夹层220的第一布线222电连接到第一芯片焊盘230。
具有第三芯片焊盘250的绝缘层可以提供在第一基板210的第二表面上，即非有源表面上。贯通电极240的另一端部可以与第三芯片焊盘250接触。
第二半导体芯片300可以包括第二基板310和芯片焊盘330。在一些实施方式中，第二半导体芯片300可以包括在第二基板310的有源表面上的绝缘夹层。例如，芯片焊盘330可以提供在绝缘夹层的最外面的绝缘层中。
电路图案(未示出)可以提供在第二基板310的有源表面中。电路图案可以包括晶体管、二极管等。电路图案可以构成电路元件。芯片焊盘330可以通过绝缘夹层中的布线电连接到电路元件。
在示例实施方式中，第二半导体芯片300可以经由导电凸块360堆叠在第一半导体芯片200上。第二半导体芯片300可以布置在第一半导体芯片200上，使得第二半导体芯片300的芯片焊盘330面对第一半导体芯片200的第三芯片焊盘250。
导电凸块360可以插设在第二半导体芯片300和第一半导体芯片200之间。导电凸块360可以将第一半导体芯片200的第三芯片焊盘250和第二半导体芯片300的芯片焊盘330电连接。例如，导电凸块可以具有10微米(μm)至100μm的直径(例如，在水平方向和/或垂直方向上)。
因此，第二半导体芯片300可以通过导电凸块360电连接到第一半导体芯片200的贯通电极240。
尽管在附图中仅示出了一些芯片焊盘，但是芯片焊盘的结构和布置被示出为示例，并且可以不限于此。
在示例实施方式中，再分配布线层100可以布置在第一半导体芯片200的第一表面上(例如，布置为覆盖第一半导体芯片200的第一表面)。再分配布线层100可以包括电连接到第一芯片焊盘230的第一再分配布线列150a和电连接到第二芯片焊盘231的第二再分配布线列150b。
外部连接构件500可以设置在再分配布线层100的外表面中的封装焊盘上。外部连接构件500可以包括电连接到第一再分配布线列150a的第一外部连接构件500a和电连接到第二再分配布线列150b的第二外部连接构件500b。例如，外部连接构件500可以包括焊料球。焊料球可以具有300μm至500μm的直径(例如，在水平方向和/或垂直方向上)。
具体地，再分配布线层100可以包括第一绝缘层110和第一再分配布线112，该第一绝缘层110提供在第一半导体芯片200的第一表面上并且具有分别暴露第一芯片焊盘230和第二芯片焊盘231的第一开口，并且至少部分的第一再分配布线112通过第一开口分别与第一芯片焊盘230和第二芯片焊盘231接触。
例如，第一再分配布线可以包括铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)、铂(Pt)或其合金。
再分配布线层100可以包括第二绝缘层120和第二再分配布线122，该第二绝缘层120提供在第一绝缘层110上并具有分别暴露第一再分配布线112的第二开口，并且至少部分的第二再分配布线122分别通过第二开口与第一再分配布线112接触。
再分配布线层100可以包括第三绝缘层130和第三再分配布线132，该第三绝缘层130提供在第二绝缘层120上并且具有分别暴露第二再分配布线122的第三开口，并且至少部分的第三再分配布线132分别通过第三开口与第二再分配布线122接触。第三再分配布线132的一部分可以用作着陆焊盘，即，其上设置有外部连接构件500的封装焊盘。在一些实施方式中，再分配布线层100可以包括在第三绝缘层130上和在第三再分配布线132的侧壁上的第四绝缘层140。
可以理解，绝缘层以及再分配布线层的再分配布线的数量、尺寸、布置等被示出为示例，因此，可以不限于此。
第一再分配布线列150a可以包括彼此电连接的第一至第三再分配布线112a、122a、132a。第一再分配布线列150a的第一再分配布线112a可以与第一芯片焊盘230接触。第一再分配布线列150a的第三再分配布线132a的一部分可以用作第一着陆焊盘，即，其上设置有第一外部连接构件500a的第一封装焊盘。因此，第一外部连接构件500a可以通过再分配布线层100的第一再分配布线列150a和第一布线222电连接到贯通电极240。
第二再分配布线列150b可以包括彼此电连接的第一至第三再分配布线112b、122b、132b。第二再分配布线列150b的第一再分配布线112b可以与第二芯片焊盘231接触。第二再分配布线列150b的第三再分配布线132b的一部分可以用作第二着陆焊盘，即，其上设置有第二外部连接构件500b的第二封装焊盘。因此，第二外部连接构件500b可以通过再分配布线层100的第二再分配布线列150b和第二布线223电连接到第一基板210中的电路元件。
因此，再分配布线层100的第一再分配布线列150a和第一半导体芯片200的贯通电极240可以用作用于第二半导体芯片300的第一输入/输出信号线。再分配布线层100的第二再分配布线列150b可以用作用于第一半导体芯片200的第二输入/输出信号线。
在示例实施方式中，模制构件600可以提供在第一半导体芯片200的侧表面和第二半导体芯片300的侧表面上(例如，设置为覆盖第一半导体芯片200的侧表面和第二半导体芯片300的侧表面)。模制构件600可以在第一半导体芯片200和第二半导体芯片300之间延伸(例如，被底部填充)。模制构件600可以提供在再分配布线层100的侧表面上(例如，设置为覆盖再分配布线层100的侧表面)。
例如，模制构件可以包括环氧树脂、聚酰亚胺或丙烯酸材料。
在示例实施方式中，粘合层610可以进一步提供在第二半导体芯片300的外表面(即，第二表面)上。粘合层610可以包括粘合膜，诸如管芯附着膜(DAF)或非导电膜(NCF)。模制构件600可以提供在粘合层610的侧表面上(例如，设置为覆盖粘合层610的侧表面)。
如上所述，作为扇入式晶片级封装的半导体封装10可以包括在第一半导体芯片200的第一表面上(例如，覆盖第一半导体芯片200的第一表面)的再分配布线层100。作为堆叠封装的半导体封装10可以包括堆叠在第一半导体芯片200的第二表面上的第二半导体芯片300。第一外部连接构件500a和第二外部连接构件500b可以分别设置在再分配布线层100的封装焊盘上。
第一外部连接构件500a可以通过再分配布线层100的第一再分配布线列150a和第一半导体芯片200的贯通电极240(其作为第一输入/输出信号线)电连接到第二半导体芯片300。第二外部连接构件500b可以通过再分配布线层100的第二再分配布线列150b(其作为第二输入/输出信号线)电连接到第一半导体芯片200。
因此，半导体封装10可以提供经由导电凸块360堆叠的第一半导体芯片200和第二半导体芯片300的堆叠封装，从而实现高带宽和高密度。输入/输出信号可以通过第一和第二输入/输出信号线被输入到第一和第二半导体芯片200、300/从第一和第二半导体芯片200、300被输出，使得信号传输长度被缩短，从而增加/优化信号完整性(SI)。
此外，模制构件600可以在再分配布线层100、第一半导体芯片200和第二半导体芯片300的侧表面上(例如，覆盖再分配布线层100、第一半导体芯片200和第二半导体芯片300的侧表面)，从而在使用再分配布线层100的外表面上的外部连接构件500的封装测试工艺期间抑制/防止出现裂纹。
在下文中，将解释制造图1中的半导体封装的方法。
图3至图20是示出根据示例实施方式的制造半导体封装的方法的剖视图。图4至图8是示出图3中的部分“B”的放大图。图12是示出图11中的部分“C”的放大图。图16是示出图15中的部分“D”的放大图。
参照图3至图10，可以在第二半导体芯片的芯片焊盘330上形成凸块32。
首先，可以以晶片级在包括第二半导体芯片的第一晶片W1的芯片焊盘330上形成凸块32。
在示例实施方式中，第一晶片W1可以包括第二基板310和提供在第二基板310的第一表面312中的芯片焊盘330。在一些实施方式中，第一晶片W1可以包括在第二基板310的有源表面上的绝缘夹层。例如，芯片焊盘330可以提供在绝缘夹层的最外面的绝缘层332中。第二基板310可以包括其中形成有电路图案和单元的管芯区域DA以及围绕管芯区域DA的划线道区域SA。如本文稍后所描述的，可以沿着划分多个管芯区域DA的划线道区域SA来切割第一晶片W1的第二基板310。
例如，第二基板310可以包括硅、锗、硅锗或III-V族化合物，例如磷化镓(GaP)、砷化镓(GaAs)、锑化镓(GaSb)等。在一些实施方式中，第二基板310可以是绝缘体上硅(SOI)基板或绝缘体上锗(GOI)基板。
电路图案(未示出)可以提供在第二基板310的有源表面中。电路图案可以包括晶体管、二极管等。电路图案可以构成电路元件。芯片焊盘330可以通过绝缘夹层中的布线电连接到电路元件。
在示例实施方式中，凸块32可以形成在芯片焊盘330上。
首先，如图4中所示，绝缘层图案20可以形成在第一晶片W1的前侧312(在下文中，为了简化说明，被称为第二基板310的第一表面)上，以暴露芯片焊盘330，然后籽晶层22可以形成在芯片焊盘330上。
例如，绝缘层图案20可以包括氧化物、氮化物等。这些可以单独使用或以其混合物使用。绝缘层图案20可以通过化学气相沉积(CVD)工艺、等离子体增强化学气相沉积(PECVD)工艺、原子层沉积(ALD)工艺、低压化学气相沉积(LPCVD)工艺、溅射工艺等来形成。可替代地，绝缘层图案20可以包括通过旋涂工艺或喷射工艺形成的聚合物层。在其中用于暴露芯片焊盘330的保护层图案形成在第二基板310的第一表面312上的实施方式中，可以省略形成绝缘层图案的工艺。
籽晶层22可以包括合金层，该合金层包括钛/铜(Ti/Cu)、钛/钯(Ti/Pd)、钛/镍(Ti/Ni)、铬/铜(Cr/Cu)或它们的组合。籽晶层22可以通过溅射工艺形成。
然后，如图5中所示，可以在第二基板310的第一表面312上形成具有开口的光致抗蚀剂图案24，该开口暴露出籽晶层22的一部分。
在光致抗蚀剂层形成在第二基板310的第一表面312上以覆盖芯片焊盘330之后，可以在光致抗蚀剂层上执行曝光工艺以形成具有开口的光致抗蚀剂图案24，该开口暴露出籽晶层22的在芯片焊盘330上的区域。
如图6至图9所示，可以在第二基板310的芯片焊盘330上形成凸块32。
具体地，导电材料30可以形成为填充光致抗蚀剂图案24的开口，光致抗蚀剂图案24可以被去除，然后可以执行回流工艺以形成凸块32。例如，导电材料30可以通过电镀工艺形成在籽晶层22上。可替代地，可以通过丝网印刷工艺、沉积工艺等来形成凸块32。籽晶层22的在光致抗蚀剂图案24下方的部分可以被去除，由此提供在凸块32下方(例如接触凸块32)的导电图案23。
凸块32可以具有从绝缘层图案20的顶表面起的第一高度H1。例如，凸块32的第一高度H1可以在20μm至150μm的范围内。
参照图10，可以沿着划线道区域SA切割第一晶片W1以形成单独的第二半导体芯片300。
在执行切割工艺之前，可以研磨第二基板310的第二表面314。
参照图11至图17，可以在第一半导体芯片的前侧上形成再分配布线层100。
首先，具有电连接到第一和第二芯片焊盘230、231的再分配布线的再分配布线层100可以形成在第二晶片W2的前侧212上。
如图11和图12所示，在示例实施方式中，第二晶片W2可以包括第一基板210、绝缘夹层220、第一芯片焊盘230、第二芯片焊盘231和贯通电极240。绝缘夹层220可以提供在第一基板210的第一表面即有源表面上。例如，第一芯片焊盘230和第二芯片焊盘231可以每个提供在绝缘夹层220的最外面的绝缘层220e中。第一基板210可以包括其中形成有电路图案和单元的管芯区域DA以及围绕管芯区域DA的划线道区域SA。如稍后所述的，可以沿着划分多个管芯区域DA的划线道区域SA来切割第二晶片W2的第一基板210。
电路图案(未示出)可以提供在第一基板210的有源表面中。电路图案可以包括晶体管、二极管等。电路图案可以构成电路元件。如稍后所述的，第二芯片焊盘231可以通过绝缘夹层220中的第二布线223电连接到电路元件。
绝缘夹层220可以提供在第一基板210的有源表面上。绝缘夹层220可以包括多个绝缘层220a、220b、220c、220d、220e以及在绝缘层中的第一布线222和第二布线223。
第一布线222可以包括分别提供在绝缘层220a、220b、220c、220d、220e中的第一金属布线222a、第一接触222b、第二金属布线222c、第二接触222d和第三金属布线230。第三金属布线230的至少一部分可以用作第一芯片焊盘，作为着陆焊盘。因此，第一芯片焊盘230可以提供在第二晶片W2的前侧212中。
第二布线223可以包括分别提供在绝缘层220a、220b、220c、220d、220e中的第四金属布线223a、第四接触223b、第五金属布线223c、第五接触223d和第六金属布线231。第六金属布线231的至少一部分可以用作第二芯片焊盘，作为着陆焊盘。因此，第二芯片焊盘231可以提供在第二晶片W2的前侧212中。第一基板210中的电路元件可以通过第二布线223电连接到第二芯片焊盘231。
贯通电极240可以提供为穿透第一基板210。贯通电极240的端部可以与绝缘夹层220的第一金属布线222a接触。然而，可以不限于此，并且例如，贯通电极240可以穿透绝缘夹层220以与第一芯片焊盘230接触。
因此，贯通电极240可以通过绝缘夹层220的第一布线222电连接到第一芯片焊盘230。可以在研磨第一基板210的背侧即第二表面214之前形成贯通电极240(先通孔工艺、中间通孔工艺)。备选地，可以在研磨第一基板210的背侧之后形成贯通电极(后通孔工艺)。
参照图13，第一绝缘层110可以形成在第二晶片W2的前侧212上(例如，形成为覆盖第二晶片W2的前侧212)，然后，第一绝缘层110可以被图案化以形成分别暴露第一芯片焊盘230和第二芯片焊盘231的第一开口111。
例如，第一绝缘层110可以包括聚合物、电介质材料等。第一绝缘层110可以通过旋涂工艺、气相沉积工艺等形成。
参照图14，第一再分配布线112可以形成在第一绝缘层110上以通过第一开口111分别与第一芯片焊盘230和第二芯片焊盘231接触。
在示例实施方式中，第一再分配布线112可以形成在第一绝缘层110的一部分以及第一芯片焊盘230和第二芯片焊盘231上。第一再分配布线112可以通过在第一绝缘层110的所述部分上和在第一开口111中形成籽晶层、图案化籽晶层以及执行电镀工艺来形成。因此，第一再分配布线112的至少部分可以通过第一开口111分别与第一芯片焊盘230和第二芯片焊盘231接触。
例如，第一再分配布线112可以包括铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)、铂(Pt)或它们的合金。
参照图15和图16，可以执行与参考图13和图14描述的工艺相同或相似的工艺，以在第二晶片W2的前侧212上形成再分配布线层100，然后，可以在再分配布线层100的外表面上形成外部连接构件500。
例如，第二绝缘层120可以形成在第一绝缘层110上、在第一再分配布线112上(例如，以覆盖第一再分配布线112)，然后，第二再分配布线122可以形成在第二绝缘层120上以通过第二开口分别与第一再分配布线112接触。第三绝缘层130可以形成在第二绝缘层120上、在第二再分配布线122上(例如，以覆盖第二再分配布线122)，然后第三再分配布线132可以形成在第三绝缘层130上以通过第三开口分别与第二再分配布线122接触。第三再分配布线132的一部分可以用作着陆焊盘，即，其上设置有外部连接构件500的封装焊盘。可以理解，再分配布线层100的绝缘层的数量、尺寸、布置等可以不限于此。
然后，外部连接构件500可以形成在再分配布线层100上以电连接到再分配布线。例如，作为外部连接构件的焊料球可以设置在第三再分配布线132的所述部分上。外部连接构件500可以通过焊料球附接工艺分别形成在再分配布线层100的外表面中的封装焊盘上。焊料球可以具有300μm至500μm的直径。
如图16所示，再分配布线层100可以包括电连接到第一芯片焊盘230的第一再分配布线列150a和电连接到第二芯片焊盘231的第二再分配布线列150b。外部连接构件500可以包括电连接到第一再分配布线列150a的第一外部连接构件500a和电连接到第二再分配布线列150b的第二外部连接构件500b。
具体地，第一再分配布线列150a可以包括彼此电连接的第一至第三再分配布线112a、122a、132a。第一再分配布线列150a的第一再分配布线112a可以与第一芯片焊盘230接触。第一再分配布线列150a的第三再分配布线132a的一部分可以用作第一着陆焊盘，即，其上设置有第一外部连接构件500a的第一封装焊盘。因此，第一外部连接构件500a可以通过再分配布线层100的第一再分配布线列150a和第一布线222电连接到贯通电极240。
第二再分配布线列150b可以包括彼此电连接的第一至第三再分配布线112b、122b、132b。第二再分配布线列150b的第一再分配布线112b可以与第二芯片焊盘231接触。第二再分配布线列150b的第三再分配布线132b的一部分可以用作第二着陆焊盘，即，其上设置有第二外部连接构件500b的第二封装焊盘。因此，第二外部连接构件500b可以通过再分配布线层100的第二再分配布线列150b和第二布线223电连接到第一基板210中的电路元件。
在示例实施方式中，在形成再分配布线层100之后，可以执行形成具有第三芯片焊盘250的绝缘层252的工艺。具有第三芯片焊盘250的绝缘层252可以提供在第一基板210的第二表面，即非有源(即，无源)表面上。贯通电极240的另一端部可以与第三芯片焊盘250接触。可替代地，可以在形成再分配布线层100之前执行形成第三芯片焊盘250的工艺。
另外，在形成第三芯片焊盘250之前，可以执行研磨第二晶片W2的背侧的工艺。可以在形成贯通电极240之前或之后执行研磨工艺。
参照图17，可以沿着划线道区域SA切割第二晶片W2以形成单独的第一半导体芯片200。
参照图18和图19，第一半导体芯片200可以堆叠在第二半导体芯片300上。
首先，如图18中所示，可以使用粘合层610将第二半导体芯片300粘附在载体基板C上。第二半导体芯片300可以粘附在载体基板C上，使得第二半导体芯片300的其上形成有凸块32的第一表面面朝上。粘合层610可以包括粘合膜，诸如管芯附着膜(DAF)或非导电膜(NCF)。
然后，如图19中所示，第一半导体芯片200可以堆叠在第二半导体芯片300上。第一半导体芯片200可以堆叠在第二半导体芯片300上，使得第一半导体芯片200的其上形成有第三芯片焊盘250的第二表面面对第二半导体芯片300的第一表面。然后，在第一半导体芯片200和第二半导体芯片300之间的凸块32可以被回流以形成导电凸块360。例如，导电凸块360可以具有10μm至100μm的直径。
导电凸块360可以插设在第二半导体芯片300和第一半导体芯片200之间。导电凸块360可以将第二半导体芯片300的芯片焊盘330和第一半导体芯片200的第三芯片焊盘250电连接。因此，第二半导体芯片300可以通过导电凸块360、第一半导体芯片200的贯通电极240和第一再分配布线列150a电连接到第一外部连接构件500a。
参照图20，模制构件600可以形成在载体基板C上以覆盖第一半导体芯片200和第二半导体芯片300。
模制构件600可以形成在第一半导体芯片200之间、在第二半导体芯片300之间以及在第一半导体芯片200和第二半导体芯片300之间。另外，模制构件600可以在再分配布线层100的侧表面上(例如，可以覆盖再分配布线层100的侧表面)。在一些实施方式中，模制构件600可以暴露(即可以不存在于)再分配布线层100的其中形成有封装焊盘的外表面。
模制构件600可以通过点胶工艺(dispensing process)、丝网印刷工艺、旋涂工艺等形成。模制构件600可以包括环氧树脂、聚酰亚胺或丙烯酸材料。
然后，可以沿着切割线CL切割模制构件600，以形成图1中的半导体封装10。可以通过激光切割工艺、刀片切割工艺等切割模制构件600。
在示例实施方式中，可以使用外部连接构件500在堆叠的第一半导体芯片200和第二半导体芯片300上执行电测试工艺。因为再分配布线层100以及堆叠的第一半导体芯片200和第二半导体芯片300被模制构件600覆盖并支撑，所以可以抑制/防止在测试工艺中出现裂纹。
图21是示出根据示例实施方式的半导体封装的剖视图。半导体封装可以与参考图1描述的半导体封装基本相同或相似，除了模制构件之外。因此，相同的附图标记将用于指代相同或相似的元件，并且可以省略关于上述元件的任何进一步重复的解释。
参照图21，半导体封装11的模制构件600可以在再分配布线层100的外表面上(例如，可以覆盖再分配布线层100的外表面)。在再分配布线层100的封装焊盘上的外部连接构件500可以通过模制构件600被暴露。
模制构件600可以提供为覆盖第一半导体芯片200的侧表面、第二半导体芯片300的侧表面以及再分配布线层100的侧表面和外表面。模制构件600可被底部填充在第一半导体芯片200和第二半导体芯片300之间。
因此，由于半导体封装11可以被模制构件600和粘合层610完全覆盖，因此可以更可靠地保护半导体封装11免受外部冲击、湿气等的影响。
在下文中，将解释制造图21中的半导体封装的方法。
图22是示出根据示例实施方式的制造半导体封装的方法的剖视图。
参照图22，首先，可以执行与参考图3至图19描述的工艺相同或类似的工艺，以在第三半导体芯片300上堆叠第一半导体芯片200，然后，模制构件600可以形成在载体基板C上以覆盖第一半导体芯片200和第二半导体芯片300。
模制构件600可以形成在第一半导体芯片200之间、在第二半导体芯片300之间以及在第一半导体芯片200和第二半导体芯片300之间。另外，模制构件600可以覆盖再分配布线层100的侧表面。在一些实施方式中，模制构件600可以在暴露外部连接构件500的同时暴露再分配布线层100的外表面。
然后，可以沿着切割线CL切割模制构件600，以形成图21中的半导体封装11。
图23是示出根据示例实施方式的半导体封装的剖视图。半导体封装可以与参考图21描述的半导体封装基本相同或相似，除了在第一半导体芯片和第二半导体芯片之间的附加粘合层之外。因此，相同的附图标记将用于指代相同或相似的元件，并且可以省略关于上述元件的任何进一步的重复解释。
参照图23，半导体封装12可以还包括在第一半导体芯片200和第二半导体芯片300之间的粘合层370，以将第一半导体芯片200和第二半导体芯片300彼此粘合。
粘合层370可以插设在第一半导体芯片200和第二半导体芯片300之间。例如，粘合层370可以包括非导电膜(NCF)。第三芯片焊盘250上的凸块可以通过芯片接合装置被热压缩并回流以形成导电凸块360，并且第一半导体芯片200和第二半导体芯片300可以通过粘合层370彼此粘合。
在下文中，将解释制造图23中的半导体封装的方法。
图24是示出根据示例实施方式的制造半导体封装的方法的剖视图。
参照图24，首先，可以执行与参照图3至图18描述的工艺相同或相似的工艺，然后，可以使用粘合层370将第一半导体芯片200粘附在第二半导体芯片300上。
在示例实施方式中，粘合层370可以涂覆在第二半导体芯片300的第一表面上或第一半导体芯片200的第二表面上，然后，第一半导体芯片200可以粘附在第二半导体芯片300上。粘合层370可以包括非导电膜。
例如，第一半导体芯片200可以被芯片接合装置的头部吸附，并且可以在第二半导体芯片300上被热压缩。粘合层370可以被加热并且凸块可以被回流以形成在芯片焊盘330和第三芯片焊盘250之间的导电凸块360。
然后，可以执行与参考图22描述的工艺相同或相似的工艺，以在载体基板C上形成覆盖第一半导体芯片200和第二半导体芯片300的模制构件600，然后，可以沿着切割线CL切割模制构件600以形成图23中的半导体封装12。
图25是示出根据示例实施方式的半导体封装的剖视图。半导体封装可以与参考图1描述的半导体封装基本相同或相似，除了附加的第三半导体芯片以外。因此，相同的附图标记将用于指代相同或相似的元件，并且可以省略关于上述元件的任何进一步的重复解释。
参照图25，半导体封装13可以包括再分配布线层100、第一半导体芯片200、第二半导体芯片300、第三半导体芯片400和模制构件600。另外，半导体封装13可以还包括用于第一半导体芯片200和第二半导体芯片300之间的电连接的导电凸块360、用于第二半导体芯片300和第三半导体芯片400之间的电连接的第二导电凸块460以及用于与外部装置电连接的外部连接构件500。
在示例实施方式中，第二半导体芯片300可以包括第二基板310、第四芯片焊盘330、第五芯片焊盘350和贯通电极340。第三半导体芯片400可以包括第三基板410和芯片焊盘430。
第二半导体芯片300可以经由导电凸块360堆叠在第一半导体芯片200上。第二半导体芯片300可以布置在第一半导体芯片200上，使得第二半导体芯片300的第四芯片焊盘330面对第一半导体芯片200的第三芯片焊盘250。
第三半导体芯片400可以经由第二导电凸块460堆叠在第二半导体芯片300上。第三半导体芯片400可以布置在第二半导体芯片300上，使得第三半导体芯片400的芯片焊盘430面对第二半导体芯片300的第五芯片焊盘350。
尽管在图中示出了三个半导体芯片，但是可以理解，堆叠的半导体芯片的数量可以不限于此。
第一外部连接构件500a可以通过再分配布线层100的第一再分配布线列150a、第一半导体芯片200的贯通电极240和第二半导体芯片300的贯通电极340电连接到第三半导体芯片400。
在下文中，将解释制造图25中的半导体封装的方法。
图26是示出根据示例实施方式的制造半导体封装的方法的剖视图。
参照图26，首先，可以执行与参照图3至图18描述的工艺相同或相似的工艺，以使用粘合层610将第三半导体芯片400粘附在载体基板C上，然后，可以在第三半导体芯片400上堆叠第二半导体芯片300，并且可以在第二半导体芯片300上堆叠第一半导体芯片200。
在示例实施方式中，第二半导体芯片300可以堆叠在第三半导体芯片400上。第二半导体芯片300可以堆叠在第三半导体芯片400上，使得第二半导体芯片300的其上形成有第五芯片焊盘350的第二表面面对第三半导体芯片400的第一表面。然后，第二半导体芯片300和第三半导体芯片400之间的凸块可以被回流以形成第二导电凸块460。
然后，第一半导体芯片200可以堆叠在第二半导体芯片300上。第一半导体芯片200可以堆叠在第二半导体芯片300上，使得第一半导体芯片200的其上形成有第三芯片焊盘250的第二表面面对第二半导体芯片300的第一表面。然后，第一半导体芯片200和第二半导体芯片300之间的凸块可以被回流以形成导电凸块360。
然后，可以执行与参考图20描述的工艺相同或相似的工艺以在载体基板C上形成覆盖第一至第三半导体芯片200、300、400的模制构件600，然后，可以沿切割线CL切割模制构件600以形成图25中的半导体封装13。
图27是示出根据示例实施方式的半导体封装的剖视图。图28是示出图27中的部分“E”的放大剖视图。半导体封装可以与参考图1描述的半导体封装基本相同或相似，除了半导体封装包括扇出型的再分配布线层之外。因此，相同的附图标记将用于指代相同或相似的元件，并且可以省略关于上述元件的任何进一步的重复解释。
参照图27和图28，半导体封装14可以包括模制构件600、布置在模制构件600中的第一半导体芯片200和第二半导体芯片300、以及再分配布线层100，该再分配布线层100覆盖模制构件600的第一表面600a并且具有电连接到第一半导体芯片200的第一和第二芯片焊盘230、231的再分配布线。另外，半导体封装14可以还包括用于在第一半导体芯片200和第二半导体芯片300之间电连接的导电凸块360以及用于与外部装置电连接的外部连接构件500。
在示例实施方式中，半导体封装14可以包括被提供为模制基板的模制构件600以及形成在模制构件600的第一表面600a上的再分配布线层100，以被提供为扇出式晶片级封装(Fan-Out WLP)。再分配布线层100可以通过晶片级再分配布线工艺形成在模制构件600的第一表面600a上。另外，半导体封装14可以被提供为包括堆叠的第一半导体芯片200和第二半导体芯片300的堆叠封装。
具体地，再分配布线层100可以覆盖模制构件600的下表面，即第一表面600a。第一半导体芯片200可以被容纳在模制构件600中，使得第一半导体芯片200的其中形成有第一和第二芯片焊盘230、231的第一表面面对再分配布线层100。第一半导体芯片200的第一表面可以通过模制构件600的第一表面600a被暴露。因此，第一半导体芯片200的第一和第二芯片焊盘230、231可以通过模制基板600的第一表面600a被暴露。
第二半导体芯片300可以经由导电凸块360堆叠在第一半导体芯片200上。第二半导体芯片300可以布置在第一半导体芯片200上，使得第二半导体芯片300的芯片焊盘330面对第一半导体芯片200的第三芯片焊盘250。
外部连接构件500可以设置在再分配布线层100的外表面中的封装焊盘上。外部连接构件500可以包括电连接到第一再分配布线列150a的第一外部连接构件500a和电连接到第二再分配布线列150b的第二外部连接构件500b。例如，外部连接构件500可以包括焊料球。
第一再分配布线列150a可以包括彼此电连接的第一至第三再分配布线112a、122a、132a。第一再分配布线列150a的第一再分配布线112a可以与第一芯片焊盘230接触。第一再分配布线列150a的第三再分配布线132a的一部分可以用作第一着陆焊盘，即，其上设置有第一外部连接构件500a的第一封装焊盘。因此，第一外部连接构件500a可以通过再分配布线层100的第一再分配布线列150a和第一布线222电连接到贯通电极240。
第二再分配布线列150b可以包括彼此电连接的第一至第三再分配布线112b、122b、132b。第二再分配布线列150b的第一再分配布线112b可以与第二芯片焊盘231接触。第二再分配布线列150b的第三再分配布线132b的一部分可以用作第二着陆焊盘，即，其上设置有第二外部连接构件500b的第二封装焊盘。因此，第二外部连接构件500b可以通过再分配布线层100的第二再分配布线列150b和第二布线223电连接到第一基板210中的电路元件。
第一外部连接构件500a可以通过再分配布线层100的第一再分配布线列150a和第一半导体芯片200的贯通电极240(其作为第一输入/输出信号线)电连接到第二半导体芯片300。第二外部连接构件500b可以通过再分配布线层100的第二再分配布线列150b(其作为第二输入/输出信号线)电连接到第一半导体芯片200。
在下文中，将解释制造图27中的半导体封装的方法。
图29至图34是示出根据示例实施方式的制造半导体封装的方法的剖视图。
参照图29，首先，可以在虚设基板40上形成分离层50，然后，可以在分离层50上顺序地堆叠第一半导体芯片200和第二半导体芯片300。
在示例实施方式中，虚设基板40可以用作其上堆叠有第一半导体芯片200和第二半导体芯片300的基础基板，并且模制基板将被形成为覆盖第一半导体芯片200和第二半导体芯片300。虚设基板40可以具有与在其上执行半导体制造工艺的晶片相对应的尺寸。虚设基板40可包括例如硅基板、玻璃基板、或者非金属或金属板。
分离层50可以包括用作临时粘合剂的聚合物带。分离层50可以包括当用光照射或被加热时失去其粘合强度的材料。分离层50可以包括例如通过紫外线或可见光的照射可交联的双重固化有机硅粘合剂。
第一半导体芯片200可以设置在虚设基板40上，使得第一半导体芯片200的第二表面面向上，然后，第二半导体芯片300可以堆叠在第一半导体芯片200上。第二半导体芯片300可以堆叠在第一半导体芯片200上，使得第二半导体芯片300的其上形成有芯片焊盘330的第一表面面对第一半导体芯片200的第二表面。
参照图30，作为模制基板的模制构件600可以形成在虚设基板40上以覆盖第一半导体芯片200和第二半导体芯片300。
在示例实施方式中，覆盖第一半导体芯片200和第二半导体芯片300的模制构件600可以通过由模制工艺在分离层50上形成模制材料来形成。
模制构件600可以形成在第一半导体芯片200的侧表面和第二半导体芯片300的侧表面上以及在第一半导体芯片200和第二半导体芯片300之间。
参照图31，图30中的包括形成在其中的模制构件600的结构可以被颠倒(例如，旋转/翻转)，然后，可以从模制构件600去除虚设基板40和分离层50。
在示例实施方式中，可以用光照射分离层50或可以加热分离层50以从模制构件600去除虚设基板40。随着虚设基板40被去除，第一半导体芯片200的第一表面可以通过模制构件600的第一表面600a被暴露。因此，第一半导体芯片200的第一芯片焊盘230和第二芯片焊盘231可以通过模制构件600的第一表面600a被暴露。
参照图32和图33，第一绝缘层110可以形成为覆盖模制构件600的第一表面600a，然后，第一绝缘层110可以被图案化以形成分别暴露第一芯片焊盘230和第二芯片焊盘231的第一开口111。然后，第一再分配布线112可以形成在第一绝缘层110上，以通过第一开口111分别与第一芯片焊盘230和第二芯片焊盘231接触。
参照图34，可以执行与参考图32和图33描述的工艺相同或相似的工艺，以在模制构件600的第一表面600a上形成再分配布线层100，然后，可以在再分配布线层100的外表面上形成外部连接构件500。
在示例实施方式中，第二绝缘层120和第二再分配布线122可以形成在第一绝缘层110和第一再分配布线112上。第二绝缘层120可以形成在第一绝缘层110上以具有分别暴露出第一再分配布线112的开口。第二再分配布线122可以形成在第二绝缘层120的一部分和第一再分配布线112的一部分上。
第三绝缘层130和第三再分配布线132可以形成在第二绝缘层120和第二再分配布线122上。第三绝缘层130可以形成在第二绝缘层120上，以具有分别暴露出第二再分配布线122的开口。第三再分配布线132可以形成在第三绝缘层130的一部分和第二再分配布线122的一部分上。
因此，包括电连接到第一芯片焊盘230和第二芯片焊盘231的再分配布线的再分配布线层100可以形成在模制构件600的第一表面600a上。可以理解的是，再分配布线层100的绝缘层的数量、尺寸、布置等可以不限于此。
然后，电连接到再分配布线的外部连接构件500可以形成在再分配布线层100上。例如，作为外部连接构件的焊料球可以设置在第三再分配布线132的一部分上。在此情况下，第三再分配布线132的所述部分可以用作着陆焊盘，即封装焊盘。因此，再分配布线层100可以形成为包括扇出型焊料球着陆焊盘，其通过执行半导体制造工艺而形成在与晶片的每个管芯相对应的模制构件600上。
然后，可以在模制构件600上执行切割工艺，以形成包括模制构件600和在模制构件600上的再分配布线层100的单独的扇出式晶片级封装。
图35是示出根据示例实施方式的半导体封装的剖视图。图36是示出图35中的部分“F”的放大剖视图。图37是示出图35中的部分“G”的放大剖视图。图35的半导体封装可以与参考图27描述的半导体封装基本相同或相似，除了附加的第二封装。因此，相同的附图标记将用于指代相同或相似的元件，并且可以省略关于上述元件的任何进一步的重复解释。
参照图35至图37，半导体封装15可以包括第一封装和堆叠在第一封装上的第二封装800。第二封装800可以经由导电连接构件900堆叠在第一封装上。
在示例实施方式中，第一封装可以包括模制构件600、布置在模制构件600中的第一半导体芯片200和第二半导体芯片300、以及再分配布线层100，该再分配布线层100覆盖模制构件600的第一表面600a并且包括电连接到第一半导体芯片200的第一芯片焊盘230和第二芯片焊盘231的再分配布线。另外，第一封装可以还包括用于在第一半导体芯片200和第二半导体芯片300之间电连接的导电凸块360、用于与外部装置电连接的外部连接构件500、以及导电连接构件，即在第一和第二半导体芯片200、300的外部区域中并且穿透模制构件600的至少一部分的导电连接柱700。
第一封装可以还包括背侧再分配布线层，该背侧再分配布线层具有提供在模制构件600的第二表面600b上的背侧再分配布线702。例如，背侧再分配布线702可以形成在模制构件600的第二表面600b上。背侧再分配布线702可以分别形成在导电连接柱700的由模制构件600的第二表面600b暴露的上表面上。导电连接柱700可以电连接到背侧再分配布线702。
第二封装800可以经由在模制构件600的第二表面600b上的导电连接构件900堆叠在第一封装上。例如，导电连接构件900可以包括焊料球、导电凸块等。导电连接构件900可以布置在导电连接柱700上的背侧再分配布线702与第二封装基板810的第一键合焊盘之间。因此，第一封装和第二封装800可以通过导电连接构件900彼此电连接。
第四和第五半导体芯片820、830可以通过粘合构件堆叠在第二封装基板810上。键合引线840可以将第四和第五半导体芯片820、830的芯片焊盘822、832电连接到第二封装基板810的第二键合焊盘814。第四和第五半导体芯片820、830可以通过键合引线840电连接到第二封装基板810。
尽管在图中示出了包括以引线键合方式安装的两个半导体芯片的第二封装800，但是可以理解的是，第二封装800的半导体芯片的数量、安装方式等可以不限于此。
在示例实施方式中，再分配布线层100可以包括电连接到第一芯片焊盘230的第一再分配布线列150a、电连接到第二芯片焊盘231的第二再分配布线列150b和电连接到导电连接柱700的第三再分配布线列150c。
外部连接构件500可以设置在再分配布线层100的外表面中的封装焊盘上。外部连接构件500可以包括电连接到第一再分配布线列150a的第一外部连接构件500a、电连接到第二再分配布线列150b的第二外部连接构件500b和电连接到第三再分配布线列150c的第三外部连接构件500c。例如，每个外部连接构件500可以包括焊料球。
第一再分配布线列150a可以包括彼此电连接的第一至第三再分配布线112a、122a、132a。第一再分配布线列150a的第一再分配布线112a可以与第一芯片焊盘230接触。第一再分配布线列150a的第三再分配布线132a的一部分可以用作第一着陆焊盘，即，第一封装焊盘。第一外部连接构件(第一焊料球)500a可以设置在第一封装焊盘上。因此，第一外部连接构件500a可以通过再分配布线层100的第一再分配布线列150a和第一布线222电连接到贯通电极240。
第二再分配布线列150b可以包括彼此电连接的第一至第三再分配布线112b、122b、132b。第二再分配布线列150b的第一再分配布线112b可以与第二芯片焊盘231接触。第二再分配布线列150b的第三再分配布线132b的一部分可以用作第二着陆焊盘，即，第二封装焊盘。第二外部连接构件(第二焊料球)500b可以设置在第二封装焊盘上。因此，第二外部连接构件500b可以通过再分配布线层100的第二再分配布线列150b和第二布线223电连接到第一基板210中的电路元件。
第三再分配布线列150c可以包括彼此电连接的第一至第三再分配布线112c、122c、132c。第三再分配布线列150c的第一再分配布线112c可以与导电连接柱700接触。第三再分配布线列150c的第三再分配布线132c的一部分可以用作第三着陆焊盘，即，第三封装焊盘。第三外部连接构件(第三焊料球)500c可以设置在第三封装焊盘上。因此，第三外部连接构件500c可以通过再分配布线层100的第三再分配布线列150c和导电连接柱700电连接到第二封装800。
因此，再分配布线层100的第一再分配布线列150a和第一半导体芯片200的贯通电极240可以用作用于第二半导体芯片300的第一输入/输出信号线。再分配布线层100的第二再分配布线列150b可以用作用于第一半导体芯片200的第二输入/输出信号线。再分配布线层100的第三再分配布线列150c和导电连接柱700可以用作用于第二封装800的第三输入/输出信号线。
在下文中，将解释制造图35中的半导体封装的方法。
图38至图46是示出根据示例实施方式的制造半导体封装的方法的剖视图。
参照图38，首先，可以在虚设基板60上形成导电层70，然后，可以在导电层70上顺序地堆叠第一半导体芯片200和第二半导体芯片300。
在示例实施方式中，虚设基板60可以用作在其上堆叠有第一半导体芯片200和第二半导体芯片300的基础基板，并且模制基板要形成为覆盖第一半导体芯片200和第二半导体芯片300。虚设基板60可以具有与在其上执行半导体制造工艺的晶片相对应的尺寸。虚设基板60可包括例如硅基板、玻璃基板、或者非金属或金属板。
然后，可以在虚设基板60上形成导电层70。例如，可以通过层压金属箔来形成导电层70。可替代地，可以通过沉积金属来形成导电层70。金属的示例可以是铜(Cu)、金(Au)、铝(Al)、钨(W)、镍(Ni)、钛(Ti)或其合金。
第一半导体芯片200可以粘附在虚设基板60上，使得第一半导体芯片200的第二表面面向上，然后，第二半导体芯片300可以堆叠在第一半导体芯片200上。第二半导体芯片300可以堆叠在第一半导体芯片200上，使得第二半导体芯片300的其上形成有芯片焊盘330的第一表面面对第一半导体芯片200的第二表面。
参照图39，可以在虚设基板60上形成作为模制基板的模制构件600，以覆盖第一半导体芯片200和第二半导体芯片300。
参照图40和图41，开口602可以形成在模制构件600中以分别暴露导电连接柱区域，然后，导电连接柱700可以形成在开口602中。然后，背侧再分配布线702可以形成在导电连接柱700的通过模制构件600的第二表面暴露的部分(例如导电连接柱700的没有模制构件600的部分)上。
例如，开口602可以通过激光钻孔工艺形成。可以在导电层70的被开口602暴露的部分上执行电镀工艺以形成导电连接柱700。
籽晶层可以形成在模制构件600的第二表面即背侧上，然后，籽晶层可以被图案化以形成背侧再分配布线702。
参照图42至图44，图41中的包括形成在其中的模制构件600的结构可以被颠倒(例如，旋转/翻转)，具有暴露第一再分配布线区域的开口的光致抗蚀剂图案80可以形成在导电层70上，然后可以使用光致抗蚀剂图案80对导电层70进行图案化以形成第一再分配布线112。
例如，可以在模制构件600的第一表面上的导电层70上形成光致抗蚀剂层，然后可以执行曝光和显影工艺以形成光致抗蚀剂图案80。可以使用光致抗蚀剂图案80作为蚀刻掩模来蚀刻导电层70，以形成第一再分配布线112。第一再分配布线112可以形成在导电连接柱700的表面上。
参照图45，可以执行与参考图34描述的工艺相同或相似的工艺，以在模制构件600的第一表面600a上形成再分配布线层100，然后，可以在再分配布线层100上形成外部连接构件500。
然后，可以在模制构件600上执行切割工艺，以形成包括模制构件600和在模制构件600上的再分配布线层100的单独的第一封装。
参照图46，第二封装800可以堆叠在第一封装上。
在示例实施方式中，第二封装800可以包括第二封装基板810、安装在第二封装基板810上的第四和第五半导体芯片820、830、以及在第二封装基板810上以覆盖第四和第五半导体芯片820、830的模制构件850。
第二封装800可以经由在模制构件600的第二表面600b上的导电连接构件900堆叠在第一封装上。例如，导电连接构件900可以包括焊料球、导电凸块等。导电连接构件900可以布置在导电连接柱700上的背侧再分配布线702与第二封装基板810的第一键合焊盘811之间。因此，第一封装和第二封装800可以通过导电连接构件900彼此电连接。
半导体封装可以包括诸如逻辑器件或存储器件的半导体器件。半导体封装可以包括逻辑器件(诸如中央处理单元(CPU)、主处理单元(MPU)或应用处理器(AP)等)，以及易失性存储器件(诸如DRAM器件、高带宽存储(HBM)器件)或非易失性存储器件(诸如闪存器件、PRAM器件、MRAM器件、ReRAM器件等)。
前述内容是示例实施方式的说明，并且不应解释为对其的限制。尽管已经描述了一些示例实施方式，但是本领域技术人员将容易认识到，在实质上不背离本发明的新颖教导和优点的情况下，可以对示例实施方式进行许多修改。因此，所有这些修改旨在被包括在如权利要求中所限定的示例实施方式的范围内。
本申请要求于2019年10月11日在韩国知识产权局(KIPO)提交的韩国专利申请第10-2019-0126109号的优先权，其全部内容通过引用合并于此。

Claims (20)

1.一种半导体封装，包括：
第一半导体芯片，包括具有第一表面和与所述第一表面相反的第二表面的第一基板、在所述第一基板中的贯通电极、在所述第一表面上并电连接到所述贯通电极的第一芯片焊盘以及在所述第一表面上并电连接到所述第一基板中的电路元件的第二芯片焊盘；
再分配布线层，在所述第一半导体芯片的所述第一表面上，并包括电连接到所述第一芯片焊盘的第一再分配布线列和电连接到所述第二芯片焊盘的第二再分配布线列；
第二半导体芯片，堆叠在所述第一半导体芯片的所述第二表面上并电连接到所述贯通电极；以及
模制构件，在所述第一半导体芯片的侧表面和所述第二半导体芯片的侧表面上。
2.根据权利要求1所述的半导体封装，其中，所述模制构件在所述第一半导体芯片和所述第二半导体芯片之间延伸。
3.根据权利要求1所述的半导体封装，还包括：
粘合层，在所述第一半导体芯片和所述第二半导体芯片之间以将所述第一半导体芯片和所述第二半导体芯片彼此粘合。
4.根据权利要求1所述的半导体封装，还包括：
导电凸块，插设在所述第一半导体芯片和所述第二半导体芯片之间，以将所述贯通电极电连接到所述第二半导体芯片。
5.根据权利要求4所述的半导体封装，其中，所述导电凸块具有10μm至100μm的直径。
6.根据权利要求4所述的半导体封装，其中，所述第二半导体芯片在其面对所述第二表面的第三表面上包括第三芯片焊盘，并且所述导电凸块在所述第三芯片焊盘上。
7.根据权利要求1所述的半导体封装，还包括：
在所述再分配布线层的外表面上的外部连接构件。
8.根据权利要求7所述的半导体封装，其中，所述外部连接构件包括电连接到所述第一再分配布线列的第一焊料球和电连接到所述第二再分配布线列的第二焊料球。
9.根据权利要求8所述的半导体封装，其中，所述第一焊料球和所述第二焊料球每个具有300μm至500μm的直径。
10.根据权利要求1所述的半导体封装，其中，所述第一半导体芯片还包括绝缘夹层，所述绝缘夹层在其外表面中具有所述第一芯片焊盘和所述第二芯片焊盘。
11.一种半导体封装，包括：
第一半导体芯片，具有第一表面和与所述第一表面相反的第二表面，并且包括在所述第一表面中以电连接到所述第一半导体芯片中的贯通电极的第一芯片焊盘以及在所述第一表面中以电连接到所述第一半导体芯片中的电路元件的第二芯片焊盘；
第二半导体芯片，堆叠在所述第一半导体芯片的所述第二表面上，并通过导电凸块电连接到所述第一半导体芯片的所述贯通电极；
再分配布线层，在所述第一半导体芯片的所述第一表面上，并包括电连接到所述第一芯片焊盘的第一再分配布线列和电连接到所述第二芯片焊盘的第二再分配布线列；以及
外部连接构件，在所述再分配布线层的外表面上，并分别电连接到所述第一再分配布线列和所述第二再分配布线列。
12.根据权利要求11所述的半导体封装，还包括：
模制构件，在所述第一半导体芯片的侧表面和所述第二半导体芯片的侧表面上。
13.根据权利要求12所述的半导体封装，其中，所述模制构件在所述第一半导体芯片和所述第二半导体芯片之间延伸。
14.根据权利要求12所述的半导体封装，还包括：
粘合层，在所述第一半导体芯片和所述第二半导体芯片之间以将所述第一半导体芯片和所述第二半导体芯片彼此粘合。
15.根据权利要求12所述的半导体封装，其中，所述模制构件在所述再分配布线层的所述外表面上。
16.根据权利要求11所述的半导体封装，其中，所述导电凸块具有10μm至100μm的直径。
17.根据权利要求11所述的半导体封装，其中，所述外部连接构件包括电连接到所述第一再分配布线列的第一焊料球和电连接到所述第二再分配布线列的第二焊料球。
18.根据权利要求11所述的半导体封装，其中，所述第一再分配布线列和所述第二再分配布线列彼此电隔离。
19.根据权利要求11所述的半导体封装，
其中所述第二半导体芯片在其面对所述第二表面的第三表面中包括第三芯片焊盘，
其中，所述导电凸块包括在所述第三芯片焊盘上的第一导电凸块，
其中，所述贯通电极包括第一贯通电极，以及
其中，所述半导体封装还包括在所述第一半导体芯片中的第二贯通电极和将所述第二半导体芯片电连接到所述第二贯通电极的第二导电凸块。
20.一种半导体封装，包括：
再分配布线层，包括第一再分配布线列和第二再分配布线列；
第一半导体芯片，在所述再分配布线层上，并包括电连接到所述第一再分配布线列的第一芯片焊盘、电连接到所述第二再分配布线列的第二芯片焊盘以及电连接到所述第一芯片焊盘的贯通电极；
第二半导体芯片，堆叠在所述第一半导体芯片上并电连接到所述贯通电极；
模制构件，在所述第一半导体芯片的侧表面和所述第二半导体芯片的侧表面上；以及
外部连接构件，在所述再分配布线层的外表面上。
CN202011078418.6A 2019-10-11 2020-10-10 半导体封装 Pending CN112652595A (zh)

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