CN108400122A - 伪金属帽和再分布线的路由设计 - Google Patents

伪金属帽和再分布线的路由设计 Download PDF

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Publication number
CN108400122A
CN108400122A CN201710482330.2A CN201710482330A CN108400122A CN 108400122 A CN108400122 A CN 108400122A CN 201710482330 A CN201710482330 A CN 201710482330A CN 108400122 A CN108400122 A CN 108400122A
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China
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pseudo
hole
metal cap
dielectric layer
active
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CN201710482330.2A
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CN108400122B (zh
Inventor
余振华
陈宪伟
李孟灿
林宗澍
吴伟诚
邱建嘉
王景德
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种封装件包括第一介电层，位于第一介电层上方且附接至第一介电层的器件管芯，有源贯通孔和伪贯通孔以及密封器件管芯、有源贯通孔和伪贯通孔的密封材料。封装件还包括位于器件管芯、有源贯通孔和伪贯通孔上方并与其接触的第二介电层。有源金属帽位于第二介电层上方并与第二介电层接触并电连接至有源贯通孔。有源金属帽与有源贯通孔重叠。伪金属帽位于第二介电层上方并接触第二介电层。伪金属帽与伪贯通孔重叠。通过间隙将伪金属帽分成第一部分和第二部分。再分布线穿过伪金属帽的第一部分和第二部分之间的间隙。本发明实施例涉及伪金属帽和再分布线的路由设计。

Description

伪金属帽和再分布线的路由设计
技术领域
本发明实施例涉及伪金属帽和再分布线的路由设计。
背景技术
随着半导体技术的进步，半导体芯片/管芯变得越来越小。同时，更多功能需要集成到半导体管芯中。因此，半导体管芯需要将越来越多的I/O焊盘封装到较小的区域中，并且因此随着时间I/O焊盘的密度迅速提升。结果，半导体管芯的封装变得更加困难，这会对封装产量产生不利影响。
传统的封装技术可以分为两类。在第一类中，晶圆上的管芯在它们被锯切之前封装。这种封装技术具有诸如较大的产量和较低的成本的一些有益的特征。此外，需要较少的底部填充物或模塑料。然而，这种封装技术还具有缺陷。由于管芯的尺寸正变得越来越小，并且相应的封装件仅可以是扇入型封装件，其中，每个管芯的I/O焊盘限制于直接位于相应的管芯的表面上方的区域。因为管芯的面积有限，由于I/O焊盘的间距的限制，I/O焊盘的数量受到限制。如果焊盘的间距减小，则可能发生焊料桥接。此外，在固定的焊球尺寸需求下，焊球必须具有特定的尺寸，这进而限制可以封装在管芯表面上的焊球的数量。
在另一类封装中，管芯在它们被封装之前从晶圆上锯切下来。该封装技术的有益特征是形成扇出型封装件的可能性，这意味着管芯上的I/O焊盘可以再分布至比管芯更大的区域，并且因此可以增大封装在管芯的表面上的I/O焊盘的数量。该封装技术的另一有益特征是封装“已知良好管芯”，以及丢弃缺陷管芯，并且因此不会在缺陷管芯上浪费成本和精力。
在扇出封装件中，将器件管芯封装在模塑料中，然后平坦化以暴露器件管芯。然后形成再分布线以连接至器件管芯。扇出封装件还可以包括穿透模塑料的贯通孔。
发明内容
根据本发明的一个实施例，提供了一种封装件，包括：第一介电层；器件管芯，位于所述第一介电层上方并且附接至所述第一介电层；有源贯通孔和伪贯通孔；密封材料，密封所述器件管芯、所述有源贯通孔和所述伪贯通孔；第二介电层，位于所述器件管芯、所述有源贯通孔和所述伪贯通孔上方并且接触所述器件管芯、所述有源贯通孔和所述伪贯通孔；有源金属帽，位于所述第二介电层上方并且接触所述第二介电层并且电连接至所述有源贯通孔，其中，所述有源金属帽与所述有源贯通孔重叠；伪金属帽，位于所述第二介电层上方并且接触所述第二介电层，其中，所述伪金属帽与所述伪贯通孔重叠，并且通过第一间隙将所述伪金属帽分成第一部分和第二部分；以及第一再分布线，穿过所述第一间隙。
根据本发明的另一实施例，还提供了一种封装件，包括：器件管芯；伪贯通孔；密封材料，密封所述器件管芯和所述伪贯通孔；第一介电层，位于所述器件管芯、所述伪贯通孔和所述密封材料上方并且接触所述器件管芯、所述伪贯通孔和所述密封材料；第一伪金属帽，位于所述第一介电层上方并且接触所述第一介电层，其中，所述第一伪金属帽与所述伪贯通孔重叠并且延伸超过所述伪贯通孔的边缘；以及第一再分布线，在与所述第一伪金属帽相同的水平处，其中，所述第一再分布线将所述第一伪金属帽分成第一部分和第二部分。
根据本发明的又一实施例，还提供了一种形成封装件的方法，包括：将器件管芯附接至第一介电层；在所述第一介电层上方形成有源贯通孔和伪贯通孔；将所述器件管芯、所述有源贯通孔和所述伪贯通孔密封在密封材料中；在所述密封材料上方形成第二介电层；以及在共同的工艺中沉积有源金属帽、再分布线和伪金属帽，其中，所述有源金属帽和所述伪金属帽分别与所述有源贯通孔和所述伪贯通孔重叠，并且通过所述再分布线将所述伪金属帽分成第一部分和第二部分。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳地理解本发明的各个方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或减小。
图1至图14是根据一些实施例的形成包括前侧再分布线的封装件的中间阶段的截面图。
图15和图16是根据一些实施例的形成包括前侧再分布线和背侧再分布线的封装件的中间阶段的截面图。
图17是根据一些实施例的封装件的顶视图。
图18至图21是根据一些实施例的伪金属帽的顶视图。
图22示出根据一些实施例的用于形成封装件的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，在此可以使用诸如“在…下方”、“在…下面”、“下部”、“在…之上”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，并且在此使用的空间相对描述符可以同样地作出相应的解释。
根据各个示例性实施例，提供了一种封装件及其形成方法。根据一些实施例示出形成封装件的中间阶段。讨论了一些实施例的一些变化。贯穿各个视图和示例性实施例，相同的参考标号用于指定相同的元件。
图1至图14示出根据一些实施例的形成封装件的中间阶段的截面图。图1至图14中所示的步骤还在图22中所示的工艺流程200中示意性地示出。
图1示出载体20和涂覆在载体20上的释放层22。载体20可以是玻璃载体、陶瓷载体等。载体20可具有圆形的顶视形状并且可具有硅晶圆的尺寸。例如，载体20可具有8英寸的直径、12英寸的直径等。释放层22可以由光热转换(LTHC)涂覆材料形成，其可以与载体20一起从将在后续步骤中形成的上面结构去除。根据本发明的一些实施例，释放层22由环氧树脂基热释放材料形成。在载体20上涂覆释放层22。
在释放层22上方形成介电层28。介电层28的底面可以与释放层22的顶面接触。根据本发明的一些实施例，介电层28由聚合物形成，该聚合物可以是诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的光敏材料。根据可选实施例，介电层28由无机介电材料形成，其可以是诸如氮化硅的氮化物，诸如氧化硅、PSG、BSG、BPSG等的氧化物。
图2至图4示出形成统称为金属杆32的金属杆32A和32B。相应步骤在图22所示的工艺流程中示出为步骤202。贯穿说明书，由于金属杆32穿透后续分配的密封材料，所以金属杆32可选地称为贯通孔32。
参考图2，例如，通过物理汽相沉积(PVD)来形成金属晶种层29。根据一些实施例，金属晶种层29可包括铜，或可以包括钛层和钛层上方的铜层。在金属晶种层29上方形成光刻胶30。然后使用光刻掩模(未示出)对光刻胶30实施曝光。在后续的显影之后，在光刻胶30中形成开口31。通过开口31暴露金属晶种层29的一些部分。
接下来，如图3所示，通过在开口31中电镀金属材料来形成贯通孔32(包括32A和32B)。镀的金属材料可以是铜或铜合金。在后续步骤中，去除光刻胶30，并且因此暴露下面的金属晶种层29的部分。然后，在蚀刻步骤中去除金属晶种层29的暴露部分。在图4中示出所得到的贯通孔32。贯穿说明书，金属晶种层29的剩余部分认为是贯通孔32的部分，并且未单独示出。贯通孔32包括功能(有源)贯通孔32A和伪通孔32B，其功能将在后续段落中讨论。
图5示出器件管芯36的放置/布置。相应步骤在图22所示的工艺流程中示出为步骤204。通过管芯附接膜(DAF)38将管芯器件36附接至介电层28，DAF 38是粘合膜。器件管芯36可以包括半导体衬底，半导体衬底的背面(朝下的表面)与DAF 38物理接触。器件管芯36可以包括位于半导体衬底的正面(朝上的表面)处的集成电路器件(例如，诸如包括晶体管的有源器件，未示出)。器件管芯36可以是诸如中央处理单元(CPU)管芯、图形处理单元(GPU)管芯、移动应用管芯等的逻辑管芯。
根据一些示例性实施例，金属柱42(诸如铜柱)预先形成为器件管芯36的部分，其中金属柱42电连接至器件管芯36中的诸如晶体管(未示出)的集成电路器件。根据本发明的一些实施例，聚合物填充相邻的金属柱42之间的间隙，以形成顶部介电层44。顶部介电层44还可以包括覆盖和保护金属柱42的部分。根据本发明的一些实施例，聚合物层44可以由PBO或聚酰亚胺形成。
接下来，如图6所示，可以用密封材料48密封器件管芯36和金属杆32。相应步骤在图22所示的工艺流程中示出为步骤206。密封材料48填充相邻贯通孔32之间的间隙以及贯通孔32和器件管芯36之间的间隙。密封材料48可以包括模塑料、模制底部填充物、环氧树脂和/或树脂。密封材料48的顶面高于金属柱42的顶端。模塑料48可以包括基体材料和基体材料中的填料颗粒(未示出)，基体材料可以是聚合物、树脂、环氧树脂等。填料颗粒可以是SiO2、Al2O3、石英等的介电颗粒，并且可以具有球形形状。
在后续步骤中，如图7所示，实施诸如化学机械抛光(CMP)步骤或机械研磨步骤的平坦化以削薄密封材料48，直到暴露贯通孔32和金属柱42。相应步骤还在图22所示的工艺流程中示出为步骤206。由于平坦化，贯通孔32的顶端与金属柱42的顶面大致齐平(共面)，并且与密封材料48的顶面大致共面。
图8和图9示出形成前侧RDL的第一层和相应的介电层。参考图8，形成介电层50。相应步骤在图22所示的工艺流程中示出为步骤208。根据本发明的一些实施例，介电层50由诸如PBO、聚酰亚胺等的聚合物形成。根据可选实施例，介电层50由氮化硅、氧化硅等形成。然后例如通过光刻工艺形成开口52。通过开口52暴露有源贯通孔32A和金属柱42。根据本发明的一些实施例，通过开口52暴露伪通孔32B。根据本发明的可选实施例，没有形成开口52以暴露伪通孔32B的一些或全部，并且因此在形成开口52之后，仍通过介电层50完全覆盖伪通孔32B的一些或全部。
接下来，参考图9，在介电层50上方形成金属部件56(包括56A、56B和56C)。导电部件56包括位于介电层50上方的(有源)金属帽56A、伪金属帽56B和再分布线(RDL)56C，其中部件56A、56B和56C位于相同的金属层中并且处于相同的水平处。相应步骤在图22所示的工艺流程中示出为步骤210。通孔54A形成在介电层50中，以将金属柱42和有源贯通孔32A连接至上面的金属帽56A和RDL 56C。RDL 56C包括位于介电层50上方的金属迹线(金属线)。根据本发明的一些实施例，在镀工艺中形成金属部件56和通孔54(包括54A和54B)，镀工艺包括沉积晶种层(未示出)，在晶种层上方形成和图案化光刻胶(未示出)，以及在晶种层上方镀诸如铜或铝的金属材料。晶种层和镀的材料可以由相同材料或不同材料形成。然后去除图案化的光刻胶，接着蚀刻晶种层的先前被图案化的光刻胶覆盖的部分。
金属帽56A与相应的有源贯通孔32A重叠，并且伪金属帽56B与相应的伪贯通孔32B重叠。金属帽56A和伪金属帽56B大于贯通孔32，从而使得屏蔽由相应的下面的贯通孔32A和32B引起的应力。根据其中形成开口52(图8)以暴露伪贯通孔32B的一些实施例，在介质层50中形成伪通孔54B，并将一些或全部伪金属帽56B物理地和电连接至伪贯通孔32B。根据可选实施例，没有形成开口52(图8)以暴露伪贯通孔32B，并且伪金属帽56B通过介电层50将金属帽56B与下面的伪贯通孔32B分离。因此，使用虚线示出伪通孔54B，以指示它们可以形成或可以不形成，并且可以形成一些伪通孔54B，而不形成其他伪通孔54B。
还如图9所示，将伪金属帽56B分成两个(或多个)部分，RDL 56C穿过伪金属帽56B的分离部分之间的间隙/间隔。金属帽56A和伪金属帽56B可具有圆形的顶视图，如图17至图21所示，从而使得由它们施加到周围介电结构的应力最小化。根据可选实施例，金属帽56A和伪金属帽56B可具有诸如六边形、八边形等的其他多边形。RDL 56C可以连接至金属帽56A、通孔54A、金属柱42和其他线导电部件。RDL 56C用于传导电压、信号、功率等。
参考图10，根据本发明的一些实施例，在图9所示的结构上方形成介电层60，接着在介电层60中形成开口。因此通过开口暴露金属帽56A和RDL 56C的一些部分。可以使用选自与形成介电层50的候选材料相同的材料来形成介电层60，该材料可以包括PBO、聚酰亚胺或BCB。然后形成包括58A和可能的58B的金属部件(RDL)58。RDL 58A延伸到介电层60中的开口中以接触金属帽56A和/或RDL 56C。相应步骤在图22所示的工艺流程中示出为步骤212。
根据本发明的一些实施例，一些RDL 58(标记为58B，其还称为金属桥)形成为互连伪金属帽56B的分离部分。结果，相同的伪金属帽56B的分离部分和相应的上面的金属桥58B组合形成集成金属部件。因此，金属桥58B可以改进伪金属帽56B的完整性，并且因此改进伪金属帽56B的应力屏蔽效应。
根据本发明的可选实施例，不形成一些或全部金属桥58B。因此，相同伪金属帽56A的分离部分彼此电断开，没有互连它们的金属部件。因此，使用虚线示出金属桥58B，以指示可以形成或可以不形成金属桥58B的一些或全部。当伪金属帽56B不具有上面连接的金属桥时，由介电层60完全覆盖伪金属帽56B的每个分离部分的整个顶面。此外，可以通过介电层50和60完全封闭伪金属帽56B的一个或多个分离部分。
图11示出形成介电层62和RDL 64。介电层62可以由选自与形成介电层50和60的候选材料相同组的材料形成。RDL 64还可以由包括铝、铜、钨和/或它们的合金的金属或金属合金形成。应当理解，尽管在所示的示例性实施例中，形成三层RDL(56、58和64)，但是RDL的数量可以具有诸如一层或多于两层的任何数量的层。
图12示出根据一些示例性实施例形成介电层66、凸块下金属(UBM)68和电连接件70。相应步骤在图22所示的工艺流程中示出为步骤214。介电层66可以由选自与形成介电层50和60的候选材料相同组的材料形成。例如，可以使用PBO、聚酰亚胺或BCB形成介电层66。在介电层66中形成开口以暴露下面的金属焊盘，下面的金属焊盘是RDL 64的部分。根据本发明的一些实施例，UBM 68形成为延伸到介电层66的开口内以接触RDL 64。UBM 68可以由镍、铜、钛或它们的多层形成。
然后形成电连接件70。形成电连接件70可包括将焊球放置到UBM 68的暴露部分上，并且然后回流该焊球。根据本发明的可选实施例，形成电连接件70包括实施镀步骤以在UBM 68上方形成焊料区并且然后回流焊料区。电连接件70还可以包括金属柱，或包括金属柱和焊帽，还可以通过镀来形成电连接件70。贯穿说明书，包括介电层28和上面的结构的组合的结构称为封装件100，其是包括多个器件管芯36的复合晶圆(并且以下还称为复合晶圆100)。
接下来，例如，通过在释放层22上投射UV光或激光束使封装件100从载体20脱黏，从而使得释放层22在UV光或激光束的热量下分解。因此使得封装件100与载体20去接合。图13中示出所得的封装件100。根据本发明的一些实施例，在所得的封装件100中，介电层28保留以作为封装件100的底部，并保护贯通孔32。然后实施激光钻孔以去除介电层28的一些部分以形成开口72，从而使得暴露有源贯通孔32A和伪贯通孔32B。接下来，实施切割(管芯锯切)工艺以将复合晶圆100分离成单独的封装件100'。相应步骤在图22所示的工艺流程中示出为步骤218。
图14示出封装件400与封装件100'的接合，从而形成叠层封装(PoP)结构/封装件300。相应步骤在图22所示的工艺流程中示出为步骤220。通过焊料区74实施接合，该焊料区74将贯通孔32A和32B连接至位于下面的封装件400中的金属焊盘406。根据本发明的一些实施例，封装件400包括封装衬底404和器件管芯402，该器件管芯402可以是诸如静态随机存取存储器(SRAM)管芯、动态随机存取存储器(DRAM)管芯等的存储器管芯。
根据本发明的可选实施例，替代在介电层28中形成开口72(图13)，以及然后将封装件400直接接合至封装件200'，在器件管芯36的背侧上形成背侧RDL。为了形成背侧RDL，首先对图12所示的结构实施载体开关，其中在载体20的去接合之前，通过粘合膜82将电连接件70附接至载体80(图15)。
接下来，载体20(图12)与复合晶圆100去接合，并且露出介电层28。然后形成金属部件26(包括金属帽26A、伪金属帽26B和RDL 26C)和通孔25/25B。该形成可以类似于导电部件56和通孔54的形成，因此不再重复细节。
然后形成如图15所示的介电层24和金属部件86A、86B、84A和84B。相应步骤在图22所示的工艺流程中示出为步骤216。介电层24可以由选自与形成介电层50和60的候选材料相同组的材料形成。金属部件86A/84A(其包括金属迹线86A和通孔84A)还可由包括铝、铜、钨和/或它们的合金的金属或金属合金形成。使用虚线示出一些通孔84B1以指示可以形成或可以不形成的这些通孔，并且焊料区(图16)74可以通过通孔84B1电连接至伪金属帽26B中的一些(但不是全部)分离的片(pieces)，或者连接至伪金属帽56B中全部分离的片(pieces)。可以形成(或者可以不形成)介电层85。然后将复合晶圆100与载体80去接合，并且实施切割/管芯锯切以将复合晶圆100分离成单独的封装件100'。然后将所得的封装件100'接合至封装件400，并且在图16中示出所得的封装件300。
根据如图14和图16所示的一些实施例，伪贯通孔32B是电浮置的。例如，在伪通孔32B的底侧上，封装件400中的金属焊盘406可以是伪焊盘，并且不电连接到任何下面的金属线和器件管芯402。在伪贯通孔32A的顶侧上，如果不形成通孔54B，则介电层50覆盖伪贯通孔32B的整个顶面。伪金属帽56B可以完全封闭在介电层50和60中(当不形成通孔54B和金属桥58B时)，或者可以与金属桥58B一起形成集成金属部件，该集成部件可以完全封闭在介电层50、60和62中(当不形成通孔54B时)。集成部件是电浮置的。如果通孔54B形成为连接至伪贯通孔32B，则金属桥58B、通孔54B和伪通孔32B中的相应几个可以形成互连的金属部件，其可以是电浮置的。
伪贯通孔32B还可以电接地或连接至非接地电压，并且可以通过器件管芯402提供电接地或非接地电压。根据一些实施例，贯通孔32B仍然是伪的，因为它们配置为不允许电流流过。这可以实现，因为电路径可以终止在金属桥58B处，其不电连接至任何上面的金属部件。当不形成金属桥58B时，电路径还可以终止在伪金属帽56B处。当不形成通孔54B时，电路径还可以终止在伪贯通孔32B的顶端处。
根据本发明的一些实施例，不形成区域78(图16)中所示的导电部件和其中的焊料区70，区域78包括通孔84B、金属迹线/焊盘86B的。因此，区域88中的全部金属部件的组合在介电材料24、28、48、50、60和62中完全绝缘，并且是电浮置的。可选地，不形成通孔25B，并且因此部件32B、54B、56B和/或58B在介电材料中完全绝缘。
根据本发明的可选实施例，可以形成多个通孔84B，每个通孔连接至相同伪金属帽26B的分离片中的一个，并且多个通孔84B可以电连接至相同的焊料区74。当不形成通孔84B时，根据这些实施例的伪金属帽26B还可在介电层24和28中完全绝缘。
图17示出如图14和图16所示的封装件100'的部分的顶视图，其中示出器件管芯36、有源贯通孔32A和伪贯通孔32B，并且不示出其他部件。应当理解，所示的贯通孔32的布局仅仅是实例，并且基于封装件100'的翘曲情况确定贯通孔32A和32B的实际数量和实际位置，并且选择为减少封装件100'的翘曲。可以从包括图17中的线A-A的平面获得图14和图16所示的封装件100'的截面图。
图18示出根据一些实施例的有源金属帽56A和伪金属帽56B的顶视图。可以将伪金属帽56B分成两个部分56B1和56B2，以允许RDL 56C穿过布置在它们之间的间隙/间隔。因此，尽管伪金属帽56B较大且占据相当大的面积，但是伪金属帽56B所使用的间隙仍可用于路由RDL 56C。图18左侧上的伪金属帽56B示出RDL 56C穿过伪金属帽56B的中间的实例。因此，不形成连接至相应的伪金属帽56B的通孔54B(参见图14和图16)。图18中间的伪金属帽56B示出RDL 56C穿过远离伪金属帽56B的中间位置的实例。因此，通孔54B可以形成或可以不形成为连接至相应的伪金属帽56B。图18右侧上的金属帽56表示有源金属帽56A。可选地，图18右侧上的金属帽56表示未分离的伪金属帽56B，其可形成在RDL稀疏区域中。
图19示出一些实施例，其中一个以上RDL 56C穿过一个伪金属帽56B。将左侧伪金属帽56B分成其中具有两个间隙的三个部分，每个间隙具有穿过的一个RDL 56C。将右侧伪金属帽56B分成两个部分，其中两个(或多个)RDL 56C穿过相同的间隙。
图20和图21示出RDL 56C不是直的的一些实施例。RDL 56C可以包括形成角度α的两个或多个部分，角度α在约30度和约150度之间的范围内。在图18至图21所示的实例中，使用虚线示出金属桥58B，以指示它们是可选地形成的。
本文提供了一些示例性尺寸。应当理解，这些尺寸是实例。参考图19、图20和图21(图18具有类似的尺寸)，再分布线56C的宽度A和间隔B和C可以小于约30μm。伪金属帽56B的直径D(或长度或宽度)可以在约140μm和约230μm之间的范围内。伪通孔32B的直径E(或长度或宽度)可以在约100μm和约190μm之间的范围内。伪贯通孔54B的直径F(长度或宽度)可以在约10μm和约60μm之间的范围内。
再次参考图16，在器件管芯36的背侧上形成伪金属帽26B，其中RDL26C穿过伪金属帽26B。伪金属帽26B和RDL 26C的布局和相应的尺寸可以与图19至图21中所示的大致相同，并且在此不再重复。
本发明的实施例具有一些有益的部件。形成伪贯通孔以提供用于接合至封装件400的额外的锚定力，并且减少封装件的翘曲。然而，伪贯通孔对RDL层产生应力。为了屏蔽由伪贯通孔导致的应力，大的伪金属帽直接形成在伪贯通孔的上方或下方。伪贯通孔占据大的芯片面积，并且不利地影响RDL的路由。因此，根据本发明的实施例，将伪金属帽分成较小部分，并且通过较小部分之间的间隙路由RDL。
根据本发明的一些实施例，一种封装件包括第一介电层，位于第一介电层上方且附接至第一介电层的器件管芯，有源贯通孔和伪贯通孔以及密封器件管芯、有源贯通孔和伪贯通孔的密封材料。封装件还包括位于器件管芯、有源贯通孔和伪贯通孔上方并接触器件管芯、有源贯通孔和伪贯通孔的第二介电层。有源金属帽位于第二介电层上方并接触第二介电层并电连接至有源贯通孔。有源金属帽与有源贯通孔重叠。伪金属帽位于第二介电层上方并接触第二介电层。伪金属帽与伪贯通孔重叠。通过间隙将伪金属帽分成第一部分和第二部分。再分布线穿过伪金属帽的第一部分和第二部分之间的间隙。
根据本发明的一些实施例，一种封装件包括器件管芯、伪贯通孔、密封器件管芯和伪贯通孔的密封材料，以及位于器件管芯、伪贯通孔和密封材料上方并且与其接触的第一介电层。伪金属帽位于第一介电层上方并且接触第一介电层，其中伪金属帽与伪贯通孔重叠并且延伸超过伪贯通孔的边缘。再分布线与伪金属帽处于相同的水平。再分布线将伪金属帽分成第一部分和第二部分。
根据本发明的一些实施例，一种方法包括将器件管芯附接至第一介电层，在第一介电层上方形成有源贯通孔和伪贯通孔，将器件管芯、有源贯通孔和伪贯通孔密封在密封材料中，在密封材料上方形成第二介电层，以及在共同的工艺中沉积有源金属帽，再分布线和伪金属帽。有源金属帽和伪金属帽分别与有源贯通孔和伪贯通孔重叠。通过再分布线将伪金属帽分成第一部分和第二部分。
根据本发明的一个实施例，提供了一种封装件，包括：第一介电层；器件管芯，位于所述第一介电层上方并且附接至所述第一介电层；有源贯通孔和伪贯通孔；密封材料，密封所述器件管芯、所述有源贯通孔和所述伪贯通孔；第二介电层，位于所述器件管芯、所述有源贯通孔和所述伪贯通孔上方并且接触所述器件管芯、所述有源贯通孔和所述伪贯通孔；有源金属帽，位于所述第二介电层上方并且接触所述第二介电层并且电连接至所述有源贯通孔，其中，所述有源金属帽与所述有源贯通孔重叠；伪金属帽，位于所述第二介电层上方并且接触所述第二介电层，其中，所述伪金属帽与所述伪贯通孔重叠，并且通过第一间隙将所述伪金属帽分成第一部分和第二部分；以及第一再分布线，穿过所述第一间隙。
在上述封装件中，所述伪贯通孔的所述第一部分和所述第二部分协作地形成圆形形状、六边形形状或八边形形状。
在上述封装件中，所述伪贯通孔的所述第一部分和所述第二部分中的至少一个是电浮置的。
在上述封装件中，还包括位于所述第二介电层中的通孔，其中，所述通孔连接所述伪金属帽的所述第一部分，并且所述伪贯通孔和所述伪金属帽的所述第一部分的组合是电浮置的。
在上述封装件中，还包括位于所述第二介电层中的通孔，其中，所述通孔连接所述伪金属帽的所述第一部分，并且所述伪贯通孔和所述伪金属帽的所述第一部分组合连接至电压并且配置为不允许电流通过。
在上述封装件中，还包括互连所述伪金属帽的所述第一部分和所述第二部分的金属桥。
在上述封装件中，所述金属桥以及所述伪金属帽的所述第一部分和所述第二部分的组合是电浮置的。
在上述封装件中，还包括穿过所述第一间隙的第二再分布线。
在上述封装件中，所述伪金属帽通过第二间隙分成第三部分，第二间隙位于所述伪金属帽的所述第二部分和所述第三部分之间，并且所述封装件还包括位于所述第二间隙中的第二再分布线。
根据本发明的另一实施例，还提供了一种封装件，包括：器件管芯；伪贯通孔；密封材料，密封所述器件管芯和所述伪贯通孔；第一介电层，位于所述器件管芯、所述伪贯通孔和所述密封材料上方并且接触所述器件管芯、所述伪贯通孔和所述密封材料；第一伪金属帽，位于所述第一介电层上方并且接触所述第一介电层，其中，所述第一伪金属帽与所述伪贯通孔重叠并且延伸超过所述伪贯通孔的边缘；以及第一再分布线，在与所述第一伪金属帽相同的水平处，其中，所述第一再分布线将所述第一伪金属帽分成第一部分和第二部分。
在上述封装件中，所述第一伪金属帽的所述第一部分和所述第二部分彼此电去耦。
在上述封装件中，还包括位于所述第一伪金属帽上方的金属桥，其中，所述金属桥互连所述第一伪金属帽的所述第一部分和所述第二部分。
在上述封装件中，还包括位于所述第一介电层中的通孔，其中，所述通孔将所述第一伪金属帽的所述第一部分连接至所述伪贯通孔，并且所述第一伪金属帽的所述第二部分是电浮置的。
在上述封装件中，还包括：第二介电层，位于所述伪贯通孔和所述密封材料下方并且接触所述伪贯通孔和所述密封材料；第二伪金属帽，位于所述第二介电层下方并且接触所述第二介电层，其中，所述伪贯通孔与所述第二伪金属帽的部分重叠；以及第二再分布线，在与所述第二伪金属帽相同的水平处，其中，所述第二再分布线将所述第二伪金属帽分成彼此物理分离的第三部分和第四部分。
在上述封装件中，所述第二伪金属帽的所述第一部分和所述第二部分的每个完全封闭在介电材料中。
根据本发明的又一实施例，还提供了一种形成封装件的方法，包括：将器件管芯附接至第一介电层；在所述第一介电层上方形成有源贯通孔和伪贯通孔；将所述器件管芯、所述有源贯通孔和所述伪贯通孔密封在密封材料中；在所述密封材料上方形成第二介电层；以及在共同的工艺中沉积有源金属帽、再分布线和伪金属帽，其中，所述有源金属帽和所述伪金属帽分别与所述有源贯通孔和所述伪贯通孔重叠，并且通过所述再分布线将所述伪金属帽分成第一部分和第二部分。
在上述方法中，所述伪金属帽的所述第一部分和所述第二部分分别通过第一间隙和第二间隙与所述再分布线分离，并且所述方法还包括形成填充在所述第一间隙和所述第二间隙内的第三介电层。
在上述方法中，还包括形成延伸到所述第三介电层内的多个导电部件，其中，所述伪金属帽的所述第一部分和所述第二部分是电浮置的。
在上述方法中，还包括形成延伸到所述第三介电层内的多个导电部件，其中，所述多个导电部件中的金属桥互连所述伪金属帽的所述第一部分和所述第二部分，并且所述金属桥是电浮置的。
在上述方法中，还包括在所述共同的工艺中形成通孔，所述通孔将所述伪金属帽的所述第一部分连接至所述伪贯通孔，其中，所述通孔位于所述第二介电层中，并且在所述第二介电层中没有通孔连接至所述伪金属帽的所述第二部分。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种封装件，包括：
第一介电层；
器件管芯，位于所述第一介电层上方并且附接至所述第一介电层；
有源贯通孔和伪贯通孔；
密封材料，密封所述器件管芯、所述有源贯通孔和所述伪贯通孔；
第二介电层，位于所述器件管芯、所述有源贯通孔和所述伪贯通孔上方并且接触所述器件管芯、所述有源贯通孔和所述伪贯通孔；
有源金属帽，位于所述第二介电层上方并且接触所述第二介电层并且电连接至所述有源贯通孔，其中，所述有源金属帽与所述有源贯通孔重叠；
伪金属帽，位于所述第二介电层上方并且接触所述第二介电层，其中，所述伪金属帽与所述伪贯通孔重叠，并且通过第一间隙将所述伪金属帽分成第一部分和第二部分；以及
第一再分布线，穿过所述第一间隙。
2.根据权利要求1所述的封装件，其中，所述伪贯通孔的所述第一部分和所述第二部分协作地形成圆形形状、六边形形状或八边形形状。
3.根据权利要求1所述的封装件，其中，所述伪贯通孔的所述第一部分和所述第二部分中的至少一个是电浮置的。
4.根据权利要求3所述的封装件，还包括位于所述第二介电层中的通孔，其中，所述通孔连接所述伪金属帽的所述第一部分，并且所述伪贯通孔和所述伪金属帽的所述第一部分的组合是电浮置的。
5.根据权利要求3所述的封装件，还包括位于所述第二介电层中的通孔，其中，所述通孔连接所述伪金属帽的所述第一部分，并且所述伪贯通孔和所述伪金属帽的所述第一部分组合连接至电压并且配置为不允许电流通过。
6.根据权利要求1所述的封装件，还包括互连所述伪金属帽的所述第一部分和所述第二部分的金属桥。
7.根据权利要求6所述的封装件，其中，所述金属桥以及所述伪金属帽的所述第一部分和所述第二部分的组合是电浮置的。
8.根据权利要求1所述的封装件，还包括穿过所述第一间隙的第二再分布线。
9.一种封装件，包括：
器件管芯；
伪贯通孔；
密封材料，密封所述器件管芯和所述伪贯通孔；
第一介电层，位于所述器件管芯、所述伪贯通孔和所述密封材料上方并且接触所述器件管芯、所述伪贯通孔和所述密封材料；
第一伪金属帽，位于所述第一介电层上方并且接触所述第一介电层，其中，所述第一伪金属帽与所述伪贯通孔重叠并且延伸超过所述伪贯通孔的边缘；以及
第一再分布线，在与所述第一伪金属帽相同的水平处，其中，所述第一再分布线将所述第一伪金属帽分成第一部分和第二部分。
10.一种形成封装件的方法，包括：
将器件管芯附接至第一介电层；
在所述第一介电层上方形成有源贯通孔和伪贯通孔；
将所述器件管芯、所述有源贯通孔和所述伪贯通孔密封在密封材料中；
在所述密封材料上方形成第二介电层；以及
在共同的工艺中沉积有源金属帽、再分布线和伪金属帽，其中，所述有源金属帽和所述伪金属帽分别与所述有源贯通孔和所述伪贯通孔重叠，并且通过所述再分布线将所述伪金属帽分成第一部分和第二部分。
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