CN103681367A - 封装方法和封装器件 - Google Patents

封装方法和封装器件 Download PDF

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CN103681367A
CN103681367A CN201310021904.8A CN201310021904A CN103681367A CN 103681367 A CN103681367 A CN 103681367A CN 201310021904 A CN201310021904 A CN 201310021904A CN 103681367 A CN103681367 A CN 103681367A
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insulating material
integrated circuit
rdl
circuit lead
patterning
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CN103681367B (zh
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潘国龙
曾明鸿
陈承先
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开了封装方法和封装器件。在一个实施例中，封装半导体器件的方法包括在载体上方形成第一再分布层(RDL)并且在第一RDL上方形成多个装配通孔(TAV)。集成电路管芯连接在第一RDL上方，并且在第一RDL、TAV和集成电路管芯上方形成模塑料。在模塑料、TAV和集成电路管芯上方形成第二RDL。

Description

封装方法和封装器件
技术领域
本发明总的来说涉及半导体领域，更具体地，涉及封装方法和封装器件。
背景技术
半导体器件被用于各种电子应用，诸如个人计算机、移动电话、数码相机和其它电子设备。通常通过在半导体衬底上方顺序地沉积绝缘层或介电层、导电层和半导体材料层，然后使用光刻图案化各个材料层以在其上形成电路部件和元件来制造半导体器件。
半导体工业通过持续减小最小部件尺寸来不断提高各种电子部件(例如，晶体管、二极管、电阻器、电容器等)的集成密度，这允许将更多的部件集成到给定面积中。在一些应用中，这些更小的电子部件还需要更小的封装件，其使用比过去的封装件更小的面积。
叠层封装(PoP)技术因为其允许将集成电路密集地集成到较小整体封装件中的能力而越来越受欢迎。PoP技术应用于许多先进的手持设备，诸如智能电话和平板电脑。
发明内容
根据本发明的一个方面，提供了一种封装半导体器件的方法，包括：在载体上方形成第一再分布层(RDL)；在第一RDL上方形成多个装配通孔(TAV)；将集成电路管芯连接在第一RDL上方；在第一RDL、TAV和集成电路管芯上方形成模塑料；以及在模塑料、TAV和集成电路管芯上方形成第二RDL。
优选地，该方法进一步包括去除载体。
优选地，将集成电路管芯连接在第一RDL上方包括：使用管芯粘附膜(DAF)或粘合剂将集成电路管芯附接至第一RDL。
优选地，该方法进一步包括将多个导电凸块连接至第二RDL。
优选地，将集成电路管芯连接在第一RDL上方包括：连接包括设置在集成电路管芯表面上的绝缘材料内的多个接触件的集成电路管芯，并且形成第二RDL包括：将第二RDL的部分连接至集成电路管芯的表面上的多个接触件。
优选地，形成多个TAV包括在部分第一RDL上方镀多个TAV。
优选地，形成多个TAV包括在第一RDL的边界区域中形成多个TAV。
优选地，将集成电路管芯连接在第一RDL上方包括将集成电路管芯连接至第一RDL的中心区域。
根据本发明的另一方面，提供了一种封装半导体器件的方法，包括：在载体上方形成第一绝缘材料；图案化第一绝缘材料；在图案化的第一绝缘材料上方形成第一导电材料；图案化第一导电材料；在图案化的第一导电材料和图案化的第一绝缘材料上方形成第二绝缘材料；图案化第二绝缘材料以露出位于第二绝缘材料的边界区域中的部分第一导电材料；在第二绝缘材料的边界区域中，在第一导电材料的露出部分上方形成多个装配通孔(TAV)；将集成电路管芯连接在第二绝缘材料的中心区域中的第二绝缘材料上方；在多个TAV和集成电路管芯之间的第二绝缘材料上方形成模塑料；在多个TAV、集成电路管芯和第二绝缘材料上方形成第三绝缘材料；图案化第三绝缘材料；在图案化的第三绝缘材料上方形成第二导电材料；图案化第二导电材料；在图案化的第二导电材料和图案化的第三绝缘材料上方形成第四绝缘材料；图案化第四绝缘材料以露出部分第二导电材料；在第二导电材料的露出部分上方形成多个导电凸块；以及去除载体。
优选地，在多个TAV和集成电路管芯之间的第二绝缘材料上方形成模塑料包括：在多个TAV的顶面上方和集成电路管芯的顶面上方形成模塑料，并且该方法进一步包括：从多个TAV的顶面上方和集成电路管芯的顶面上方去除模塑料。
优选地，从多个TAV的顶面上方和集成电路管芯的顶面上方去除模塑料包括化学机械抛光(CMP)工艺、蚀刻工艺或它们的组合。
优选地，形成第一绝缘材料、形成第二绝缘材料、形成第三绝缘材料或形成第四绝缘材料包括形成选自基本由聚酰亚胺、聚合物、聚苯并恶唑(PBO)和它们的组合所组成的组中的材料。
优选地，将集成电路管芯连接在第二绝缘材料上方包括连接包括位于集成电路管芯表面上的多个接触件的集成电路管芯。
优选地，图案化第三绝缘材料包括露出位于集成电路管芯的表面上的多个接触件，并且在图案化的第三绝缘材料上方形成第二导电材料包括将部分第二导电材料连接至位于集成电路管芯的表面上的多个接触件。
根据本发明的又一方面，提供了一种封装半导体器件，包括：第一再分布层(RDL)；集成电路管芯，设置在第一RDL的中心区域上方；管芯粘附膜(DAF)或粘合剂，设置在第一RDL和集成电路管芯之间；第二RDL，设置在集成电路管芯上方并与集成电路管芯电连接；模塑料，设置在第一RDL和第二RDL之间；以及多个装配通孔(TAV)，设置在第一RDL的边界区域中的模塑料中。
优选地，模塑料设置在集成电路管芯周围。
优选地，该封装半导体器件进一步包括连接至第二RDL的多个导电凸块。
优选地，多个导电凸块包括焊料凸块或可控坍塌芯片连接(C4)凸块。
根据本发明的再一方面，提供了一种叠层封装(PoP)器件，其包括根据上述封装半导体器件。
优选地，封装半导体器件包括第一封装半导体器件，并且集成电路管芯包括第一集成电路管芯，该PoP器件进一步包括具有连接至多个导电凸块的第二集成电路管芯的第二封装半导体器件。
附图说明
为了更完整地理解本发明及其优点，现在结合附图作为参考进行以下描述，其中：
图1至图18是示出根据本发明实施例的封装集成电路管芯的方法的截面图；
图19是根据实施例的PoP器件的截面图；以及
图20是示出根据实施例的封装集成电路管芯的方法的流程图。
除非另有指明，否则不同图中对应的数字和符号通常代表对应的部件。绘制附图是为了清楚地说明各个实施例的相关内容并且无需按比例绘制。
具体实施方式
以下详细讨论本发明的实施例的制造和使用。然而，应该理解，本发明提供了许多可在各种具体环境中具体化的可应用发明概念。所讨论的具体实施例仅是本发明的制造和使用的具体方式的说明，但不限制本发明的范围。
本发明的实施例涉及用于封装半导体器件的方法和结构。本文将描述新的PoP器件、封装的半导体器件和封装方法，其中，首先在载体上方形成第一再分布层(RDL)，集成电路管芯被附接至第一RDL，然后在集成电路管芯上方形成第二RDL。
图1至图18是示出根据本发明实施例的封装集成电路管芯114(参见图9)的方法的截面图。首先参照图1，提供载体100。在一些实施例中，载体100包括晶圆。作为实例，载体100可包括半导体材料或玻璃。可选地，载体100可包括其它材料。
如图2所示，在载体100上方形成第一绝缘材料103。第一绝缘材料103包括设置在载体100上方的第一层102和设置在第一层102上方的第二层104。例如，第一绝缘材料103的第一层102包括诸如具有约1μm厚度的光热转换(LTHC)膜的感光材料，虽然可选地，第一层102还可以包括其它材料和尺寸。作为实例，第一绝缘材料103的第二层104包括诸如聚酰亚胺、聚合物、聚苯并恶唑(PBO)或者它们的多层或组合的绝缘材料。例如，第二层104的厚度为约5μm至10μm。可选地，第一绝缘材料103的第二层104可包括其它材料和尺寸。在一些实施例中，第一绝缘材料103不包括第一层102。
如图3所示，使用光刻来图案化第一绝缘材料103。如果第一绝缘材料103包括第一层102，则在一些实施例中不对第一层102进行图案化。图案化的第一绝缘材料103形成用于封装件的第一再分布层(RDL)的一部分(在图3至图17中没有标出，参见图18所示的第一RDL132)，这将在本文进行进一步的描述。第一绝缘材料103中的图案包括位于第一绝缘材料103中，至少在第二层104中的开口。在一些实施例中，还对第一层102进行图案化(未示出)。第一绝缘材料103中的图案形成在第一绝缘材料103的中心区域。在一些实施例中，第一绝缘材料103中的图案还形成在第一绝缘材料103的边界区域，将在文中进行进一步的描述。
在一些实施例中，通过在第一绝缘材料103上方沉积光刻胶层(未示出)，并且将光刻胶层暴露给从其上形成有期望图案的光刻掩模反射的或通过其上具有期望图案的光刻掩模的光或能量，利用光刻来图案化第一绝缘材料103。光刻胶层被显影，并且灰化或蚀刻掉部分光刻胶层，在第一绝缘材料103的顶部上留下图案化的光刻胶层。然后，将光刻胶层用作蚀刻掩模同时蚀刻掉第一绝缘材料103的露出部分。然后，去除光刻胶层。
如图4所示，第一导电材料106形成在图案化的第一绝缘材料103上方。例如，第一导电材料106包括Cu、Al、其它金属或者它们的多层或组合。例如，第一导电材料106具有约4μm至7μm的厚度。可选地，第一导电材料106可包括其它材料和尺寸。第一导电材料106对第一绝缘材料103中的图案加衬。例如，在一些实施例中，第一导电材料106基本共形并均匀地对第一绝缘材料103的第二层104的顶面、第一绝缘材料103的第一层102的顶面的露出部分和第一绝缘材料103的第二层104中的图案的侧壁加衬。在其他实施例中，第一导电材料106可以是非共形的。
如图5所示，使用光刻来图案化第一导电材料106(例如，如第一绝缘材料103所描述的，通过在第一导电材料106上方形成光刻胶，图案化光刻胶，并将光刻胶用作蚀刻掩模)。第一导电材料106包括封装件的第一RDL132的一部分。在第一绝缘材料103的中心区域中，第一导电材料106对第一绝缘材料103中的图案加衬。第一导电材料106包括位于第一绝缘材料103的边界区域上方的平台(landing)区域或接触焊盘。例如，在一些实施例中，第一导电材料106可包括将中心区域中的图案和边界区域中的平台区域或接触焊盘连接在一起的导线的扇出区域。
在图1至图18所示的实施例中，如图3所示，仅在中心区域中图案化第一绝缘材料103的第二层104。可选地，如图19所示，还可以在边界区域中图案化第一绝缘材料103的第二层104以形成位于封装器件的边界区域的第一RDL132中的外部连接件。
然后，参照图6，在图案化第一导电材料106之后，第二绝缘材料108形成在图案化的第一导电材料106和图案化的第一绝缘材料103上方。第二绝缘材料108包括第一RDL132的一部分。例如，第二绝缘材料108包括与本文描述的第一绝缘材料103的第二层104的材料和厚度相似的材料和厚度。可选地，第二绝缘材料108可包括其它材料和厚度。
如图7所示，使用光刻来图案化第二绝缘材料108。图案化第二绝缘材料108以在第二绝缘材料108的边界区域中露出部分第一导电材料106。在一些实施例中，第一导电材料106的露出部分包括平台区域或接触焊盘。
如图8所示，多个装配通孔(TAV)110形成在位于第二绝缘材料108的边界区域中的第一导电材料106的露出部分上方。在一些实施例中，TAV110包括Cu或Cu合金。例如，TAV110具有约60μm至90μm的宽度和约100μm至120μm的高度或厚度。可选地，TAV110可包括其它材料和尺寸。在一些实施例中，在俯视图中，TAV110具有圆形、椭圆形、正方形或矩形的形状。可选地，TAV110可具有其它形状。在一些实施例中，使用喷镀工艺形成TAV110。可选地，例如，在其他实施例中，可在第二绝缘材料108上方沉积并图案化导电材料以形成TAV110。
如图9所示，提供集成电路管芯114并将其连接至第一RDL。集成电路管芯114包括可形成在包括硅或其它半导体材料的半导体衬底上方的半导体电路。集成电路管芯114可包括有源器件或电路(未示出)，它们可包括晶体管、二极管、电容器、电感器。作为实例，集成电路管芯114可包括存储器件、逻辑器件或其他类型的电路。
集成电路管芯114被连接至第二绝缘材料108的中心区域。集成电路管芯114被朝上安装，其中接触件116位于其顶面。集成电路管芯114连接在第一RDL132的上方，例如位于第一RDL132的第二绝缘材料108的上方。集成电路管芯114通过管芯粘附膜(DAF)或粘合剂112附接至第二绝缘材料108的中心区域。集成电路管芯114包括设置在其顶面上形成的第三绝缘材料118中的多个接触件116。作为实例，接触件116包括Cu、Cu合金或其它金属。在一些实施例中，接触件116包括镀通孔。可选地，接触件116可包括其它材料并且可使用其它方法形成。在一些实施例中，第三绝缘材料118包括与第一绝缘材料103的第二层104的材料相似的材料。可选地，第三绝缘材料118可包括其它类型的材料。
如图10所示，模塑料120形成在第一RDL132上方，例如位于第一RDL132的第二绝缘材料108的顶面上方、TAV110的顶面上方以及集成电路管芯114的顶面上方。在一些实施例中，作为实例，模塑料120包括聚酰亚胺、环氧基树脂、丙烯酸盐或二氧化硅，虽然可选地，模塑料120可包括其它材料。如图10所示，模塑料120开始沉积在TAV110的顶面上方和集成电路管芯114的顶面上方。如图11所示，化学机械抛光(CMP)工艺、蚀刻工艺或它们的组合用于从TAV110的顶面上方和集成电路管芯114的顶面上方去除部分模塑料120。模塑料120被设置在集成电路管芯114周围、集成电路管芯114和TAV110之间以及TAV110之间。
然后，第二RDL134(在图12至图17中没有标出，参见图18所示的第二RDL134)形成在模塑料120以及TAV110和集成电路管芯114的露出顶面的上方。如图12所示，通过在模塑料120、TAV110和集成电路管芯114上方形成第四绝缘材料122来形成第二RDL134。第四绝缘材料122在文中(例如，在一些权利要求中)还被称为第三绝缘材料。在一些实施例中，第四绝缘材料122包括与第一绝缘材料103的第二层104相似的材料和厚度。可选地，第四绝缘材料122可包括其它材料和尺寸。
如图13所示，使用光刻来图案化第四绝缘材料122。图案化的第四绝缘材料122形成用于封装的第二RDL134的一部分。第四绝缘材料122中的图案包括TAV110和集成电路管芯114的接触件116上方的第四绝缘材料122中的开口。第四绝缘材料122中的图案形成在集成电路管芯114的接触件116上方的第四绝缘材料122的中心区域中。例如，在一些实施例中，图案化第四绝缘材料122包括露出集成电路管芯114的顶面上的多个接触件116。第四绝缘材料122中的图案还形成在TAV110上方的第四绝缘材料122的边界区域中。
如图14所示，第二导电材料124形成在图案化的第四绝缘材料122上方。在一些实施例中，第二导电材料124包括与第一导电材料106相似的材料和尺寸。可选地，第二导电材料124可包括其它材料和尺寸。第二导电材料124对第四绝缘材料122中的图案加衬。例如，在一些实施例中，第二导电材料124基本共形且均匀地对第四绝缘材料122的顶面、TAV110的露出部分、集成电路管芯114露出的接触件116和第四绝缘材料122中的图案的侧壁加衬。在其他实施例中，第二导电材料124可以是非共形的。
部分第二导电材料124连接至集成电路管芯114顶面上的多个接触件116的顶面。部分第二导电材料124还连接至TAV110的顶面。
如图15所示，使用光刻来图案化第二导电材料124。第二导电材料124包括封装件的第二RDL134的一部分。在第四绝缘材料122的中心区域和边界区域中，第二导电材料124对第四绝缘材料122的图案加衬。第二导电材料124包括位于第四绝缘材料122的边界区域和中心区域上方的平台区域或接触焊盘。例如，在一些实施例中，第二导电材料124可包括将中心区域中的图案和边界区域中的平台区域或接触焊盘连接在一起的导线的扇出区域。作为另一个实例，在一些实施例中，第二导电材料124的平台区域和/或接触焊盘可包括凸块下金属化(UBM)结构。
如图16所示，第五绝缘材料126形成在图案化的第二导电材料124和图案化的第四绝缘材料122上方。第五绝缘材料126在本文中(例如，在一些权利要求中)还被称为第四绝缘材料。第五绝缘材料126包括第二RDL134的一部分。例如，第五绝缘材料126包括与本文描述的第一绝缘材料103的第二层104的材料和厚度相似的材料和厚度。可选地，第五绝缘材料126可包括其它材料和尺寸。
如图17所示，使用光刻来图案化第五绝缘材料126。图案化第五绝缘材料126以露出第五绝缘材料126的边界区域和中心区域中的第二导电材料124的部分。在一些实施例中，第五绝缘材料126的露出部分包括平台区域或接触焊盘。
然后，如图17所示，通过图案化的第五绝缘材料126，多个导电凸块128连接至第二RDL134，例如连接至第二导电材料124的露出部分。例如，在一些实施例中，多个导电凸块128包括焊料凸块或可控坍塌芯片连接(C4)凸块。例如，导电凸块128可包括Cu、Cu合金和/或焊料，并且一些可能包括金属柱。可选地，导电凸块128可包括其它类型的接触件或外部连接件，并且导电凸块128可包括其它材料。
然后，去除载体100，如图18所示，其示出了根据实施例的包括集成电路管芯114的封装半导体器件130的截面图。如果第一绝缘材料103包括第一层102，则第一绝缘材料103的第一层102也被去除。根据本发明的一些实施例，第一绝缘材料103、第一导电材料106和第二绝缘材料108包括第一RDL132。根据一些实施例，第四绝缘材料122、第二导电材料124和第五绝缘材料126包括第二RDL134。
模塑料120设置在第一RDL132和第二RDL134之间。TAV110将第一RDL132连接至第二RDL134并且为封装半导体器件130提供垂直电连接。第一RDL132和第二RDL134为封装半导体器件130提供水平电连接。
图1至图18所示TAV110在封装半导体器件130的每一侧上以两行进行配置。可选地，在一些实施例中，TAV110可以以其它数量的行来配置，而且在俯视图中可沿着封装半导体器件130的整个边界形成TAV110。TAV110可在封装半导体器件130的边界中以单行进行配置，或者TAV110可在封装半导体器件130的边界中以三行或更多行进行配置。例如，可在封装半导体器件130的俯视图或仰视图中，以阵列图案、沿边界以一行或多行、或者以其它配置或随机配置来配置导电凸块128。作为另一个实例，可在封装半导体器件130的俯视图或仰视图中，以阵列图案、沿边界以一行或多行、或者以其它配置或随机配置来配置第一RDL132的第一导电材料106的露出部分。
用于封装半导体器件130的各个材料层的沉积方法包括通常用于半导体制造和封装工艺的方法。作为实例，根据所形成的材料类型，化学汽相沉积(VCD)、等离子体增强CVD(PECVD)、溅射、涂旋和喷镀技术可用于形成封装半导体器件130的各个材料层。可选地，其它方法可用于沉积或形成本文描述的各个材料层。
在图1至图17中，仅示出在载体100上方封装一个集成电路114。可选地，多个集成电路114可封装在载体100上方，并且在去除载体100之前或之后，沿划线将封装半导体器件130切割成多个封装半导体器件130。
图19是根据实施例的PoP器件140的截面图。根据叠层封装(PoP)结构的实施例，可将图18所示的两个封装半导体器件130(例如，图19中的封装半导体器件130a和130b)连接到一起。在图19所示的实施例中，连接至封装半导体器件130a的第二RDL134a的导电凸块128a被连接至封装半导体器件130b的第一RDL132b的第一导电材料106b的露出部分。
例如，在图19中，第一封装半导体器件130a包括封装第一集成电路管芯114a，并且第二封装半导体器件130b包括封装第二集成电路管芯114b。第二封装半导体器件130b连接至与第一封装半导体器件130a的第二RDL134a连接的多个导电凸块128a。
图19中还示出，根据一些实施例，在封装半导体器件130a和130b的第一RDL132a和132b的边界区域和中心区域中分别露出部分第一导电材料106a和106b。
根据一些实施例，三个或更多个封装半导体器件130、130a和130b可使用导电凸块128、128a和128b以及第一RDL132、132a和132b垂直堆叠并互相连接。例如，在图19中，其他的封装半导体器件130可连接至封装半导体器件130b的导电凸块128b或连接至封装半导体器件130a的导电凸块128a露出的第一导电材料106a。
在图19中，封装半导体器件130、130a和130b中的两个连接在一起以形成PoP器件140。可选地，本文所述的封装半导体器件130、130a和130b可连接至另一种类型的封装半导体器件。例如，以倒装芯片方式安装在衬底上或使用引线接合法安装在衬底上的集成电路管芯可使用导电凸块128、128a、128b或第一RDL132、132a、132b分别连接至封装半导体器件130、130a和130b。可选地，本文所述的封装半导体器件130、130a和130b可以连接至以其他封装类型封装的集成电路管芯以形成3DIC和其它垂直堆叠的集成电路结构。
图20是示出根据实施例的封装集成电路管芯114的方法的流程图150。在步骤152中，第一RDL132形成在载体100上方。在步骤154中，多个TAV110形成在第一RDL132上方。在步骤156中，集成电路管芯114连接在第一RDL132上方。在步骤158中，模塑料120形成在TAV110和集成电路管芯114之间的第一RDL132上方。模塑料120还形成在多个TAV110之间。在步骤160中，第二RDL134形成在模塑料120、TAV110和集成电路管芯114上方。
本发明的实施例包括封装半导体器件的方法，并且还包括使用本文所描述的方法封装的封装半导体器件。本发明的实施例还包括PoP器件，其包括本文描述的封装半导体器件。
本发明实施例的优点包括提供了新的封装器件和方法，其提供了在封装工艺流程中需要较少步骤的封装半导体器件的流水线方法。利用数量减少的工艺步骤来提供创新的3D叠层封装结构。由于简化的工艺流程，本文描述的封装技术成本低并且产量高。新的封装结构和设计在封装工艺流程中很容易实施，并且可用于封装许多类型的集成电路。新的封装方法和结构有利地要求只使用一个载体100。
根据本发明的一个实施例，封装半导体器件的方法包括在载体上方形成第一RDL以及在第一RDL上方形成多个TAV。集成电路管芯连接在第一RDL上方，并且在第一RDL、TAV和集成电路管芯上方形成模塑料。在模塑料、TAV和集成电路管芯上方形成第二RDL。
根据本发明的另一个实施例，封装半导体器件的方法包括：在载体上方形成第一绝缘材料，图案化第一绝缘材料并且在图案化的第一绝缘材料上方形成第一导电材料。该方法包括图案化第一导电材料，在图案化的第一导电材料和图案化的第一绝缘材料上方形成第二绝缘材料，并且图案化第二绝缘材料以露出第二绝缘材料的边界区域中的部分第一导电材料。在第二绝缘材料的边界区域中，在第一导电材料的露出部分上方形成多个TAV。集成电路管芯在第二绝缘材料的中心区域中连接至第二绝缘材料上方，并且模塑料形成在多个TAV和集成电路管芯之间的第一RDL上方。第三绝缘材料形成在多个TAV、集成电路管芯和第二绝缘材料上方。图案化第三绝缘材料，并且在图案化的第三绝缘材料上方形成第二导电材料。该方法包括图案化第二导电材料，在图案化的第二导电材料和图案化的第三绝缘材料上方形成第四绝缘材料，以及图案化第四绝缘材料以露出部分第二导电材料。在第二导电材料的露出部分上方形成多个导电凸块，并且去除载体。
根据又一实施例，封装半导体器件包括第一RDL、设置在第一RDL的中心区域上方的集成电路管芯以及设置在第一RDL和集成电路管芯之间的DAF或粘合剂。第二RDL设置在集成电路管芯上方并与其电连接。模塑料设置在第一RDL和第二RDL之间，并且多个TAV设置在第一RDL的边界区域中的模塑料中。
尽管已经详细描述了本发明的一些实施例及它们优点，但是应当理解，在不背离所附权利要求限定的本发明精神和范围的情况下，可以进行各种改变、替换和更改。例如，本领域技术人员很容易理解，可以改变文中描述的许多特征、功能、工艺以及材料，而剩余的特征、功能、工艺、以及材料在本发明的范围内。此外，本申请的范围不旨在限于说明书中描述的工艺、机械装置、制造、物质组成、工具、方法和步骤的特定实施例。根据本发明的内容本领域技术人员应容易地理解，根据本发明可以使用与文中描述的对应实施例执行基本相同的功能或实现基本相同结果的目前现有或即将开发的工艺、机械装置、制造、物质组成、工具、方法或步骤。因此，所附权利要求旨在包括在这种工艺机械装置、制造、物质组成、工具、方法或步骤的范围内。

Claims (10)

1.一种封装半导体器件的方法，所述方法包括：
在载体上方形成第一再分布层(RDL)；
在所述第一RDL上方形成多个装配通孔(TAV)；
将集成电路管芯连接在所述第一RDL上方；
在所述第一RDL、所述TAV和所述集成电路管芯上方形成模塑料；以及
在所述模塑料、所述TAV和所述集成电路管芯上方形成第二RDL。
2.根据权利要求1所述的方法，进一步包括去除所述载体。
3.根据权利要求1所述的方法，其中，将所述集成电路管芯连接在所述第一RDL上方包括：使用管芯粘附膜(DAF)或粘合剂将所述集成电路管芯附接至所述第一RDL。
4.根据权利要求1所述的方法，进一步包括将多个导电凸块连接至所述第二RDL。
5.根据权利要求1所述的方法，其中，将所述集成电路管芯连接在所述第一RDL上方包括：连接包括设置在集成电路管芯表面上的绝缘材料内的多个接触件的集成电路管芯，并且形成所述第二RDL包括：将所述第二RDL的部分连接至所述集成电路管芯的表面上的所述多个接触件。
6.根据权利要求1所述的方法，其中，形成所述多个TAV包括在部分所述第一RDL上方镀所述多个TAV。
7.一种封装半导体器件的方法，所述方法包括：
在载体上方形成第一绝缘材料；
图案化所述第一绝缘材料；
在图案化的第一绝缘材料上方形成第一导电材料；
图案化所述第一导电材料；
在图案化的第一导电材料和所述图案化的第一绝缘材料上方形成第二绝缘材料；
图案化所述第二绝缘材料以露出位于所述第二绝缘材料的边界区域中的部分所述第一导电材料；
在所述第二绝缘材料的所述边界区域中，在所述第一导电材料的露出部分上方形成多个装配通孔(TAV)；
将集成电路管芯连接在所述第二绝缘材料的中心区域中的所述第二绝缘材料上方；
在所述多个TAV和所述集成电路管芯之间的所述第二绝缘材料上方形成模塑料；
在所述多个TAV、所述集成电路管芯和所述第二绝缘材料上方形成第三绝缘材料；
图案化所述第三绝缘材料；
在图案化的第三绝缘材料上方形成第二导电材料；
图案化所述第二导电材料；
在图案化的第二导电材料和所述图案化的第三绝缘材料上方形成第四绝缘材料；
图案化所述第四绝缘材料以露出部分所述第二导电材料；
在所述第二导电材料的露出部分上方形成多个导电凸块；以及
去除所述载体。
8.一种封装半导体器件，包括：
第一再分布层(RDL)；
集成电路管芯，设置在所述第一RDL的中心区域上方；
管芯粘附膜(DAF)或粘合剂，设置在所述第一RDL和所述集成电路管芯之间；
第二RDL，设置在所述集成电路管芯上方并与所述集成电路管芯电连接；
模塑料，设置在所述第一RDL和所述第二RDL之间；以及
多个装配通孔(TAV)，设置在所述第一RDL的边界区域中的所述模塑料中。
9.根据权利要求8所述的封装半导体器件，进一步包括连接至所述第二RDL的多个导电凸块。
10.一种叠层封装(PoP)器件，包括根据权利要求9所述的封装半导体器件。
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