TWI591736B - 積體電路封裝接墊及其形成方法 - Google Patents

積體電路封裝接墊及其形成方法 Download PDF

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TWI591736B
TWI591736B TW104139360A TW104139360A TWI591736B TW I591736 B TWI591736 B TW I591736B TW 104139360 A TW104139360 A TW 104139360A TW 104139360 A TW104139360 A TW 104139360A TW I591736 B TWI591736 B TW I591736B
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Taiwan
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layer
forming
integrated circuit
dielectric layer
circuit die
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TW104139360A
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TW201622018A (zh
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陳憲偉
余振華
吳集錫
葉德強
蘇安治
陳威宇
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台灣積體電路製造股份有限公司
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Description

積體電路封裝接墊及其形成方法
本揭露係關於積體電路封裝及其形成方法。
半導體裝置係用於各種電子應用，例如個人電腦、手機、數位相機、以及其他電子設備。通常藉由在半導體基板上方連續沉積絕緣或介電層、傳導層與半導體材料層，以及使用微影蝕刻而圖案化不同材料層，以形成電路組件與元件於其上，而製造半導體裝置。通常在單一半導體晶圓上製造數十或數百個積體電路。沿著切割線切割積體電路而單粒化個別晶粒。而後，將個別晶粒分別封裝於多晶片模組中或是其他形式的封裝。
由於各種電子組件(例如，電晶體、二極體、電阻器、電容器等)積體密度之持續改良，使得半導體產業快速成長。在大多數情況下，積體密度的改良係來自於反覆縮小最小特徵尺寸(例如，將半導體製程節點縮小至次20奈米節點)，使得在給定的面積上整合更多組件。隨著微小化的需求，近來已發展更高速、更大帶寬、較低功率消耗與延遲，因此半導體晶粒需要更小且更具有創造性的封裝技術。
隨著半導體技術的進展，堆疊的半導體裝置，例如三維積體電路(3DIC)已成為有效的選擇用於進一步縮小半導體裝置的實 體尺寸。在堆疊的半導體裝置中，在不同的半導體晶圓上，製造主動電路，例如邏輯、記憶體、處理器電路、以及類似物。二或多個半導體晶圓可設置或堆疊在彼此的頂部，進一步縮小半導體裝置的外形。封裝上封裝(POP)裝置係一種3DIC形式，其中封裝晶粒而後與另一封裝晶粒封裝在一起。
本揭露的一些實施例係提供一種製造半導體裝置的方法，該方法包括在載體基板上方形成第一層；在該第一層上形成貫穿通路；在該第一層上方放置積體電路晶粒；在該第一層上方形成模塑料化合物，該模塑料化合物沿著該積體電路晶粒與該貫穿通路的側壁延伸；移除該載體基板，暴露該第一層；以及完全移除該第一層，因而暴露該貫穿通路。
本揭露的一些實施例係提供一種製造半導體裝置的方法，該方法包括在載體基板上方形成第一層，該第一層具有開口；在該第一層上形成貫穿通路，該貫穿通路具有延伸至該開口中的貫穿通路突出部；在該第一層上方放置積體電路晶粒；在該第一層上方形成模塑料化合物，該模塑料化合物沿著該積體電路晶粒與該貫穿通路的側壁延伸；在該積體電路晶粒與該貫穿通路上方形成重佈層；移除該載體基板，暴露該第一層；以及凹陷該第一層，因而該貫穿通路自該第一層突出。
本揭露的一些實施例係提供一種半導體裝置，其包括積體電路晶粒，其具有正面與背面；模塑料化合物，其係與該積體電路晶粒的側壁相鄰；以及第一層，其係延伸於該模塑料化合物上方，貫穿通路具有延伸穿過該第一層的貫穿通路突出部。
100‧‧‧載體基板
102‧‧‧脫膜層
104‧‧‧背面介電層
206‧‧‧貫穿通路
310‧‧‧積體電路晶粒
312‧‧‧黏著劑
314‧‧‧晶粒接點
416‧‧‧封裝物
518‧‧‧正面重佈結構
520、520a、520b、520c‧‧‧介電層
520a‧‧‧第一介電層
520b‧‧‧第二介電層
520c‧‧‧第三介電層
522a‧‧‧第一金屬化圖案
522b‧‧‧第二金屬化圖案
524‧‧‧鈍化層
526‧‧‧凸塊下金屬
528‧‧‧連接物
830‧‧‧背面連接物
932‧‧‧第一基板
934‧‧‧第二基板
936‧‧‧成形底膠填充
1340‧‧‧開口
1442‧‧‧貫穿通路突出部
3160‧‧‧背面重佈結構
3162‧‧‧第一背面金屬化層
3164‧‧‧第一背面介電層
3166‧‧‧第二背面介電層
2450‧‧‧犧牲背面介電層
3970‧‧‧導線
為協助讀者達到最佳理解效果，建議在閱讀本揭露時同時參 考附件圖示及其詳細文字敘述說明。請注意為遵循業界標準作法，本專利說明書中的圖式不一定按照正確的比例繪製。在某些圖式中，尺寸可能刻意放大或縮小，以協助讀者清楚了解其中的討論內容。
圖1至9係根據一些實施例說明形成半導體裝置的各種中間步驟之剖面圖。
圖10至12係根據一些實施例說明形成半導體裝置的各種中間步驟之剖面圖。
圖13至20係根據一些實施例說明形成半導體裝置的各種中間步驟之剖面圖。
圖21至23係根據一些實施例說明形成半導體裝置的各種中間步驟之剖面圖。
圖24至31係根據一些實施例說明形成半導體裝置的各種中間步驟之剖面圖。
圖24至31係根據一些實施例說明形成半導體裝置的各種中間步驟之剖面圖。
圖32至40係根據一些實施例說明形成半導體裝置的各種中間步驟之剖面圖。
本揭露提供了數個不同的實施方法或實施例，可用於實現本發明的不同特徵。為簡化說明起見，本揭露也同時描述了特定零組件與佈置的範例。請注意提供這些特定範例的目的僅在於示範，而非予以任何限制。舉例而言，在以下說明第一特徵如何在第二特徵上或上方的敘述中，可能會包括某些實施例，其中第一特徵與第二特徵為直接接觸，而敘述中也可能包括其他不同實施例，其中第一特徵與第二特徵中間另有其他特徵，以致於第一特徵與第二特徵並不直接接觸。此外，本揭露中的各種範例可能使用重複的參考數字和/或文 字註記，以使文件更加簡單化和明確，這些重複的參考數字與註記不代表不同的實施例與配置之間的關聯性。
另外，本揭露在使用與空間相關的敘述詞彙，如“在...之下”，“低”，“下”，“上方”，“之上”，“下”，“頂”，“底”和類似詞彙時，為便於敘述，其用法均在於描述圖示中一個元件或特徵與另一個(或多個)元件或特徵的相對關係。除了圖示中所顯示的角度方向外，這些空間相對詞彙也用來描述該裝置在使用中以及操作時的可能角度和方向。該裝置的角度方向可能不同(旋轉90度或其它方位)，而在本揭露所使用的這些空間相關敘述可以同樣方式加以解釋。
本揭露的實施例係關於特定內容，稱為三維(3D)積體扇出(InFO)封裝上封裝(package-on-package，PoP)裝置。然而，其他實施例亦可應用於其他電連接組件，包含但不限於封裝上封裝組合、晶粒與晶粒組合、晶圓與晶圓組合、晶粒與基板組合、組合封裝、處理基板、插入物、基板、或類似物、裝配輸入組件、板、晶粒、或其他組件、或用於連接封裝或是裝配任何形式的積體電路或電阻組件的組合。
圖1至9係根據一些實施例說明形成半導體封裝的中間步驟之剖面圖。參閱圖1，其係說明載體基板100具有脫膜層102與形成於其上的背面介電層104。通常，載體基板100在後續製程步驟過程中提供暫時的機械與結構支撐。載體基板100可包含任何合適的材料，例如矽基底材料，例如矽晶圓、玻璃或氧化矽、或其他材料，例如氧化鋁、陶瓷材料、這些材料的任何組合、或類似物。在一些實施例中，載體基板100是平面的，以便於進一步處理。
脫膜層102係形成於載體基板100上方之任選層，使得更容易移除載體基板100。進一步詳細說明如下，在載體基板100上方 放置各種層與裝置，而後可移除載體基板100。任選的脫膜層102輔助載體基板100的移除，降低對於載體基板100上方所形成的結構之破壞。脫膜層102可由聚合物為基底的材料所形成。在一些實施例中，脫膜層102係環氧化合物為基底的熱釋放材料，例如光熱轉換(LTHC)釋放塗覆，當受熱時，該熱釋放材料會失去其黏性。在一些實施例中，脫膜層102可為紫外線(UV)膠，當其暴露至UV光時，會失去其黏性。脫膜層102可為液體並且被硬化。在其他實施例中，脫膜層102可為壓層於載體基板100上的壓層膜。可使用其他脫膜層。
背面介電層104可為聚合物(例如聚苯并噁唑(polybenzoxazole，PBO)、聚亞醯胺、苯并環丁烯(benzocyclobutene，BCB)、或類似物)、氮化物(例如氮化矽或類似物)、氧化物(例如氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻雜的磷矽酸鹽玻璃(BPSG)、或其組合、或類似物)、或類似物，並且可由旋塗、壓層、化學氣相沉積(CVD)、或類似方法而形成。在一些實施例中，背面介電層104的厚度係約1微米至約10微米，例如約7微米。
參閱圖2，其係根據一些實施例說明貫穿通路206的形成。貫穿通路206從封裝的一側提供電連接至封裝的另一側。例如，如以下之更詳細說明，將晶粒安置於背面介電層104，以及在貫穿通路與晶粒附近形成模塑料化合物。接著，另一裝置，例如另一晶粒、封裝、基板、或類似物，可附接至晶粒與模塑料化合物。貫穿通路206係在另一裝置與封裝的背面之間提供電連接，而不需要經由配置在背面介電層104的晶粒傳送電子信號。
例如，可藉由在背面介電層104上方形成傳導晶種層(未繪示)，形成貫穿通路206。在一些實施例中，晶種層係金屬層，其可為單層或是包含由不同材料所形成之複數個子層的複合層。晶種 層可由銅、鈦、鎳、金、或其組合、或類似物而製成。在一些實施例中，晶種層係包括鈦層與位於鈦層上方的銅層。例如，可使用物理氣相沉積(PVD)、CVD、原子層沉積(ALD)、其組合、或類似物而形成晶種層。晶種層可包括一或多層。
可沉積且圖案化遮罩，例如圖案化的光阻層，以定義貫穿通路206的形狀，其中遮罩中的開口係暴露晶種層。例如，可使用無電鍍製程或是電化學鍍製程，以傳導材料填充該開口。鍍製程可為單向填充圖案化光阻中的開口(例如從晶種層向上)。單向填充可更均勻填充開口，特別是對於高深寬比的貫穿通路。或者，可在圖案化光阻中的開口之側壁上形成晶種層，並且可多重方向填充該些開口。接著，可於灰化與/或溼式剝除製程中移除光阻，並且可蝕刻晶種層之過多材料，留下貫穿通路206於背面介電層104上方，如圖2所示。藉由打線接合製程，例如銅線接合製程，貫穿通路206亦可具有金屬線柱。使用打線接合製程可免除沉積晶種層、沉積與圖案化光阻、以及電鍍以形成貫穿通路的需求。
圖3係根據一些實施例說明將積體電路晶粒310附接至背面介電層104。在一些實施例中，積體電路晶粒310可藉由黏著劑312，例如晶粒附接膜(DAF)而附著至背面介電層104。黏著劑312的厚度範圍可從約10微米至約30微米。積體電路晶粒310可為單晶粒，如圖3所示，或是在一些實施例中，可附接二或更多晶粒，其可包含適合特定方式的任何晶粒。例如，積體電路晶粒310可包含靜態隨機存取記憶體(SRAM)晶片或是動態隨機存取記憶體(DRAM)晶片、處理器、記憶體晶片、邏輯晶片、類比晶片、數位晶片、中央處理單元(CPU)、圖形處理單元(GPU)、或其組合、或類似物。積體電路晶粒310可附接至合適的位置作為特定設計或應用。例如，圖3係說明積體電路晶粒310配置在中心區域的實施例，其中貫穿通路206係位於周圍 附近。在一些實施例中，積體電路晶粒310可自中心偏移。在附接至背面介電層104之前，根據可應用的製程而處理積體電路晶粒310，以於積體電路晶粒310中形成積體電路。
在一些實施例中，積體電路晶粒310係配置於背面介電層104，因而晶粒接點314係面離背面介電層104或是在背面介電層104的遠端。晶粒接點314提供電連接至積體電路晶粒310上所形成的電路。晶粒接點314可形成於積體電路晶粒310的主動側或是可形成於背面，並且包括貫穿通路。晶粒接點314可進一步包括貫穿通路，其係在積體電路晶粒310的第一側與第二側之間提供電連接。在一實施例中，晶粒接點314的傳導材料係銅、鎢、鋁、銀、金、錫、其組合、或類似物。
圖4係根據一些實施例說明以封裝物416封裝積體電路晶粒310與貫穿通路206。在一些實施例中，封裝製程係晶圓級成形製程。例如，施加封裝物416，以填充積體電路晶粒310與貫穿通路206之間的間隙。封裝物416可包含任何合適的材料，例如模塑料化合物、環氧樹脂、聚合物、底膠填充、或類似物。形成封裝物416的合適方法可包含壓縮成形、轉移成形、液體封裝物成形、或類似方法。例如，封裝物416可為液體形式位於積體電路晶粒310與貫穿通路206之間。接著，進行硬化製程以固化封裝物416。
在一些實施例中，形成封裝物416以覆蓋貫穿通路206與/或晶粒接點314。在這些實施例中，可使用機械研磨、化學機械拋光(CMP)、或其他回蝕技術，以移除封裝物416之過多部分並且暴露積體電路晶粒310的晶粒接點314。在平面化之後，封裝物416、積體電路晶粒310、以及貫穿通路206的頂表面係實質齊平。
圖5係根據一些實施例說明正面重佈結構518的形成。通常，正面重佈結構518包括一或多個重佈層(RDL)並且提供欲形成 的傳導圖案使得完成的封裝有引腳輸出(pin-out)接點圖案，這不同於貫穿通路206與晶粒接點314的圖案，對於置放貫穿通路206與積體電路晶粒310有更大的彈性。RDL可用於提供外部電連接至積體電路晶粒310與/或至貫穿通路206。RDL可進一步用於將積體電路晶粒310電耦合至貫穿通路206，其可電耦合至一或多個其他封裝、封裝基板、組件、類似物、或其組合。在正面重佈結構518中的金屬化層之所述數目係僅作為說明之目的並非用於限制本揭露的內容。正面重佈結構518可包括任何數目的介電層、金屬化圖案、以及通路。例如，圖5係說明重佈結構518包含三個介電層520a、520b與520c，統稱為正面介電層520，具有個別的金屬化圖案與通路，如下所述，然而其他實施例可具有較少或較多的介電層。
第一介電層520a係形成於封裝物416與積體電路晶粒310上。在一些實施例中，第一介電層520a係由聚合物所組成，其可為光敏感材料，例如聚苯并噁唑(PBO)、聚亞醯胺、苯并環丁烯(BCB)、或類似物，可使用微影蝕刻將其圖案化。在其他實施例中，第一介電層520a係由例如氮化矽的氮化物、例如氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻雜的磷矽酸鹽玻璃(BPSG)、或類似物而形成。可藉由旋塗、壓層、CVD、類似方法、或其組成而形成第一介電層520a。而後，將第一介電層520a圖案化以形成開口，暴露晶粒接點314與貫穿通路206的部分。在第一介電層520a係由光敏感材料所形成的實施例中，圖案化的進行可根據所欲之圖案而暴露第一介電層520a並且顯影以移除不想要的材料，因而暴露部分的晶粒接點314與貫穿通路206。亦可使用其他方法，例如使用圖案化的遮罩與蝕刻，以圖案化第一介電材料520a。
第一金屬化圖案522a係形成於第一介電層520a上，並且接觸暴露的晶粒接點314與貫穿通路206。在形成第一金屬化圖案 522a的範例中，晶種層(未繪示)係形成於第一介電層522a上方與第一介電層522a中所形成的開口中。在一些實施例中，晶種層係金屬層，其可為單層或是包含由不同材料所形成之複數個子層的複合層。在一些實施例中，晶種層系包括鈦層以及形成於鈦層上方的銅層。例如，可使用PVD或類似方法，形成晶種層。而後，根據所欲之重佈圖案，形成且圖案化遮罩於晶種層上。在一些實施例中，遮罩係藉由旋塗或類似方法並且曝光進行圖案化而形成的光阻。遮罩的圖案係對應於第一金屬化圖案522a。圖案化形成穿過遮罩的開口，以暴露晶種層。在遮罩的開口中與晶種層的暴露部分上，形成傳導材料。可藉由電鍍，例如電鍍或是無電鍍、或類似方法，形成傳導材料。傳導材料可包括金屬，例如銅、鈦、鎢、鋁、或類似物。而後，移除光阻以及未有傳導材料形成於其上的部分晶種層。藉由可接受的灰化或是剝除製程，例如使用氧氣電漿或是類似方法，移除光阻。一旦移除光阻，例如使用可接受的蝕刻製程，例如濕式或乾式蝕刻，移除晶種層的暴露部分。晶種層與傳導材料的剩餘部分係形成第一金屬化圖案522a。在第一介電層520a上方形成第二介電層520b，為後續的層形成更多平坦表面，並且可使用與形成第一介電層520a類似的材料與製程而形成第二介電層520b。在一些實施例中，第二介電層520b係由聚合物、氮化物、氧化物、或類似物所形成。在一些實施例中，藉由旋塗製程，形成PBO作為第二介電層520b。
第三介電層520c與第二金屬化圖案522b係形成於第二介電層520b與第一金屬化圖案522a上。可使用與上述形成第一介電層520a與第一金屬化圖案522a類似的材料與類似的製程，形成第三介電層520c與第二金屬化圖案522b。正面介電層520中的開口形成通路，其互連相鄰的金屬化層，例如互連第一金屬化圖案522a與貫穿通路206/晶粒接點314，以及互連第一金屬化圖案522a與第二金屬化圖案522b。
圖5係根據一些實施例說明在最上方的金屬化圖案上方形成鈍化層524。鈍化層524可由聚合物形成，其可為光敏感材料，例如PBO、聚亞醯胺、BCB、或類似物，可使用微影蝕刻遮罩將其圖案化。在其他實施例中，鈍化層524係由氮化物或氧化物所形成，例如氮化矽、氧化矽、PSG、BSG、BPSG、或類似物。可藉由旋塗、壓層、CVD、類似方法、或其組合，而形成鈍化層524。而後，將鈍化層524圖案化以暴露下方的金屬化層，例如第二金屬化圖案522b。圖案化係可接受的製程，例如當介電層為光敏感材料時，將鈍化層524暴露於光下，或是使用蝕刻，例如非等向性蝕刻。單一鈍化層524僅為說明，在其他實施例中，可使用複數個鈍化層。
圖5亦說明凸塊下金屬(UBM)526形成且圖案化在鈍化層524上方且穿過鈍化層524，因而形成電連接最上方的金屬化層，例如圖5所示之實施例的第二金屬化圖案522b。凸塊下金屬526對於上方所放置的電連接物，例如焊球/凸塊、傳導柱、或類似物，提供電連接。在一實施例中，凸塊下金屬526係包含擴散阻障層、晶種層、或其組合，擴散阻障層可包含Ti、TiN、Ta、TaN、或其組合。晶種層可包含銅或銅合金。然而，亦可包含其他金屬，例如鎳、鈀、銀、金、鋁、其組合、以及其多層。在一實施例中，使用濺鍍形成凸塊下金屬526。在其他實施例中，可使用電鍍。
根據一些實施例，在凸塊下金屬526上方形成連接物528。連接物528可為焊球、金屬柱、受控的塌陷晶片連接(C4)凸塊、微凸塊、化學鍍鎳鈀浸金(electroless nickel-electroless palladium-immersion gold technique，ENEPIG)形成的凸塊、其組合(例如，附接焊球的金屬柱)、或類似物。連接物528可包含傳導材料，例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似物、或其組合。在一些實施例中，連接物528係包括共晶材料，並且可包括焊料凸塊或焊球。例如，焊料可為鉛為基底與無鉛銲料，例如Pb-Sn組成物的鉛為基底焊 料；無鉛銲料包含InSb、錫、銀與銅(SAC)組成物；以及具有共同熔點並且在電性應用中形成傳導焊料連接的其他共晶材料。關於無鉛焊料，可使用不同組成的SAC焊料，例如SAC 105(Sn 98.5%,Ag 1.0%,Cu 0.5%)、SAC 305以及SAC 405。亦可自SnCu化合物形成無鉛連接物，例如焊球，而不使用銀(Ag)。或者，無鉛焊料連接物可包含錫與銀，Sn-Ag，而不使用銅。連接物528可形成柵格，例如球柵陣列(GBA)。在一些實施例中，可進行回焊製程，形成具有部分球形的連接物528。或者，連接物528可包括其他形狀。例如，連接物528亦可包括非球型傳導連接物。
在一些實施例中，連接物528包括由濺鍍、印刷、電鍍、無電鍍、CVD、或類似方法所形成的金屬柱(例如銅柱)，其上有焊料或是沒有焊料。金屬柱可為無焊料，並且具有實質垂直側壁或是錐形側壁。
為了說明，簡化正面重佈結構518。例如，為了說明，僅說明從貫穿通路206延伸的傳導線，然而，可使用正面重佈結構518提供外部電連接至貫穿通路206與晶粒接點314之任一者，以及將個別的貫穿通路206耦合至個別的晶粒接點314。
圖6係根據一些實施例說明移除載體基板100與脫膜層102(參閱圖5)，以暴露背面介電層104。在一些實施例中，脫層包含投射光在脫膜層102上，該光係例如雷射光或UV光，因而脫膜層102在光熱之下分解，並且可移除載體基板100。在另一實施例中，可使用熱製程、化學剝除製程、雷射移除、UV處理、類似方法、或其組合。
在分離載體基板100之後，可使用清理製程移除脫膜層102的殘留物。在使用LTHC膜作為脫膜層102的實施例中，可使用電漿清理製程移除LTHC殘留物。例如，在一些實施例中，電漿清理製程使用Ar、N2、CF4、O2、或類似物作為製程氣體。在載體基板100與脫膜 層102脫層之後，背面介電層104被暴露。
在一些實施例中，可具有其他支撐物。在這些情況下，在移除載體基板100之前，第二載體基板(未繪示)可附接至鈍化層524與/或連接物528。例如，可使用黏著劑，例如UV黏著劑，用於附接第二載體基板。
圖7係根據一些實施例說明移除背面介電層104。通常，若對於貫穿通路206與/或積體電路晶粒310形成電接觸(例如積體電路晶粒位向倒反，或是積體電路晶粒包含貫穿通路)，則移除至少部分的背面介電層104。已發現雷射鑽孔開口穿過背面介電層104可能破壞貫穿通路並且具有許多額外的製程步驟。根據本揭露的一些實施例，雷射鑽孔製程不需要暴露貫穿通路206，因而減少且/或防止不必要的破壞。
在一些實施例中，使用乾式蝕刻製程，其使用例如Ar、N2、CF4、O2、或類似物，移除背面介電層104。
圖8係根據一些實施例說明背面連接物830的形成。在移除背面介電層104之後，可直接在貫穿通路206上形成背面接物830。可使用與正面連接物528類似的製程與材料，形成背面連接物830。
圖9係根據一些實施例說明圖8所示之結構附接至第一基板932與第二基板934。第一基板932與第二基板934各自可為任何基板，例如積體電路晶粒、封裝、印刷電路板、插入物、或類似物。例如，圖9係說明第一基板932包括印刷電路板或插入物，以及第二基板934包括另一封裝。
圖9係根據一些實施例說明第一基板934與成形封裝物416之間插入的成形底膠填充936。在一些實施例中，例如，成形底膠填充係聚合物、環氧化合物、以及/或類似物。成形底膠填充保護背面連接物830免於外部環境影響並且可提供額外的支撐。在一些實施例中，成形底膠填充936可沿著第二基板934的側壁延伸，如圖9所示。在一些實施例中，成形底膠填充936可不沿著第二基板934的側壁延伸。雖未繪示，然而，成形底膠填充亦可形成於第一基板932與鈍化層524之間，環繞正面連接物。
本揭露所提供的圖示為了說明已做簡化，可進行其他製程。 例如，圖式所示的結構可代表較大的類晶圓結構之單一3DIC封裝區域。在一些實施例中，載體基板100可為晶圓，以及積體電路晶粒可為晶圓上所形成的許多晶粒區之一。第二基板934可為附接至個別晶粒的多個基板之一，以及成形底膠填充936可形成於晶粒區上方。而後，可進行單粒化製程，用以將晶粒區分為個別的3DIC結構，如圖9所示。
圖10至12係根據一些其他的實施例說明形成半導體封裝的中間步驟之剖面圖。可使用與上述圖1至9之類似製程與材料，形成圖10至12所示之許多結構，其中相同的元件符號係指相同元件，因此，不再重複該等元件的說明。圖10至12所述之實施例係假設已進行圖1至6所述之製程。據此，本揭露的方法係包含圖1至6所示的製程接著圖10至12所示之製程。
參閱圖10，根據一些實施例，移除背面介電層104(參閱圖6)，並使封裝物416凹陷。如上述說明與圖7所示，移除背面介電層104，因而封裝物416未凹陷。圖10係說明封裝物416凹陷，因而造成貫穿通路206突出穿過或延伸於封裝物416的表面，因而暴露貫穿通路206的部分側壁。
在一些實施例中，移除背面介電層104，以及使用例如過度蝕刻製程，使得封裝物416產生凹陷。例如，在一些實施例中，使用與圖7所述之類似方式，但以較長蝕刻時間移除背面介電層104。蝕刻製程係選擇性的，貫穿通路206發生很少或無蝕刻，而較長的蝕刻時間使得蝕刻製程持續蝕刻並使得封裝物416產生凹陷。
在一些實施例中，封裝物416凹陷深度D1係等於或大於2微米。藉由使得封裝物416凹陷並且暴露貫穿通路206的側壁一距離(例如此處所述)，而後形成於貫穿通路206上方的背面連接物(例如焊料)可沿著貫穿通路206的側壁延伸，增加接觸表面積。在一些實施例中，在焊料與貫穿通路206之間的此增加之接觸表面可增加可信賴度。
參閱圖11，其係根據一些實施例說明背面連接物830的形成。可使用形成如圖5所示之正面連接物528的類似製程與材料，形成背面連接物。
圖12係根據一些實施例說明圖11的結構附接至第一基板932與第二基板934。第一基板932與第二基板934各自可為任何基板，例如積體電路晶粒、封裝、印刷電路板、插入物、或類似物。例如，圖12係說明第一基板932包括印刷電路板或插入物，以及第二基板934包括另一封裝。
圖12係根據一些實施例說明在第二基板934與成形封裝物416之間所插入的成形底膠填充936。例如，在一些實施例中，成形底膠填充936係聚合物、環氧化合物、以及/或類似物。成形底膠填充936保護背面連接物830免於外部環境影響並且可提供額外的支撐。在一些實施例中，成形底膠填充936可沿著第二基板934的側壁延伸，如圖12所示。在一些實施例中，成形底膠填充936可不沿著第二基板934的側壁延伸。雖未繪示，然而，成形底膠填充亦可形成於第一基板932與鈍化層524之間，環繞正面連接物。
藉由過度蝕刻而凹陷封裝物416亦可粗糙化封裝物416的表面。封裝物416的粗糙表面可增加封裝物與成形底膠填充936之間的接合，因而減少或防止脫層問題。
圖13至20係根據一些其他實施例說明形成半導體封裝的中間步驟之剖面圖。可使用形成圖1至12所述之類似製程與材料而形成圖13至20的許多結構，其中相同的元件符號係指相同元件，據此，不再重複說明該等元件。
參閱圖13，其係說明載體基板100，其具有脫膜層102與形成於其上的背面介電層104。可使用圖1所述之類似製程，以類似材料形成載體基板100、脫膜層102以及背面介電層104。如圖13所示，圖案化背面介電層104以於其中形成開口。上述圖1至2的實施例係使用具有相對平坦表面的貫穿通路，更詳細說明如下，開口1340用於形成具有一或多個突出部的貫穿通路，該突出部係從貫穿通路的一端延伸。
在背面介電層104係由例如PBO的光敏感材料所形成的實施例中，背面介電層104的圖案化可根據所欲之突出部的圖案而暴露背面介電層104，並且將背面介電層104顯影以移除對應於突出部之位置的背面介電層104 的部分。在一些實施例中，背面介電層104的厚度係約1微米制約10微米，例如約7微米。如以下更詳細之說明，接著在背面介電層104的上方形成貫穿通路，其中開口1340係對應於貫穿通路突出部。約7微米的厚度係提供足夠厚度將貫穿通路突出部塑形(例如錐形側壁)，並且提供足夠的製程窗用於過度蝕刻製程，以暴露貫穿通路突出部的側壁之部分。
圖14至18係說明後續製程，分別類似於圖2至6所述。如圖14所示，貫穿通路206係包含貫穿通路突出部1442，其對應於圖13所示之開口1340。可使用與上述類似的製程與材料形成貫穿通路206與貫穿通路突出部1442。例如，於背面介電層104上方並且沿著開口1340的側壁與底部，可形成晶種層(未繪示)。可在晶種層上方形成圖案化的遮罩(未繪示)，其中圖案化的遮罩具有開口對應於貫穿通路206的位置。在開口中形成傳導材料，移除圖案化遮罩，並且移除晶種層的過多材料，形成具有貫穿通路突出部1442的貫穿通路206，如圖14所示。
圖18係說明進行圖2至6的上述製程之後的結構，包含移除載體基板100與脫膜層102。在一些實施例中，背面介電層104留著，因而背面介電層104的表面係相對與貫穿通路突出部1442齊平，允許在相同脫膜層102上形成貫穿通路206與背面介電層104的製程變化。
此後，如圖19與20所示，可分別進行與圖8與9所述之類似的製程，以形成背面結構830，附接結構至其他基板(例如，第一基板932與/或第二基板934)，以及形成成形底膠填充936。如圖20所示，在一些實施例中，背面連接物830直接連接至貫穿通路突出部1442。在一些實施例中，可在第二基板934上提供背面連接物830，而後附接至貫穿通路突出部1442。
圖21至23係根據一些實施例說明形成半導體封裝的中間步驟之剖面圖。圖21至23係假設已進行圖13至19的上述製程，其中相同的元件符號係指相同的元件。參閱圖21，其係說明圖18進行凹陷製程以使背面介電層104凹陷以暴露貫穿通路突出部1442之至少部分的側壁之後的結構。例如，可使用Ar、N2、CF4、O2、或類似物之乾式蝕刻製程，進行凹陷製程。凹陷製程可造 成暴露貫穿通路突出部1442的側壁，增加後續所形成之背面連接物830的濕潤表面。在一些實施例中，將背面介電層104凹陷，因而貫穿通路突出部1442突出距離D1，其係大於約2微米。
藉由凹陷背面介電層104以及暴露貫穿通路突出部1442的側壁距離D1，在貫穿通路突出部1442上方後續形成的背面連接物830(例如焊料)可沿著貫穿通路突出部1442的側壁與/或貫穿通路206延伸，因而增加接觸表面積。在一些實施例中，在焊料與貫穿通路突出部1442與/或貫穿通路206之間的此增加的接觸表面積可增加可信賴度。
此後，如圖22與23所示，可進行與圖19及20所述之類似的製程，以形成背面連接物830，附接結構至其他基板(例如，第一基板932與/或第二基板934)，以及形成成形底膠填充936。在一些實施例中，成形底膠填充936可不沿著第二基板934的側壁延伸。如圖22所示，在一些實施例中，背面連接物830係直接在貫穿通路突出部1442上。雖未繪示，亦可在第一基板932與鈍化層524之間形成成形底膠填充，環繞正面連接物。
圖24至29係根據一些實施例說明形成半導體封裝的中間步驟之剖面圖。如以下詳述說明，犧牲層用於輔助形成貫穿通路的製程，該貫穿通路具有一或多個貫穿通路突出部，其類似於圖21至23所示之結構。參閱圖24，類似的製程與類似的材料係用於形成類似於圖13所示之結構，具有額外的特徵為犧牲背面介電層2450，其係在形成背面介電層104之前形成於脫膜層102上方，其中相同的元件符號係指相同的元件。
在一些實施例中，犧性背面介電層2450可為聚合物(例如聚苯并噁唑(PBO)、聚亞醯胺、苯并環丁烯(BCB)、或類似物)、氮化物(例如氮化矽或類似物)、氧化物(例如氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻雜磷矽酸鹽玻璃(BPSG)、或其組合、或類似物)、或類似物，並且可藉由旋塗、壓層、化學氣相沉積(CVD)、或類似物而形成。在一些實施例中，犧牲背面介電層2450係光阻材料(例如PBO)，其已塗覆在表面上並且顯影。在一些實施例中，犧牲層 2450的厚度約為2微米。
此後，在犧牲背面介電層2450上方形成且圖案化背面介電層104。在一些實施例中，背面介電層104係光阻材料(例如PBO)，其已經塗覆、曝光並且顯影，以形成開口1340，如圖24所示。由於犧牲背面介電層2450已經硬化，因而在圖案化背面介電層104的過程中仍保留犧牲背面介電層2450。在一些實施例中，背面介電層104的厚度約為1微米至約10微米，例如約7微米。進一步詳細說明如下，接著在背面介電層104上方形成貫穿通路，其中開口1340係對應於貫穿通路突出部。約7微米的厚度提供足夠厚度以塑形貫穿通路突出部(例如錐形側壁)，以及提供足夠的製程窗用於過度蝕刻製程，以暴露貫穿通路突出部的部分側壁。
圖25至28係說明分別與上述圖14至17類似的製程，其中相同元件符號係指相同元件，差別在於有犧牲背面介電層2450存在。在移除載體基板100與脫膜層102之後，可移除犧牲背面介電層2450，如圖29所示。在一些實施例中，犧牲背面介電層2450係由與背面介電層104相同材料所形成，並且以與圖21所述之背面介電層104類似的方式移除犧牲背面介電層2450。例如，使用乾式蝕刻進行犧牲背面介電層2450的移除，該乾式蝕刻係使用例如Ar、N2、CF4、O2、或類似物。可控制移除製程為過度蝕刻，因而背面介電層104係凹陷至低於貫穿通路突出部1442的表面，以致暴露貫穿通路突出部1442的部分側壁。在一些實施例中，將背面介電層104凹陷，因而貫穿通路突出部1442突出距離D2，其等於或大於約2微米。在一些實施例中，貫穿通路突出部1442的錐形側壁從貫穿通路206之垂直側壁內縮一寬度。藉由凹陷背面介電層104且將貫穿通路突出部1442的側壁暴露距離D2，接著在貫穿通路突出部1442上方形成的背面連接物830(例如焊料)可沿著貫穿通路突出部1442與/或貫穿通路206的側壁延伸，因而增加接觸表面積。在一些實施例中，在焊料與貫穿通路突出部1442與/或貫穿通路206之間的此增加的接觸表面積可增加可信賴度。
此後，如圖30與31所示，可分別進行與圖19及20類似的製程，以形成背面連接物830、附接結構至其他基板(例如第一基板932與/或第二基板934)，以及形成成形底膠填充936。在一些實施例中，成形底膠填充936可不沿著第二基板934的側壁延伸。雖未繪示，然而亦可在第一基板932與鈍化層524之間形成成形底膠填充，環繞正面連接物。如圖31所示，在一些實施例中，背面連接物830直接位於貫穿通路突出部1442的側壁上且沿著貫穿通路突出部1442的側壁延伸。
圖32至40係根據一些實施例說明形成半導體封裝的中間步驟之剖面圖。如上所述，在移除載體基板100之後，暴露貫穿通路206。在一些實施例中，在形成貫穿通路206之前，在背面介電層104上方可形成背面重佈結構。據此，圖32至40所示之實施例係類似於上述之圖24至31具有背面重佈結構。
參閱圖32，其係說明類似於圖24所示之實施例，其中相同的元件符號係指相同元件。背面介電層104中的開口1340係對應於圖24中的貫穿通路突出部1442，圖32中的背面介電層104中的開口1340係對應於最外的背面重佈層。在一些實施例中，背面介電層104的厚度係約1微米至約10微米，例如約7微米。此厚度提供傳導層足夠的厚度以及製程窗，以於後續步驟中，部分暴露背面介電層104的側壁。
圖33係說明背面重佈結構3160，其包含第一背面金屬化層3162形成於第一背面介電層3164與第二背面介電層3166中。可使用與形成圖5之上述正面重佈結構518的類似製程與材料，形成背面重佈結構3160。
圖34至40係說明分別類似於圖25至31的製程，其中相同元件符號係指相同元件。在移除載體基板100與脫膜層102之後，可移除犧牲背面介電層2450。在一些實施例中，犧牲背面介電層2450係由與第一背面介電層3164類似的材料所形成，並且係以類似於圖29所述之背面介電層104的方法而移除。例如，可使用乾式蝕刻製程進行犧牲背面介電層2450的移除，該乾式蝕刻製程係使用例如Ar、N2、 CF4、O2、或類似物。可控制移除製程為過度蝕刻，因而第一背面介電層3164係凹陷至低於第一背面金屬化層3162的表面，以致暴露第一背面金屬化層3162的至少一部分側壁。
在一些實施例中，第一背面介電層3164凹陷的深度D3係等於或大於2微米。藉由凹陷第一背面介電層3164與暴露第一背面金屬化層3162的側壁距離D3，接著在第一背面金屬化層3162上方所形成的背面連接物830(例如焊料)可沿著第一背面金屬化層3162的側壁延伸，因而增加接觸表面積。在一些實施例中，在焊料與第一背面金屬化層3162之間的此增加的接觸表面積可增加可信賴度。
此後，如圖39與40所示，可進行分別與圖30及31類似的製程，以形成背面連接物830，附接結構至其他基板(例如第一基板932與/或第二基板934)，以及形成成形底膠填充936。如圖40所示，在一些實施例中，背面連接物830係直接位於第一背面金屬化層3162上並且沿著第一背面金屬化層3162的側壁延伸。
圖39與40亦說明可暴露一或多個導線(trace)，例如導線3970。導線3970代表形成於第一背面金屬化層3162中的導線(例如進入紙面以及從紙面而出的導線)，並且可連接接一或多個該背面連接物。如圖40所示，以成形底膠填充936覆蓋導線3970的暴露部分，保護導線3970免於外部環境影響。在一些實施例中，成形底膠填充936可不沿著第二基板934的側壁延伸。雖未繪示，亦可在第一基板932與鈍化層524之間形成成形底膠填充，環繞正面連接物。
在一些實施例中，提供製造半導體裝置的方法。該方法包含於載體基板上方形成第一層，以及在第一層上形成貫穿通路。在第一層上方置放積體電路晶粒，以及在第一層上方形成模塑料化合物，因而模塑料化合物沿著積體電路晶粒與貫穿通路的側壁延伸。在移除載體基板之後，完全移除第一層。
在一些實施例中，提供製造半導體裝置的方法。該方 法包含在載體基板上方形成第一層，該第一層具有開口，以及在該地一層上形成貫穿通路，該貫穿通路延伸至開口中。積體電路晶粒係放置在第一層上，以及在該第一層上方形成模塑料化合物，模塑料化合物沿著積體電路晶粒與貫穿通路的側壁延伸。在積體電路晶粒與貫穿通路上方形成重佈層。在移除載體基板之後，暴露且凹陷第一層，使得貫穿通路自第一層突出。
在一些實施例中，提供半導體裝置。該半導體裝置包含積體電路晶粒，其具有正面與背面。模塑料化合物係與積體電路晶粒的側壁相鄰。第一層在模塑料化合物上方延伸，以及貫穿通路具有延伸穿過第一層的貫穿通路突出部。
前述內容概述一些實施方式的特徵，因而熟知此技藝之人士可更加理解本揭露之各方面。熟知此技藝之人士應理解可輕易使用本揭露作為基礎，用於設計或修飾其他製程與結構而實現與本申請案所述之實施例具有相同目的與/或達到相同優點。熟知此技藝之人士亦應理解此均等架構並不脫離本揭露揭示內容的精神與範圍，並且熟知此技藝之人士可進行各種變化、取代與替換，而不脫離本揭露之精神與範圍。
206‧‧‧貫穿通路
310‧‧‧積體電路晶粒
312‧‧‧黏著劑
314‧‧‧晶粒接點
416‧‧‧封裝物
518‧‧‧正面重佈結構
522a‧‧‧第一金屬化圖案
522b‧‧‧第二金屬化圖案
520a‧‧‧第一介電層
520b‧‧‧第二介電層
520c‧‧‧第三介電層
524‧‧‧鈍化層
526‧‧‧凸塊下金屬
528‧‧‧連接物
830‧‧‧背面連接物
932‧‧‧第一基板
934‧‧‧第二基板
936‧‧‧成形底膠填充

Claims (11)

  1. 一種製造半導體裝置的方法，該方法包括：在載體基板上方形成第一層；在該第一層上形成貫穿通路；在該第一層上方放置積體電路晶粒；在該第一層上方形成模塑料化合物，該模塑料化合物沿著該積體電路晶粒與該貫穿通路的側壁延伸；移除該載體基板，暴露該第一層；完全移除該第一層，因而暴露該貫穿通路；以及凹陷該模塑料化合物，因而該貫穿通路自該模塑料化合物的表面突出第一距離。
  2. 如申請專利範圍第1項所述之方法，其中該第一距離係等於或大於2微米。
  3. 如申請專利範圍第1項所述之方法，進一步包括在移除該載體基板之前，在該積體電路晶粒與該貫穿通路上方形成重佈層。
  4. 如申請專利範圍第1項所述之方法，進一步包括在形成該貫穿通路之前，在該第一層上方形成第二層。
  5. 如申請專利範圍第4項所述之方法，其中該貫穿通路係包括貫穿通路突出部，該貫穿通路突出部延伸穿過該第二層。
  6. 如申請專利範圍第5項所述之方法，進一步包括凹陷該第二層，因而該貫穿通路突出部自該第二層的表面突出。
  7. 如申請專利範圍第6項所述之方法，其中該貫穿通路突出部係自該第二層的該表面突出一距離，該距離係等於或大於2微米。
  8. 一種製造半導體裝置的方法，該方法包括：在載體基板上方形成第一層，該第一層具有開口； 在該第一層上形成貫穿通路，該貫穿通路具有延伸至該開口中的貫穿通路突出部；在該第一層上方放置積體電路晶粒；在該第一層上方形成模塑料化合物，該模塑料化合物沿著該積體電路晶粒與該貫穿通路的側壁延伸；在該積體電路晶粒與該貫穿通路上方形成重佈層；移除該載體基板，暴露該第一層；以及凹陷該第一層，因而該貫穿通路自該第一層突出。
  9. 一種半導體裝置，其包括：積體電路晶粒，其具有正面與背面；模塑料化合物，其係與該積體電路晶粒的側壁相鄰；第一層，其係延伸於該模塑料化合物上方，貫穿通路具有延伸穿過該第一層的貫穿通路突出部；以及背面連接物，其實體接觸該貫穿通路突出部，其中該貫穿通路突出部具有一錐形側壁，錐形側壁之第一部分被該第一層圍繞，而該錐形側壁之第二部分自該第一層突出。
  10. 如申請專利範圍第9項所述之半導體裝置，其中該錐形側壁從該貫穿通路之垂直側壁內縮一寬度。
  11. 如申請專利範圍第9項所述之半導體裝置，其中該模塑料化合物在靠近該貫穿通路處與靠近該積體電路晶粒處具有實質上相同的高度。
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US10283375B2 (en) 2019-05-07
US20210035819A1 (en) 2021-02-04
CN105679681A (zh) 2016-06-15
CN105679681B (zh) 2019-01-18
US20220285171A1 (en) 2022-09-08
US10510556B2 (en) 2019-12-17
US11721559B2 (en) 2023-08-08
US20180061668A1 (en) 2018-03-01
US11342196B2 (en) 2022-05-24
US20190259630A1 (en) 2019-08-22
DE102015110635A1 (de) 2016-06-09
KR101822233B1 (ko) 2018-03-08
US10796927B2 (en) 2020-10-06
US9812337B2 (en) 2017-11-07
US20200083061A1 (en) 2020-03-12
TW201622018A (zh) 2016-06-16
US20160163566A1 (en) 2016-06-09
KR20160067022A (ko) 2016-06-13

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