CN106129038A - 集成电路芯片及其制作方法 - Google Patents

集成电路芯片及其制作方法 Download PDF

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Publication number
CN106129038A
CN106129038A CN201610552274.0A CN201610552274A CN106129038A CN 106129038 A CN106129038 A CN 106129038A CN 201610552274 A CN201610552274 A CN 201610552274A CN 106129038 A CN106129038 A CN 106129038A
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China
Prior art keywords
layer
chip
medium layer
insulating medium
wiring layer
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Pending
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CN201610552274.0A
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English (en)
Inventor
肖明
姚泽强
李恒
银发友
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Chengdu Monolithic Power Systems Co Ltd
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Chengdu Monolithic Power Systems Co Ltd
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Application filed by Chengdu Monolithic Power Systems Co Ltd filed Critical Chengdu Monolithic Power Systems Co Ltd
Priority to CN201610552274.0A priority Critical patent/CN106129038A/zh
Publication of CN106129038A publication Critical patent/CN106129038A/zh
Priority to US15/644,403 priority patent/US20180019199A1/en
Pending legal-status Critical Current

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Abstract

本发明公开了一种包括再布线层和焊接凸起结构的集成电路芯片及其制作方法。所述集成电路芯片通过在再布线层的侧面或者侧面以及上表面覆盖绝缘介质层，从而避免了钝化层和塑封料之间的非紧密直接接触。本发明公开的集成电路芯片通过绝缘介质层与塑封料的紧密接触，避免了铜离子迁移通路的形成。

Description

集成电路芯片及其制作方法
技术领域
本发明涉及集成电路芯片，尤其涉及一种集成电路芯片与外部电路的连接结构和制作方法。
技术背景
随着微电子封装尺寸越来越小，倒装芯片封装逐渐代替传统的导线封装成为主流。
倒装芯片封装利用焊球或者铜柱加焊料凸块将芯片的电极耦接到封装框架、封装衬底或者电路板。其中芯片可能包括多个电极用于接收或者传输信号。
随着芯片面积越来越小，连接不同电极的相邻金属走线之间的间隙越来越小。此时，芯片若工作于高压高湿的环境中或者芯片自身具有大功率的情况下，很容易在连接不同电极的相邻金属走线之间发生离子迁移现象，从而导致连接不同电极的相邻金属走线之间发生短接，从而导致芯片失效。
因此需要一种技术可以在金属走线相邻间隙越来越小的情况下显著减小或者避免离子迁移现象的发生。
发明内容
本发明一实施例提出了一种集成电路芯片，包括：衬底，制作有集成电路和金属层，其中金属层电气耦接至集成电路；钝化层，覆盖在衬底上；通孔，位于钝化层中；再布线层，分布于通孔和部分钝化层上，通过通孔电气耦接至金属层，再布线层具有侧面和上表面；绝缘介质层，分布在再布线层的侧面上；以及焊接凸起结构，分布在再布线层上表面的部分区域上。
本发明一实施例提出了一种集成电路芯片，包括：衬底，制作有集成电路和金属层，其中，金属层电气耦接至集成电路；钝化层，覆盖在衬底上；第一和第二连接单元，其中，第一和第二连接单元间隔开，第一和第二连接单元各包括：通孔，分布在钝化层中；再布线层，分布于通孔和钝化层上，通过通孔电气耦接至金属层，再布线层具有侧面和上表面；以及焊接凸起结构，分布在再布线层上表面的部分区域上；以及绝缘介质层，覆盖在第一和第二连接单元中再布线层的侧面以及第一和第二连接单元之间的钝化层上。
本发明一实施例提出了一种制造集成电路芯片的方法，包括：在制有集成电路芯片的衬底上形成钝化层；在钝化层上通过刻蚀形成通孔；在钝化层表面的部分区域以及通孔中电镀形成再布线层；在再布线层上以及钝化层表面的裸露区域上淀积形成绝缘介质层；对绝缘介质层进行刻蚀形成窗口以漏出再布线层的一部分；以及在再布线层的窗口上电镀形成焊接凸起结构。
根据本发明提供的集成电路芯片及其制作方法，采用在再布线层的侧面或者侧面以及上表面上覆盖绝缘介质层，使得在金属走线相邻间隙越来越小的工艺情况下，有效的减少或者避免了铜离子迁移现象的发生。
附图说明
为了更好的理解本发明，将根据以下附图对本发明的实施例进行描述。这些附图仅用于示例。附图通常仅示出实施例中的部分特征，并且附图不一定是按比例绘制的。
图1给出了根据本发明一实施例的集成电路芯片100的局部示意图。
图2给出了根据本发明另一实施例的集成电路芯片200的局部示意图。
图3给出了根据本发明又一实施例的集成电路芯片300的局部示意图。
图4-14给出了制作如图1所示集成电路芯片100的流程剖面图。
图15-16给出了制作如图2所示集成电路芯片200所需的不同于制作集成电路芯片100的流程剖面图。
不同示意图中的相同的附图标记表示相同或者相似的部分或特征。
具体实施方式
下面将详细描述本发明的具体实施例，应当注意，这里描述的实施例只用于举例说明，并不用于限制本发明。在以下描述中，为了提供对本发明的透彻理解，阐述了大量特定细节。然而，对于本领域普通技术人员显而易见的是，不必采用这些特定细节来实行本发明。在其它实施例中，为了避免混淆本发明，未具体描述公知的电路、材料或方法。
在本公开的说明书及权利要求书中，若采用了诸如“左、右、内、外、上、下、之上、之下”等一类词，均只是为了便于描述，而不表示组件/结构的必然或者永久的相对位置。本领域的技术人员应该理解这类词在合适的情况下是可以互换的，例如，以使的本公开的实施例可以在不同于本说明书描绘的方向下仍可以运作。在本公开的上下文中，将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者他们之间可以存在居中层/元件。此外“耦接”一词意味着以直接或者间接的电气的或者非电气的方式连接。“一个/这个/那个”并不用于特指单数，而可能涵盖复数形式。整个说明书的各个地方出现的短语“一个实施例”、“实施例”、“一个示例”、“示例”不一定都指同一个实施例或者示例。本领域普通技术人员应该理解，在本公开说明书的一个或者多个实施例中公开的各个具体特征、结构或者参数、步骤等可以以任何合适的方式组合。这里使用的术语“和/或”包括一个或多个相关列出的项目的任何和所有组合。
图1给出了根据本发明一实施例的集成电路芯片100的局部示意图。集成电路芯片100包括制作含有集成电路(图中未示出)的衬底101，所述集成电路包括例如DC-DC转换器电路、微控制器电路等等。衬底101还包括金属层102，其位于衬底101上部且电气耦接至集成电路。本领域技术人员应当理解，在某些实施例中，金属层102可以包括单层金属或者多层金属。在金属层102包括多层金属的实施例中，本发明上下文中描述的金属层102与其它结构的连接是指多层金属的最顶层金属与其它结构的连接。本领域技术人员还应当理解，在某些实施例中，制作于衬底101中的集成电路可能包括连接不同信号的多个电极，在这样的实施例中，金属层102包括不同走线(如图1所示102-1和102-2)，其可将集成电路中的各个电极耦接至集成电路芯片100外部的电路。在一实施例中，衬底101还可以包括多层中间介质层。
在图1的示例性实施例中，集成电路芯片100还包括位于衬底101上的钝化层103。在一实施例中，钝化层103包括二氧化硅、氮化硅或者二氧化硅和氮化硅的混合物。在另一实施例中，钝化层103包括例如氮化硅-二氧化硅堆栈层，其中二氧化硅层分布于衬底101上，而氮化硅层分布于二氧化硅层上。
在图1所示实施例中，集成电路芯片100还包括通孔105，通孔105位于钝化层103中，通孔105将金属层102的一部分暴露以便使金属层102与下文将要描述的再布线层106电气耦接。更进一步的，在某些实施例中，通孔105位于金属层102上方的钝化层103。在一实施例中，每个通孔105的长×宽可以具有例如3μm×3μm或者6μm×3μm的尺寸。本领域技术人员应当理解，在图1所示实施例中，通孔105为多个，然而，在其它一些实施例中，通孔105也可以仅为一个。在图1的示例性实施例中，集成电路芯片100还包括分布于通孔105中以及钝化层103的一部分上的再布线层106，其通过通孔105和金属层102之间电气耦接起来，再布线层106具有侧面S1和上表面S2，。在一实施例中，再布线层106包括铜。在一实施例中，再布线层106具有第一厚度T1，所述第一厚度T1根据实际应用设计。在一实施例中，第一厚度T1为1μm至30μm；在另一实施例中，第一厚度T1为5μm至10μm。
在图1所示实施例中，集成电路芯片100还可以包括位于再布线层106和钝化层103之间以及再布线层106与金属层102之间的种子层104，用于改善再布线层106和钝化层103之间以及再布线层106与金属层102之间的粘着力，并可用于防止再布线层106和钝化层103之间以及再布线层106与金属层102之间的金属互相扩散。在一实施例中，种子层104包括铜。
继续图1的说明，集成电路芯片100进一步包括焊接凸起结构110，其位于再布线层106上表面的部分区域上并与再布线层106电气耦接。焊接凸起结构110包括铜柱108和焊料凸起109，铜柱108位于再布线层106上并且与再布线层106电气耦接，焊料凸起109位于铜柱108上并且与铜柱108电气连接。需要说明的是，此处焊料凸起109中所称的“焊料”是指熔点在90℃至450℃范围内的一种易熔金属合金。这种焊料可以是铜、锡、银、锌和/或其它适用金属中至少几种金属的合金。
在图1所示实施例中，集成电路芯片100还包括绝缘介质层107。绝缘介质层107包括绝缘介质材料，其覆盖于再布线层106的侧面S1。在一实施例中，绝缘介质层107还进一步覆盖于再布线层106上表面S2上除去生长焊接凸起结构110的剩余区域。
在一实施例中，绝缘介质层107包括二氧化硅；在另一实施例中，绝缘介质层107包括氮化硅；在又一实施例中，绝缘介质层107包括氮氧化硅。在一实施例中，采用化学气相淀积的方法形成绝缘介质层107；在另一实施例中，采用TEOS(正硅酸乙酯)-臭氧方法淀积二氧化硅形成绝缘介质层107；在其它实施例中可以采用其它任何方法形成绝缘介质层107。在图1所示实施例中，绝缘介质层107的厚度根据实际应用设计；在一实施例中，绝缘介质层107的厚度范围为至在另一实施例中，绝缘介质层107的厚度范围为至
在图1所示实施例中，集成电路芯片100包括至少第一连接单元A和第二连接单元B，第一连接单元A和第二连接单元B隔开，每个连接单元包括：分布在钝化层103中的通孔105；分布在通孔105和钝化层103的一部分上的再布线层106，再布线层106通过通孔105耦接至金属层102；以及分布在再布线层106的上表面的部分区域上的焊接突起结构110。再布线层106具有侧面S1和上表面S2。绝缘介质层107覆盖在两个连接单元中再布线层106的侧面S1以及两个连接单元之间的钝化层103上。在一实施例中，绝缘介质层107还进一步覆盖于两个连接单元中的再布线层106上表面S2上除去生长有焊接凸起结构110的剩余区域。
继续参考图1，在封装过程中，集成电路芯片100被塑封在塑封料中(图1中未示出)。在传统技术中，由于再布线层106的表面和钝化层103的表面不具有绝缘介质层107，塑封料与钝化层103直接接触，由于塑封料和钝化层103本身的物理特性，钝化层103和塑封料的交界面结合不好，从而使得再布线层106中连接不同电极的两相邻走线(如图1所示的106-1和106-2)容易沿钝化层103和塑封料的交界面形成迁移通路从而发生铜离子迁移。在本发明实施例中，再布线层106的表面和钝化层103的表面覆盖有绝缘介质层107，绝缘介质层107本身的物理特性，使其可以与钝化层103紧密接触，即绝缘介质层107与钝化层103的接触面(如图1中示意的交界面112)不容易形成铜离子迁移通道，从而防止再布线层106的连接不同电极的两相邻走线(如106-1和106-2)之间的铜离子迁移。
图2给出了根据本发明另一实施例的集成电路芯片200的局部示意图。图2所示集成电路芯片200与图1所示集成电路芯片100相比还具有缓冲介质层111，缓冲介质层111覆盖在绝缘介质层107的表面。在一实施例中，缓冲介质层111包括聚酰亚胺树脂(Polyimide)；在另一实施例中，缓冲介质层111包括聚对苯撑苯并二噁唑(PBO)。在一实施例中，缓冲介质层111的厚度范围在1μm至20μm之间；在另一实施例中，缓冲介质层111的厚度范围在5μm至10μm之间。缓冲介质层111的柔韧性良好，当集成电路芯片100工作于恶劣环境，比如说高压高湿时，可以释放焊接凸起结构110所承受的应力。
图3给出了根据本发明又一实施例的集成电路芯片300的局部示意图。图3所示集成电路芯片300与图1所示集成电路芯片100相比，给出了另一种焊接凸起结构110。图3所示的焊接凸起结构110包括焊球，其中焊球可以是铜、锡、银、锌和/或其它适用金属中至少几种金属的合金。
图4-14给出了制作图1所示集成电路芯片100的流程剖面图。为了简明起见，图4-14仅示出了一个连接单元，但是应该理解集成电路芯片100可以包含多个连接单元。
首先参考图4，在衬底101上制作集成电路和金属层102。在某些实施例中，金属层102可以包括单层金属或者多层金属。在金属层102包括多层金属的实施例中，此处示出的金属层102指的是多层金属的最顶层金属。在一实施例中金属层102包括铝。金属层102耦接至所述集成电路。
在图4的示例中，进一步在衬底101和金属层102上制作钝化层103。在一实施例中，钝化层103包括氮化硅-二氧化硅堆栈层，其中氮化硅-二氧化硅堆栈层中的二氧化硅层形成于衬底101上，而氮化硅层形成于二氧化硅层上。
下面参考图5，随后在钝化层103中位于金属层102上方的部分制作通孔105。通孔105的长×宽可以具有例如3μm×3μm或者6μm×3μm的尺寸。进一步地，在钝化层103的表面以及通孔105暴露的金属层102的表面形成种子层104。在一实施例中，可以采用溅射的方式形成种子层104。
接下来参考图6，在种子层104上制作电镀掩膜PR1。电镀掩膜PR1包括感光性材料，例如光刻胶。电镀掩膜PR1用于界定制作再布线层106的区域。
接下来如图7示例，以电镀掩膜PR1为掩蔽在种子层104上电镀制作铜以形成再布线层106。在一实施例中，再布线层106具有第一厚度T1，所述第一厚度T1根据实际应用设计。在一实施例中，第一厚度T1为1μm至30μm；在另一实施例中，第一厚度T1为5μm至10μm。
接下来如图8示例，去除电镀掩膜PR1。在一实施例中，电镀掩膜PR1可以采用感光性材料(例如光刻胶)的剥除工艺去除。电镀掩膜PR1去除后，在再布线层106的表面以及钝化层103的表面淀积形成绝缘介质层107。在一实施例中，绝缘介质层107包括二氧化硅；在另一实施例中，绝缘介质层107包括氮化硅；在又一实施例中，绝缘介质层107包括氮氧化硅。在一实施例中，采用化学气相淀积的方法形成绝缘介质层107；在一实施例中采用TEOS(正硅酸乙酯)-臭氧方法淀积二氧化硅形成绝缘介质层107；在其它实施例中可以采用其它任何方法形成绝缘介质层107。绝缘介质层107的厚度根据实际应用设计。在一实施例中，绝缘介质层107的厚度范围为至在另一实施例中，绝缘介质层107的厚度范围为至
接下来参考图9，在绝缘介质层107上制作电镀掩膜PR2,电镀掩膜PR2可以包括感光性材料，例如光刻胶。电镀掩膜PR2用于界定制作焊接凸起结构110的区域。在图9的示例中，电镀掩膜PR2将绝缘介质层107上即将用于电镀形成铜柱108的部分107S暴露，并将绝缘介质层107的其余部分掩盖，然后通过湿法刻蚀、干法刻蚀或者其它合适的技术将绝缘介质层107的部分区域107S刻蚀掉以暴露出如图10所示的再布线层106的部分区域106S。
接下来，继续以电镀掩膜PR2为掩蔽在再布线层106的部分区域106S上电镀制作焊接凸起结构110。在一实施例中，制作焊接凸起结构110包括如图11所示电镀铜形成铜柱108和如图12所示在铜柱108上再次电镀制作锡形成焊料层209。其中铜柱108具有第二高度T2，所述第二高度T2根据实际应用设计，在一实施例中，第二高度T2为35μm至65μm；在另一实施例中，第二高度T2为55μm至65μm。
接下来参考图13，将电镀掩膜PR2去除。然后将图13所示的结构进行热处理。在一实施例中，可以采用回流工艺。回流工艺的步骤包括把图13所示的结构置于回流炉中或者其它热炉中使其历经热能梯度。在回流工艺的步骤中提供的热能使得焊料层209形成焊料凸起109，从而得到如图14所示的结构示意图。其中焊料凸起109具有第三高度T3，所述第三高度T3根据实际应用设计，在一实施例中，第三高度T3为10μm至50μm；在另一实施例中，第三高度T3为25μm至50μm。
如上所述，图4-14给出了制作图1所示集成电路芯片100的流程剖面图，制作图2所示集成电路芯片200的结构只需将上述图9所示的步骤替换成下述图15-16所示的步骤即可，其它步骤类似。
在图8所示的在再布线层106上淀积形成绝缘介质层107后，接下来进行图15所示步骤，在绝缘介质层107的表面覆盖缓冲介质层111。在一实施例中，采用涂抹聚酰亚胺树脂(Polyimide)在绝缘介质层107的表面形成缓冲介质层111；在另一实施例中，采用涂抹聚对苯撑苯并二噁唑(PBO)在绝缘介质层107的表面形成缓冲介质层111。
接下来参考图16，分别刻蚀缓冲介质层111、绝缘介质层107后以暴露出如图16所示的再布线层106的部分区域106S。接下来继续图10的步骤以形成焊接凸起结构110，后继步骤类似。
上述的一些特定实施例仅仅以示例性的方式对本发明进行说明。这些实施例不是完全详尽的，并不用于限定本发明的范围。对于公开的实施例进行变化和修改都是可能的，其它可行的选择性实施例和对实施例中元件的等同变化可以被本技术领域的普通技术人员所了解。本发明所公开的实施例的其它变化和修改并不超出本发明的精神和权利要求限定的保护范围。

Claims (13)

1.一种集成电路芯片，包括：
衬底，制作有集成电路和金属层，其中金属层电气耦接至集成电路；
钝化层，覆盖在衬底上；
通孔，位于钝化层中；
再布线层，分布于通孔和部分钝化层上，通过通孔电气耦接至金属层，再布线层具有侧面和上表面；
绝缘介质层，分布在再布线层的侧面上；以及
焊接凸起结构，分布在再布线层上表面的部分区域上。
2.如权利要求1所述的集成电路芯片，其中所述绝缘介质层还覆盖在再布线层上表面的剩余区域上。
3.如权利要求1所述的集成电路芯片，其中所述绝缘介质层包括二氧化硅、氮化硅或者氮氧化硅。
4.如权利要求1所述的集成电路芯片，其中所述绝缘介质层的厚度区间为至
5.如权利要求1所述的集成电路芯片还包括缓冲介质层，所述缓冲介质层覆盖在绝缘介质层的表面，其中所述缓冲介质层包括聚酰亚胺树脂或者聚对苯撑苯并二噁唑。
6.如权利要求5所述的集成电路芯片，其中所述缓冲介质层的厚度区间为1μm至30μm。
7.一种集成电路芯片，包括：
衬底，制作有集成电路和金属层，其中金属层电气耦接至集成电路；
钝化层，覆盖在衬底上；
第一和第二连接单元，其中，第一和第二连接单元间隔开，第一和第二连接单元各包括：
通孔，分布在钝化层中；
再布线层，分布于通孔和部分钝化层上，通过通孔电气耦接至金属层，再布线层具有侧面和上表面；以及
焊接凸起结构，分布在再布线层上表面的部分区域上；以及绝缘介质层，覆盖在第一和第二连接单元中再布线层的侧面以及第一和第二连接单元之间的钝化层上。
8.如权利要求7所述的集成电路芯片，其中所述绝缘介质层还覆盖在第一和第二连接单元中再布线层上表面的剩余区域上。
9.如权利要求7所述的集成电路芯片，其中所述绝缘介质层包括二氧化硅、氮化硅或者氮氧化硅。
10.如权利要求7所述的集成电路芯片还包括缓冲介质层，所述缓冲介质层覆盖在绝缘介质层的表面，其中所述缓冲介质层可以是聚酰亚胺树脂或者聚对苯撑苯并二噁唑。
11.一种制作集成电路芯片的方法，包括：
在制作有集成电路的衬底上形成钝化层；
在钝化层上刻蚀形成通孔；
在钝化层表面的部分区域以及通孔中电镀形成再布线层；
在再布线层的表面上以及钝化层表面的裸露区域上淀积形成绝缘介质层；
对绝缘介质层进行刻蚀形成窗口以漏出再布线层的一部分；以及
在再布线层的窗口上电镀形成焊接凸起结构。
12.如权利要求11所述的制造集成电路芯片的方法，其中所述绝缘介质层包括二氧化硅、氮化硅或者氮氧化硅。
13.如权利要求11所述的制造集成电路芯片的方法，还包括在形成绝缘介质层后，在绝缘介质层表面上形成缓冲介质层，其中所述缓冲介质层包括聚酰亚胺树脂或者聚对苯撑苯并二噁唑。
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Application publication date: 20161116