CN108269780A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN108269780A
CN108269780A CN201711326822.9A CN201711326822A CN108269780A CN 108269780 A CN108269780 A CN 108269780A CN 201711326822 A CN201711326822 A CN 201711326822A CN 108269780 A CN108269780 A CN 108269780A
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ubm
layer
semiconductor device
isolation structure
seed layer
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CN108269780B (zh
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黄文宏
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

一种半导体装置包含一基板、在基板上之一图案化导电层、在基板上并围绕图案化导电层之一钝化层、在钝化层上且电连接至图案化导电层之一第一球下金属层(under bump metallurgy；UBM)及一第二UBM以及在钝化层上且在第一UBM及第二UBM之间的一隔离结构。

Description

半导体装置及其制造方法
技术领域
本揭露关于一半导体装置及其制造方法，更明确地关于包含在球下金属层(UBM)之间之隔离结构的一半导体装置及其制造方法。
背景技术
因为半导体封装之输入/输出(I/O)的增加，封装中焊锡凸块(包含其下相应之UBM)之间的间距减少。因此，使用习知技术在封装制程中形成焊锡凸块及其下相应UBM(例如藉由一层堆栈形成导电柱)具有挑战性。一种子层经形成用于随后导电柱及焊锡凸块之形成。在焊锡凸块之形成后，未被UMB所覆盖之种子层之部分应被移除(例如藉由一湿蚀刻技术)，以避免焊锡凸块之间的短路。然而，在凝结焊锡凸块所形成之区域中，因为相对高的密度(例如凸块之间距可小于40微米(μm))，难以将用以移除种子层之一蚀刻剂施加进入焊锡凸块之间的空间中。一种增加蚀刻操作之时间及成本的过蚀刻(over-etching)技术可被用以促进焊锡凸块之间种子层之部份的移除，然而在焊锡凸块下之UBM可能被损害。举例而言，可具有宽度15μm之一焊锡凸块应对应至具有宽度约15μm之一UMB。在过蚀刻制程之后，导电柱可能仅剩有宽度9μm(例如导电柱之两侧之每一者损失3μm)，且因此UBM可能容易破裂。
发明内容
根据本揭露之某些实施例，一种半导体装置包含：一基板；一图案化导电层，其位于所述基板上；一钝化层，其位于所述基板上；一第一球下金属层(under bumpmetallurgy；UBM)及一第二UBM，其等位于所述钝化层上；及一隔离结构，其位于所述钝化层上且位于所述第一UBM及所述第二UBM之间。所述钝化层围绕所述图案化导电层。所述等第一及第二UBM电连接至所述图案化导电层。
根据本揭露之某些实施例，一种半导体装置包含：一基板；一图案化导电层，其位于所述基板上；一钝化层，其位于所述基板上；一第一种子层及一第二种子层，其等位于所述钝化层上；及一隔离结构，其位于所述第一种子层及所述第二种子层之间并接触所述第一种子层及所述第二种子层。所述钝化层围绕所述图案化导电层且曝露所述图案化导电层之一第一部分及一第二部分。所述图案化导电层之所述第一部分可与所述图案化导电层之所述第二部分分隔开。所述第一种子层接触所述图案化导电层之所述第一部分，且所述第二种子层接触所述图案化导电层之所述第二部分。
根据本揭露之某些实施例，一种用于制造一半导体装置之方法，其包含：提供一基板；在所述基板上形成一图案化导电层；在所述基板上形成一第一图案化钝化层以围绕所述图案化导电层并以曝露所述图案化导电层之部分；及在所述第一图案化钝化层及所述图案化导电层之经曝露部分之某些部分上形成一第二图案化钝化层。
图式简单说明
当与附图一起阅读时，从下面的详细描述中可以最好地理解本揭露某些实施例的态样。应注意，可能不按比例绘制各种结构，为了清楚的讨论，可以任意增加或减少各种结构的尺寸。
图1A为根据本揭露之某些实施例之一半导体装置之俯视图；
图1B为根据本揭露之某些实施例之一半导体装置之横截面图；
图1C为根据本揭露之某些实施例之一半导体装置之横截面图；
图2A、图2B、图2C、图2D、图2E及图2F绘示根据本揭露之某些实施例之制造一半导体装置之一方法。
图2G及图2H绘示根据本揭露之某些实施例之制造一半导体装置之一方法。
图3A、图3B、图3C、图3D、图3E及图3F绘示根据本揭露之某些实施例之制造一半导体装置之一方法；
图4A及图4B绘示根据本揭露之某些实施例使用一灰阶光罩制造一隔离结构之一方法；
图5A为根据本揭露之某些实施例之一隔离结构之一俯视图；
图5B为根据本揭露之某些实施例之一隔离结构之一俯视图；
图5C为根据本揭露之某些实施例之一隔离结构之一横截面图；及
图5D为根据本揭露之某些实施例之一隔离结构之一横截面图。
实施方法
以下揭露提供多个不同的实施例或例示，用以实施所提供之本发明目标之不同特征。组件及配置之特定例示描述于其下以解释本揭露之某些态样。当然，本揭露仅有数个例示，但并不意图限制本发明之范畴。举例而言，以下所描述在一第二特征上面或之上形成一第一特征可包含第一及第二特征经形成以直接接触的实施例，且可包含额外特征可形成于第一及第二特征之间的实施例，使得第一及第二特征可不直接接触。此外，本揭露可在多个例示中重复参考数字及文字。此种重复系为简易及清楚之目题，且本身并不表示所讨论的各种实施例及/或组态之间的关系。
空间的描述，例如「上方」、「下方」、「上」、「左」、「右」、「下」、「顶部」、「底部」、「垂直」、「水平」、「侧」、「高于」、「下部」、「上部」、「之上」、「之下」等等，系用以指示关于图中所示定向，除非另有说明。应了解本揭露使用的空间的描述仅仅是用于图解之目的，且本揭露描述之结构的实际实施可以以任何定向或方式在空间上配置，只要本揭露之实施例的优点不偏离这种配置。
图1A为根据本揭露之某些实施例之半导体装置100之俯视图。焊锡凸块102(或焊锡球)及隔离结构104经配置为图1A所示。焊锡凸块102可以由导电材料所形成。焊锡凸块102可以由金属、合金或其他相似物所形成。焊锡凸块102可以包含锡(Sn)。隔离结构104可包含一绝缘材料。半导体装置100之一放大图亦绘示于图1A之右上部分。
图1B为根据本揭露之某些实施例之穿过图1A中所示线1-1'之一横截面图。参考图1B，半导体装置100包含焊锡凸块102、隔离结构104、球下金属层(under bump metallurgy；UBM)106、钝化层108、图案化导电层110、导电通孔112、基板114及种子层116。
隔离结构104自钝化层108之顶表面突出。每一隔离结构104可具有，例如但不限于，半椭圆截面。隔离结构104接触种子层116。隔离结构104之一或多者可接触UBM 106下的种子层106。隔离结构104之一者的高度为h1。UBM 106之一者、所述UBM 106上之焊锡凸块102及所述UBM106下之种子层116具有一种高度h2。高度h1及高度h2之比率范围从约0.05至约0.4。高度h1及高度h2之比率范围从约0.1至约0.2。由导电材料所制成之导电通孔112形成于基板114中。基板114上之钝化层108可包含一绝缘材料。钝化层108围绕图案化导电层110。图案化导电层110可包含一导电材料。图案化导电层110电连结至导电通孔112。基板114可包含有机基板、陶瓷基板、玻璃基板或其他适合的基板类型。
UBM 106电连接至图案化导电层110。UBM 106可包含导电柱，所述导电柱包含，例如但不限于，导电层堆栈。在本揭露之某些实施例中，UBM 106可包含导电柱，所述导电柱包含单一导电层。UBM 106可包含黏合促进层(adhesion-promoting layer)、扩散阻障层(diffusion barrier layer)及可焊层(solderable layer)。黏合促进层可包含铝或可接合至其下输入/输出垫(例如铝垫)之其他金属组成。可焊层(例如顶部层)可包含立即可焊之铜(例如铜可被用于焊锡凸块之焊锡合金类型湿润且可接合至用于焊锡凸块之焊锡合金类型)。扩散阻障层可包含镍-钒(NiV)或铬-铜(CrCu)合金，且被置于黏合促进层及可焊层之间以抑制焊锡及铝垫之间的扩散。若一上覆铜层溶于焊锡合中，NiV及CrCu层亦作为一可湿润层。种子层116在UBM 106及图案化导电层110之间。举例而言，UBM 106系形成于种子层116上。此外，一主动组件(例如一半导体芯片或晶粒)之接合端子或垫可经由焊锡凸块102而被接合至UBM 106。
图1C为根据本揭露之某些实施例之半导体装置的一横截面图。参考图1C，除图1C所示之隔离结构104'并未接触UBM 106下之种子层116之外，半导体装置100'相似于参考图1B所绘示及描述之半导体装置100。隔离结构104'与种子层116间隔或隔开。
参考图1B及1C，隔离结构104(或104')及相邻UMB 106之间的距离小于任两个UBM106之间的距离。
图2A、2B、2C、2D、2E及2F绘示根据本揭露之某些实施例之制造半导体装置200之方法。图2A-2F所示之组件相似于关于图1A-1C中所揭示及描述具有相似名称之组件。
参考图2A，由导电材料制成之导电通孔212形成于基板214中。形成于基板214上之钝化层208可包含绝缘材料。钝化层208围绕图案化导电层210。图案化导电层210之一部分由钝化层208之顶表面所曝露。图案化导电层210可包含重布层(redistribution layer；RDL)，其可包含迹线及/或互连(例如通孔)。图案化导电层210可包含导电材料。图案化导电层210电连结至导电通孔212。基板214可包含有机基板、陶瓷基板、玻璃基板或其他适合的基板类型。图案化导电层210及导电通孔212可藉由诸如涂布光罩、蚀刻、沉积、电镀或其他类似技术形成。
参考图2B，隔离结构204形成于钝化层208上以覆盖部分钝化层208及部分导电层210之经曝露部分。隔离结构204可包含绝缘材料。隔离结构204可藉由正型光阻及灰阶光罩(例如下面参考图4A及4B所绘示及描述之光阻402及灰阶光罩404)所形成。
参考图2C，种子层216(例如藉由溅镀(sputtering)技术)形成于隔离结构204、钝化层208及由隔离结构204所曝露之图案化导电层210上。种子层216可包含，例如但不限于，钛(Ti)、铜(Cu)或其组合之层。在某些实施例中，种子层216可包含两个子层，其中下部子层包含Ti且上部子层包含Cu。
参考图2D，图案化光阻218形成于种子层216上。图案化光阻218界定复数个开口217。图案化光阻218可藉由光微影技术形成。举例而言，图案化光阻218可使用涂布光罩、曝光及显影之程序而形成。
参考图2E，UBM 206及焊锡膏202形成于种子层216上。UBM 206及焊锡膏202形成于开口217中。UBM 206及焊锡膏202可藉由电镀形成。UBM 206、焊锡膏202及图案化导电层210电连结。焊锡膏202可由导电材料形成。焊锡膏202可由金属、合金或其他相似物形成。焊锡膏202可包含Sn。UBM 206可包含导电柱，所述导电柱包含，例如但不限于，导电层堆栈。在本揭露之某些实施例中，UBM 206可包含导电柱，所述导电柱包含单一导电层。UBM 206可包含包括Ni及/或Cu之金属组成。
参考图2F，图案化光阻218及在图案化光阻218下之种子层216藉由蚀刻技术而移除(如藉由将蚀刻剂喷洒于图2F所示之结构上)。在喷洒蚀刻剂的期间，旋转图2E所示之结构以促进蚀刻。在隔离结构204及相邻UBM 206(相邻的种子层216之部分)之间的空间或间隔制造毛细作用(capillarity)或虹吸作用(siphonage)以帮助蚀刻剂流进深入所述空间或间隔中并更有效率地移除在图案化光阻218下之种子层216。更甚者，在任意两个UBM 206之间的空间的深宽比(aspect ratio)因为隔离结构204而被实质降低，且被降低的深宽比帮助蚀刻剂流入空间中以便于更有效率地移除在图案化光阻218下的种子层216之部分。
图2F所示之结构可经回焊(reflowed)以形成如图1B所示之半导体装置100(例如一蚀刻剂可被喷洒于焊锡膏202上以形成焊锡凸块102)。
图2G及2H绘示根据本揭露之某些实施例之制造半导体装置之方法。图2G及2H所绘示之步骤可分别用以代替图2E及图2F所绘示之步骤。
参考图2G，在图2D所示图案化光阻218之形成之后，UBM 206及焊锡膏202'被置于开口217中。除了焊锡膏202'经形成超出图案化光阻218之外，图2G所示之结构相似于图2E所示之结构。如此，相对多的焊锡膏202'被用以填入开口217。
参考图2H，图案化光阻218及在图案化光阻218下之种子层藉由蚀刻技术而移除(如藉由将蚀刻剂喷洒于图2H所示之结构上)。在喷洒蚀刻剂的期间，旋转图2H所示之结构以促进蚀刻。在隔离结构204及相邻UBM 206(或相邻的种子层216之部分)之间的空间或间隔制造毛细作用或虹吸作用以帮助蚀刻剂流进深入所述空间或间隔中并更有效率地移除在图案化光阻218下之种子层216。更甚者，在任意两个UBM 206之间的空间的深宽比因为隔离结构204而被实质降低，且被降低的深宽比帮助蚀刻剂流入空间中以便于更有效率地移除在图案化光阻218下的种子层216之部分。
焊锡膏202'可具有一蕈状轮廓。焊锡膏202'包含藉由在图案化光阻218之顶表面上之溢出的焊锡材料所形成之边缘。焊锡膏202'之边缘可不利于移除种子层216，例如在焊锡膏202'之边缘下的种子层216。因为前述之毛细作用、虹吸作用及降低的深宽比，隔离结构204帮助允许蚀利剂流入边缘下之空间。此外，隔离结构204之形状，举例而言但不限于，半椭圆截面，其帮助蚀刻剂流入边缘下之空间并移除图案化光阻218及种子层216之部分。
如图2H所示之结构可经回焊(reflowed)以形成如图1B所示之半导体装置100(例如一蚀刻剂可被喷洒于焊锡膏202上以形成焊锡凸块102)。
图3A、3B、3C、3D、3E及3F绘示根据本揭露之某些实施例之制造半导体装置300之方法。图3A-3F所示之组件相似于图1A-1C中所示或相关描述中具有相似名称之组件。
参考图3A，由导电材料制成之导电通孔312形成于基板314中。形成于基板314上之钝化层308可包含绝缘材料。钝化层308围绕图案化导电层310。图案化导电层310之一部分由钝化层308之顶表面所曝露。图案化导电层310可包含RDL，其可包含迹线及/或互连(例如通孔)。图案化导电层310可包含导电材料。图案化导电层310电连结至导电通孔312。基板314可包含有机基板、陶瓷基板、玻璃基板或其他适合的基板类型。图案化导电层310及导电通孔312可藉由诸如涂布光罩、蚀刻、沉积、电镀或其他类似技术形成。在图3A中，隔离结构304形成于钝化层308上以覆盖部分钝化层308及部分导电层310之经曝露部分。隔离结构304可包含绝缘材料。隔离结构304可藉由正型光阻及光罩所形成。图3A所示之结构相似于图2B所示之结构，但图2B及3A所示之结构之不同在于隔离结构204及304之横截面图。举例而言，隔离结构204之横截面图为半椭圆，且隔离结构304之横截面图为矩形。
参考图3B，种子层316(例如藉由溅镀技术)形成于隔离结构304、钝化层308及由隔离结构304所曝露之图案化导电层310上。种子层316可包含，例如但不限于，一Ti/Cu层。在某些实施例中，种子层316可包含两个子层，其中下部子层包含Ti且上部子层包含Cu。
参考图3C，图案化光阻318形成于隔离结构304上之种子层316之部分上。图案化光阻318界定复数个开口317。图案化光阻318可藉由光微影技术形成。举例而言，图案化光阻318可使用涂布光罩、曝光及显影之程序而形成。光阻318之一部分之宽度实质小于隔离结构304的宽度，其中光阻318之所述部分形成于所述隔离结构304。
参考图3D，UBM 306及焊锡膏302形成于种子层316上。UBM 306及焊锡膏302形成于开口317中。UBM 306及焊锡膏302可藉由电镀形成。UBM 306、焊锡膏302及图案化导电层310电连结。焊锡膏302可由导电材料形成。焊锡膏302可由金属、合金或其他相似物形成。焊锡膏302可包含Sn。UBM 306可包含导电柱，所述导电柱包含，例如但不限于，导电层堆栈。在本揭露之某些实施例中，UBM 306可包含导电柱，所述导电柱包含单一导电层。UBM 306可包含包括Ni及/或Cu之金属组成。如3D所示，UBM 306可形成为包含两区段，每一区段具有不同宽度。
参考图3E，图案化光阻318及在图案化光阻318下之种子层316藉由蚀刻技术而移除(如藉由将蚀刻剂喷洒于图3D所示之结构上)。在喷洒蚀刻剂的期间，旋转图3E所示之结构以促进蚀刻。在任意两个UBM 306之间的空间的深宽比因为隔离结构304而被实质降低，且被降低的深宽比帮助蚀刻剂流入空间中以便于更有效率地移除在图案化光阻318下的种子层316之部分。
图3E所示之结构可藉由一蚀刻剂而被回焊以形成如图3F所示之半导体装置300。如图3E所示之焊锡膏302经回焊以形成焊锡凸块302'。参考图3F，半导体装置300包含焊锡凸块302'、隔离结构304、UBM 306、钝化层308、图案化导电层310、导电通孔312、基板314及种子层316。
图4A及4B绘示根据本揭露之某些实施例以灰阶光罩制造隔离结构之方法。参考图4A，灰阶光罩404用以部分地将光阻402(例如正型或负型光阻)曝露至紫外(UV)光(如箭头所示)，以便于部分地移除在基板400上之光阻402。灰阶光罩404之使用亦允许光阻402之部分被部分地移除(例如光阻402之0％、10％、20％、50％或其他适合的百分比)。根据本揭露之某些实施例，任何适合的灰阶光罩404可被用以形成光阻402之三维表面。
参考图4B，在光阻402之移除之后，形成隔离结构402'。隔离结构402'具有台阶结构。在某些实施例中，当灰阶光罩404之分辨率相对地增加，隔离结构402'之轮廓可为平滑的(例如以形成一半椭圆轮廓)。
图5A展示隔离结构504之一例示之一俯视图，根据某些实施例隔离结构504具有，但不限于一矩形结构。
图5B展示隔离结构504'之一例示之一俯视图，根据某些实施例隔离结构504'具有，但不限于一圆形结构。焊锡凸块502及隔离结构504及504'展示于图5A及图5B中。图5A及5B中所示之组件相似于图1A-1C中所示或相关描述中具有相似名称之组件。
图5C展示横越图5A中所示线2-2'或图5B中所示线3-3'之横截面图。在某些实施例中，隔离结构504或504'具有半椭圆横截面结构。
图5D展示横越图5A中所示线2-2'或图5B中所示线3-3'之横截面图。在某些实施例中，隔离结构504或504'具有三角形横截面结构。为简单起见，图案化导电层、导电通孔及钝化层未示于图5C及5D中。焊锡凸块502、隔离结构504、UBM 506、基板514及种子层516示于图5C及5D中。图5C及5D中所示之组件相似于图1A-1C中所示或相关描述中具有相似名称之组件。
在某些实施例中，隔离结构504之一例示之横截面图可为，但不限于，半圆形。举例而言，横越图5A中所示线2-2'之隔离结构504之一例示之横截面图可为，但不限于半椭圆形、半圆形或一三角形。此外，横越图5B中所示线3-3'之隔离结构504'之一例示之横截面图可为，但不限于半椭圆形、半圆形或一三角形。
在某些实施例中，隔离结构504或504'之例示之三维结构可为，但不限于实质三角锥(triangular pyramid)结构、实质四边形金字塔(quadrangle pyramid)结构、实质多边形金字塔(polygonal pyramid)结构、实质锥(conical)结构、实质球形(spherical)结构、实质半球形(hemispherical)结构、实质非球面(aspherical)结构、实质半非球面(semi-aspherical)结构或实质柱状(pillar)结构。
如本揭露所使用，除非上下文另外清楚地指出，否则单数术语「一」及「所述」可包含复数指示物。
如本揭露所使用，术语「导电」及「电连接」是指传输电流的能力。导电材料通常表示那些对电流流动展示微小或没有反抗的材料。电导率的一个量度为西门子(Siemens)每米(S/m)。通常，导电材料是具有大于约104S/m电导率的材料，例如至少105S/m或至少106S/m的电导率的材料。材料的电导率有时会随温度而变化。除非另外指明，否则材料的电导率在室温下测量。
如本揭露所使用，术语「大约」、「大体上」及「实质」用于描述和解释小的变化。当与事件或环境一起使用时，这些术语可以指事件或环境明确发生的情况，以及事件或环境发生的大约情况。举例而言，当与数值一起使用时，这些术语可以指小于或等于所述数值的±10％的变化范围，诸如小于或等于±5％，小于或等于±4％，小于或等于±3％，小于或等于±2％，小于或等于±1％，小于或等于±0.5％，小于或等于±0.1％，或者小于或等于±0.05％。举例而言，如果两个数值之间的差值小于或等于数值的平均值的±10％，则可以认为两个数值「实质上」相同或相等，诸如小于或等于±5％，小于或等于±4％，小于或等于±3％，小于或等于±2％，小于或等于±1％，小于或等于等于±0.5％，小于或等于±0.1％，或者小于或等于±0.05％。举例而言，「实质上」平行可以指相对于0°的角度变化范围，其小于或等于±10°，小于或等于±5°，小于或等于±4°，小于或等于±3°，小于或等于±2°，小于或等于±1°，小于或等于±0.5°，小于或等于±0.1°，或者小于或等于±0.05°。举例而言，「实质上」垂直可以指相对于90°小于或等于±10°的角度变化范围，例如小于或等于±5°，小于或等于±4°，小于或等于等于±3°，小于或等于±2°，小于或等于±1°，小于或等于±0.5°，小于或等于±0.1°，或者小于或等于±0.05°。
此外，数量，比率和其他数值在本揭露中有时以范围格式呈现。应所述理解的是，这样的范围格式是为了方便和简洁而使用的，并且应当被灵活地理解为包括被明确地指定为范围界限的数值，而且还包括包含在所述范围内的所有单个数值或子范围，如同每个数值和子范围已被明确指定。
尽管本揭露已经参考其具体实施例而描述和说明，但是这些描述和说明不限制本揭露。本领域技术人员应该理解，在不脱离由所附权利要求限定之本公开的真实精神和范围的情况下，可以进行各种改变并且可以替换等同物。图式可能不一定按比例绘制。由于制造工艺和公差的原因，本揭露内容的艺术表现与实际装置之间可能存在区别。本揭露的其他实施例可以没有具体说明。说明书和附图应被认为是说明性的而非限制性的。可以进行修改以使特定情况、材料、物质组成、方法或过程适应本公开的目的、精神和范围。所有这些修改意图在所附权利要求的范围内。尽管已经参考以特定顺序执行之特定操作描述了本揭露公开的方法，但是应理解的是，可以在不偏离本揭露之教示下而对这些操作进行组合，细分或重新排序以形成等同的方法。因此，除非在本揭露中特别指出，操作的顺序和分组并非本揭露的限制。
符号说明
100 半导体装置
100' 半导体装置
102 焊锡凸块
104 隔离结构
104' 隔离结构
106 球下金属层/UBM
108 钝化层
110 图案化导电层
112 导电通孔
114 基板
116 种子层
200 半导体装置
202 焊锡膏
202' 焊锡膏
204 隔离结构
206 UBM
208 钝化层
210 图案化导电层
212 导电通孔
214 基板
216 种子层
217 开口
218 图案化光阻
300 半导体装置
302 焊锡膏
302' 焊锡凸块
304 隔离结构
306 UBM
308 钝化层
310 图案化导电层
312 导电通孔
314 基板
316 种子层
317 开口
318 光阻/图案化光阻
400 基板
402 光阻
402' 隔离结构
404 灰阶光罩
502 焊锡凸块
504 隔离结构
504' 隔离结构
514 基板
516 种子层
h1 高度
h2 高度

Claims (30)

1.一种半导体装置，其包括：
一基板；
一图案化导电层，其位于所述基板上；
一钝化层，其位于所述基板上并围绕所述图案化导电层；
一第一球下金属层(under bump metallurgy；UBM)及一第二UBM，其等位于所述钝化层上并电连接至所述图案化导电层；及
一隔离结构，其位于所述钝化层上且位于所述第一UBM及所述第二UBM之间。
2.如权利要求1之半导体装置，其中在所述第一UBM及所述隔离结构之间的一第一距离小于在所述第一UBM及所述第二UBM之间的一第二距离。
3.如权利要求1之半导体装置，其中所述隔离结构系从所述钝化层的一突出。
4.如权利要求3之半导体装置，其中从所述钝化层的所述突出包括一实质三角锥(triangular pyramid)结构、一实质四边形金字塔(quadrangle pyramid)结构、一实质多边形金字塔(polygonal pyramid)结构、一实质锥(conical)结构、一实质球形(spherical)结构、一实质半球形(hemispherical)结构、一实质非球面(aspherical)结构、一实质半非球面(semi-aspherical)结构或一实质柱状(pillar)结构。
5.如权利要求3之半导体装置，其中所述第一UBM接触所述隔离结构。
6.如权利要求3之半导体装置，其中所述第一UBM与所述隔离结构分隔。
7.如权利要求1之半导体装置，其进一步包括位于所述第一UBM上之一焊锡凸块，及位于所述第一UBM之下的一种子层。
8.如权利要求7之半导体装置，其中所述隔离结构具有一第一高度，且其中所述第一UBM、所述焊锡凸块及所述种子层具有有一第二高度，且所述第一高度与所述第二高度之一比率的范围约0.05至约0.4。
9.如权利要求7之半导体装置，其中所述隔离结构具有一第一高度，且其中所述第一UBM、所述焊锡凸块及所述种子层具有有一第二高度，且所述第一高度与所述第二高度之一比率的范围约0.1至约0.2。
10.如权利要求7之半导体装置，其中所述种子层系置于所述第一UBM及所述钝化层之间。
11.如权利要求7之半导体装置，其中所述种子层接触所述隔离结构。
12.如权利要求7之半导体装置，其中所述隔离结构包含一绝缘材料。
13.如权利要求7之半导体装置，其中所述种子层接触所述隔离结构。
14.如权利要求1之半导体装置，其进一步包括一第三UBM及一第四UBM，其中所述隔离结构系置于所述第一UBM、所述第二UBM、所述第三UBM及所述第四UBM之间。
15.如权利要求1之半导体装置，其进一步包括电连结至所述第一UBM及所述第二UBM的一芯片。
16.一半导体装置，其包括：
一基板；
一图案化导电层，其位于所述基板上；
一钝化层，其位于所述基板上且围绕所述图案化导电层，所述钝化层曝露所述图案化导电层之一第一部分及一第二部分，所述图案化导电层之所述第一部分与所述图案化导电层之所述第二部分分隔开；
一第一种子层及一第二种子层，其等位于所述钝化层上，所述第一种子层接触所述图案化导电层之所述第一部分，且所述第二种子层接触所述图案化导电层之所述第二部分；及
一隔离结构，其位于所述第一种子层及所述第二种子层之间。
17.如请求项16之半导体装置，其进一步包括位于所述第一种子层上的一第一球下金属层(UBM)及位于所述第二种子层上的一第二UBM。
18.如请求项17之半导体装置，其进一步包括位于所述第一UBM上的一焊锡凸块，其中所述隔离结构具有一第一高度，且其中所述第一UBM、所述焊锡凸块及所述第一种子层具有有一第二高度，且所述第一高度与所述第二高度之一比率的范围约0.05至约0.4。
19.如请求项17之半导体装置，其进一步包括位于所述第一UBM上的一焊锡凸块，其中所述隔离结构具有一第一高度，且其中所述第一UBM、所述焊锡凸块及所述第一种子层具有有一第二高度，且所述第一高度与所述第二高度之一比率的范围约0.1至约0.2。
20.如请求项17之半导体装置，其进一步包括一第三UBM及一第四UBM，其中所述隔离结构系置于所述第一UBM、所述第二UBM、所述第三UBM及所述第四UBM之间。
21.如请求项17之半导体装置，其进一步包括电连结至所述第一UBM及所述第二UBM的一芯片。
22.如请求项16之半导体装置，其中所述隔离结构系自所述钝化层的一突出。
23.如请求项16之半导体装置，其中所述隔离结构自所述第一种子层及所述第二种子层隔开。
24.如请求项16之半导体装置，其中所述隔离结构接触所述第一种子层及所述第二种子层。
25.一种用于制造一半导体装置之方法，其包括：
提供一基板；
在所述基板上形成一图案化导电层；
在所述基板上形成一第一图案化钝化层以围绕所述图案化导电层并以曝露所述图案化导电层之部分；及
在所述第一图案化钝化层及所述图案化导电层之经曝露部分之某些部分上形成一第二图案化钝化层。
26.如请求项25之方法，其进一步包括在所述第二图案化钝化层及所述图案化导电层之所述等经曝露部分上形成一种子层。
27.如请求项26之方法，其进一步包括在所述图案化导电层之所述等经曝露部分上之所述种子层上形成复数个球下金属层(UBM)。
28.如请求项27之方法，其进一步包括移除所述第二图案化钝化层上之所述种子层。
29.如请求项28之方法，其中所述第二图案化钝化层与所述等UBM下之所述种子层之部分隔开。
30.如请求项28之方法，其中所述第二图案化钝化层接触所述等UBM下之所述种子层之部分。
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