JP5784280B2 - 電子デバイスパッケージ及び製造方法 - Google Patents
電子デバイスパッケージ及び製造方法 Download PDFInfo
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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Description
Claims (5)
- 電子デバイスパッケージを製造する方法であって、
金属層の第1の面を第1の絶縁層で被覆するステップ、
前記金属層の第2の反対側の面を第2の絶縁層で被覆するステップ、
前記金属層の前記第2の反対側の面に配置された第2の絶縁層の反対側に前記金属層の前記第1の面上に接合位置を露出させるために前記第1の絶縁層をパターン形成するステップ、
前記第2の反対側の面上の前記第2の絶縁層の残存部分が前記第1の面上の前記接合位置の真反対側に配置されるように前記第2の絶縁層をパターン形成するステップ、
分離された同一平面上の金属層を形成するために、前記第2の反対側の面上の前記第2の絶縁層の前記残存部分によって覆われない前記金属層の部分を選択的に除去するステップであって、前記分離された同一平面上の金属層は前記接合位置を含む、ステップ、及び
前記第2の絶縁層の前記残存部分を選択的に除去するステップであって、それにより前記分離された同一平面上の金属層の前記第2の反対側の面上に第2の接合位置を露出させるステップ
を備える方法。 - 請求項1の方法であって、前記パターン形成された第1の絶縁層が前記接合位置と同一平面上にない、方法。
- 請求項1の方法であって、前記接合位置が、前記パターン形成された第1の絶縁層によって互いに分離される方法。
- 請求項1の方法であって、前記パターン形成された第1の絶縁層内の複数の開口部のうちの1つの周囲が、前記分離された同一平面上の金属層のうちの1つの周囲と接触する、方法。
- 請求項1の方法であって、さらに、前記パターン形成された第1の絶縁層の分離された層それぞれがデバイス装着部位として構成された前記接合位置の少なくとも1つを含むように前記パターン形成された第1の絶縁層を分離させるステップを含む方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US12/483,139 | 2009-06-11 | ||
US12/483,139 US7993981B2 (en) | 2009-06-11 | 2009-06-11 | Electronic device package and method of manufacture |
Publications (2)
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JP2010287893A JP2010287893A (ja) | 2010-12-24 |
JP5784280B2 true JP5784280B2 (ja) | 2015-09-24 |
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Application Number | Title | Priority Date | Filing Date |
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JP2010132552A Active JP5784280B2 (ja) | 2009-06-11 | 2010-06-10 | 電子デバイスパッケージ及び製造方法 |
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Country | Link |
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US (2) | US7993981B2 (ja) |
EP (1) | EP2261962A3 (ja) |
JP (1) | JP5784280B2 (ja) |
KR (1) | KR20100133310A (ja) |
CN (1) | CN101924038B (ja) |
SG (1) | SG191632A1 (ja) |
TW (1) | TWI413210B (ja) |
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US20100015340A1 (en) * | 2008-07-17 | 2010-01-21 | Zenergy Power Inc. | COMPOSITIONS AND METHODS FOR THE MANUFACTURE OF RARE EARTH METAL-Ba2Cu3O7-delta THIN FILMS |
US7993981B2 (en) | 2009-06-11 | 2011-08-09 | Lsi Corporation | Electronic device package and method of manufacture |
US8525334B2 (en) * | 2010-04-27 | 2013-09-03 | International Rectifier Corporation | Semiconductor on semiconductor substrate multi-chip-scale package |
TWI427716B (zh) | 2010-06-04 | 2014-02-21 | 矽品精密工業股份有限公司 | 無載具之半導體封裝件及其製法 |
US9142426B2 (en) * | 2011-06-20 | 2015-09-22 | Cyntec Co., Ltd. | Stack frame for electrical connections and the method to fabricate thereof |
US8525312B2 (en) * | 2011-08-12 | 2013-09-03 | Tessera, Inc. | Area array quad flat no-lead (QFN) package |
US9275877B2 (en) * | 2011-09-20 | 2016-03-01 | Stats Chippac, Ltd. | Semiconductor device and method of forming semiconductor package using panel form carrier |
US9129951B2 (en) * | 2013-10-17 | 2015-09-08 | Freescale Semiconductor, Inc. | Coated lead frame bond finger |
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-
2009
- 2009-06-11 US US12/483,139 patent/US7993981B2/en active Active
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2010
- 2010-06-10 TW TW099118956A patent/TWI413210B/zh not_active IP Right Cessation
- 2010-06-10 CN CN201010202786.7A patent/CN101924038B/zh not_active Expired - Fee Related
- 2010-06-10 JP JP2010132552A patent/JP5784280B2/ja active Active
- 2010-06-10 SG SG2013042312A patent/SG191632A1/en unknown
- 2010-06-10 KR KR1020100054807A patent/KR20100133310A/ko not_active Application Discontinuation
- 2010-06-11 EP EP10165738A patent/EP2261962A3/en not_active Withdrawn
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Also Published As
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US20100314747A1 (en) | 2010-12-16 |
SG191632A1 (en) | 2013-07-31 |
KR20100133310A (ko) | 2010-12-21 |
CN101924038A (zh) | 2010-12-22 |
US7993981B2 (en) | 2011-08-09 |
US8384205B2 (en) | 2013-02-26 |
CN101924038B (zh) | 2016-01-06 |
JP2010287893A (ja) | 2010-12-24 |
TW201110267A (en) | 2011-03-16 |
US20110260324A1 (en) | 2011-10-27 |
TWI413210B (zh) | 2013-10-21 |
EP2261962A3 (en) | 2013-02-27 |
EP2261962A2 (en) | 2010-12-15 |
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