TW201816970A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TW201816970A
TW201816970A TW106122617A TW106122617A TW201816970A TW 201816970 A TW201816970 A TW 201816970A TW 106122617 A TW106122617 A TW 106122617A TW 106122617 A TW106122617 A TW 106122617A TW 201816970 A TW201816970 A TW 201816970A
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Taiwan
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semiconductor wafer
region
area
semiconductor device
adhesive layer
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TW106122617A
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English (en)
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黑田壯司
小林達也
青木隆德
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日商瑞薩電子股份有限公司
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Publication of TW201816970A publication Critical patent/TW201816970A/zh

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Abstract

本發明之目的在於提高半導體裝置之可靠性。 本發明之半導體裝置具有：配線基板SUB；接合焊接區BL1；半導體晶片CP，其藉由黏著層AD搭載於配線基板SUB上且具有焊墊電極PA；接合線BW，其連接焊墊電極PA及接合焊接區BL1；及密封體EB。密封體EB在電路形成區域CR中與有機保護膜PI接觸，且在分劃區域SR及焊墊電極PA與分劃區域SR間之區域中未與有機保護膜PI接觸而與表面保護膜10接觸。側面GV1s比側面GV2s更靠近電路形成區域CR側，且黏著層AD覆蓋半導體晶片CP之背面CPb的全面並覆蓋半導體晶片CP之側面GV2s，並且側面GV1s未被黏著層AD覆蓋而與密封體EB接觸。

Description

半導體裝置及其製造方法
本發明係關於半導體裝置及其製造方法，特別關於應用於在基板上搭載半導體晶片並用樹脂加以密封之半導體裝置及其製造方法的有效技術。
日本特開2010-21251號公報(專利文獻1)揭示防止晶粒接合材到達半導體晶片之電路形成面的技術。
日本特開2010-171156號公報(專利文獻2)揭示在藉由具錐形之刀在半導體晶圓中形成溝後，用比該溝寬度薄之刀分割半導體晶圓之階段切割方式的切割處理。 [先前技術文獻] [專利文獻]
[專利文獻1] 日本特開2010-21251號公報 [專利文獻2] 日本特開2010-171156號公報
[發明所欲解決的問題] 本申請案發明人，例如，對BGA[Ball Grid Array(球狀柵格陣列)]型半導體裝置進行檢討，發現以下問題，且該BGA型半導體裝置具有：配線基板；半導體晶片，其藉由黏著層搭載於配線基板上；複數之接合線，其連接形成於配線基板上面之複數之端子及半導體晶片之焊墊電極；及密封體，其用樹脂覆蓋配線基板、半導體晶片及複數之接合線。
在上述半導體裝置中，為確保其可靠性，例如，雖然以溫度範圍(-65℃至150℃)之升溫及降溫為1次循環，實施2000次循環之溫度循環試驗，但在該溫度循環試驗中，確認在接合線及焊墊電極之連接部中產生裂縫的現象。該裂縫引起接合線由焊墊電極剝離之開口不良，因此半導體裝置之可靠性降低。
即，需要提高半導體裝置之可靠性。
其他目的及新特徵可由本說明書之記載及添附圖式了解。 [解決問題的手段]
一實施形態之半導體裝置具有：配線基板；複數之端子，其位於配線基板之周圍；半導體晶片，其藉由黏著層搭載於配線基板上且具有複數之焊墊電極；複數之接合線，其連接複數之焊墊電極及複數之端子；及密封體，其密封配線基板、複數之端子、半導體晶片及複數之接合線。此外，半導體晶片具有：第一主面；背面，其位於第一主面之相反側；及側面，其與第一主面及背面連接，第一主面由包含第一邊之矩形形成並具有電路形成區域及包圍電路形成區域之周圍的分劃區域，且複數之焊墊電極沿著第一邊配置在電路形成區域之周邊部。另外，半導體晶片具有：第一保護膜，其露出複數之焊墊電極且覆蓋電路形成區域及分劃區域並由無機絕緣膜形成；及第二保護膜，其形成於第一保護膜上，露出複數之焊墊電極及分劃區域且覆蓋電路形成區域並由有機絕緣膜形成。密封體在電路形成區域中與第二保護膜接觸，且在分劃區域及複數之焊墊電極與分劃區域間之區域中未與第二保護膜接觸而與第一保護膜接觸。此外，半導體晶片之側面位於分劃區域，且具有連接於第一主面之第一側面及連接於背面之第二側面，第一側面比第二側面更靠近電路形成區域側，且第二側面比第一側面長。另外，黏著層覆蓋半導體晶片之背面的全面且覆蓋半導體晶片之第二側面，第一側面未被黏著層覆蓋而與密封體接觸。 [發明的功效]
依據一實施形態，可提高半導體裝置之可靠性。
雖然在以下實施形態中為方便起見在有必要時，分割成多數段或實施形態來說明，但除了特別明示之情形以外，該等多數段或實施形態並非互相沒有關係，且其關係是其中一者為另一者之一部分或全部的變形例、細節、補充說明等。
此外，在以下實施形態中，提及要素之數等(包含個數、數值、量、範圍等)時，除了特別明示之情形及原理上顯而易見地限定於特定數之情形以外，不限於該特定數，可為特定數以上或以下。
另外，在以下之實施形態中，該構成要素(亦包含要素步驟等)，除了特別明示之情形及考慮原理上顯而易見地為必須之情形等以外，當然不一定是必須的。
同樣地，在以下之實施形態中，提及構成要素等之形狀、位置關係等時，除了特別明示之情形及考慮原理上顯而易見地為必須之情形等以外，實質上包含近似或類似其形狀等者等。這對於上述數值及範圍而言亦相同。
此外，在用以說明實施形態之全部圖中，同一構件原則上賦予同一符號，並省略其重複之說明。另外，俯視圖亦有為容易看見圖式而加上陰影線之情形。
(實施形態) 在本實施形態中，以BGA[Ball Grid Array(球狀柵格陣列)]型半導體裝置為例來說明。首先，說明檢討例之半導體裝置及其問題。
＜檢討例之說明＞ 圖14係檢討例之半導體裝置的剖面圖。半導體裝置具有：配線基板SUB；半導體晶片CP，其藉由黏著層AD搭載於配線基板SUB上；複數之接合線BW，其連接形成於配線基板SUB主面上之複數之接合焊接區(端子)BL1及半導體晶片CP之焊墊電極PA；及密封體EB，其用樹脂覆蓋配線基板SUB、半導體晶片CP及複數之接合線BW。
在此，半導體晶片CP係由例如單晶矽形成，且其線膨脹係數係大約4ppm/K。黏著層AD係由含有氧化鋁等之填料的熱硬化性環氧樹脂形成，且其線膨脹係數係大約40至50ppm/K。密封體EB由含有氧化矽等之填料的熱硬化性環氧樹脂形成，且其線膨脹係數係大約10至40ppm/K。配線基板SUB由在玻璃纖維中含浸環氧樹脂之玻璃環氧樹脂形成，且其線膨脹係數係大約10至15ppm/K。此外，接合線BW係例如銅(Cu)線，且焊墊電極PA由例如鋁層形成。
此外，黏著層AD不僅覆蓋半導體晶片CP之背面CPb的全區域(全面)，亦覆蓋半導體晶片之側面(側壁)CPss，且黏著層AD成為到達半導體晶片CP之主面CPa附近的構造。即，將比較多量之糊狀黏著層AD供給(塗布)至配線基板SUB後，在該配線基板SUB上按壓並黏著半導體晶片CP，因此黏著層AD溢出半導體晶片CP之側面CPss並爬上半導體晶片CP之側面CPss上，藉此形成圖14所示之三角形填角。
藉由使用比較多量之黏著層AD，可減少或防止在配線基板SUB與半導體晶片CP之背面CPb間的黏著層AD中殘留孔洞(空孔)。若在黏著層AD中殘留孔洞，則半導體裝置SD之溫度循環試驗時，在安裝時或動作時半導體裝置SD呈高溫狀態，孔洞內之空氣或水分體積膨脹，並在黏著層AD或半導體晶片CP中產生裂縫。因此，在配線基板SUB與半導體晶片CP之背面CPb間之黏著層AD中不殘留孔洞是重要的。
此外，雖然省略機構說明，但在半導體晶片CP之側面CPss上形成三角形填角時，可減少、防止形成於配線基板SUB之主面側(半導體晶片CP之搭載側)的主面配線的斷線。
因此，減少黏著層AD中之孔洞及在半導體晶片CP之側面CPss上形成填角是重要的。
然而，難以高精度地控制糊狀之黏著層AD的供給量(塗布量)。其原因是，一般而言，糊狀之黏著層AD，例如，使用像稱為「分配器」之注射器的裝置來供給。因此，如圖14所示地，覆蓋半導體晶片CP之側面CPss的黏著層AD成為到達半導體晶片CP之主面CPa附近的構造。
依據本申案發明人之檢討，確認對如此構造之半導體裝置SD實施前述溫度循環試驗時，有在接合線BW與焊墊電極PA之接合部產生裂縫，使接合線BW由焊墊電極PA剝離的問題。
在溫度循環試驗之低溫側，雖然半導體晶片CP及密封體EB收縮，但由於兩者之熱膨脹係數差，向半導體晶片CP之中央部側的應力Fa施加在接合線BW上。此外，由於覆蓋半導體晶片CP之側面CPss之黏著層AD的收縮，向半導體晶片CP之外側的應力Fb施加在半導體晶片CP之主面CPa的端部上。本申請案發明人推定由於應力Fa及應力Fb，在接合線BW與焊墊電極PA之接合部中產生裂縫，使接合線BW產生剝離。另外，焊墊電極PA配置成接近半導體晶片CP之主面CPa的端部時，容易產生裂縫。即，考慮覆蓋半導體晶片CP之側面CPss之黏著層AD收縮產生的應力Fb對產生裂縫之影響大。
此外，亦確認如圖2所示地，雖然半導體晶片CP之中央部形成由聚醯亞胺層等之有機絕緣膜構成之有機保護膜，但在焊墊電極PA與半導體晶片CP之主面CPa端部間的區域中未形成有機保護膜時特別容易產生裂縫。即，在焊墊電極PA與半導體晶片CP之主面CPa端部間的區域中未形成有機保護膜時，由於焊墊電極PA配置成接近半導體晶片CP之主面CPa的端部，容易產生裂縫。此外，在半導體晶片CP之主面CPa的端部中，由於未形成有機保護膜，密封體EB與半導體晶片CP之主面的密接性降低，因此容易產生裂縫。
因此，在本實施形態中，提供減少或防止上述裂縫產生之構造及製造方法。
＜半導體裝置＞ 圖1係本實施形態之半導體裝置的剖面圖，圖2係本實施形態之半導體裝置一部分的半導體晶片的俯視圖，圖3係圖1之A部分的放大剖面圖。此外，圖3係沿著圖2之X-X線的剖面圖。
如圖1所示地，半導體裝置具有：配線基板(基材)SUB；半導體晶片CP，其藉由黏著層AD搭載於配線基板SUB之主面SUBa上；複數之接合線BW，其連接形成於配線基板SUB之主面SUBa上的複數之接合焊接區(端子)BL1及半導體晶片CP之焊墊電極PA；及密封體EB，其用樹脂覆蓋配線基板SUB、半導體晶片CP及複數之接合線BW。
配線基板SUB具有：核心層CL，其由在玻璃纖維中含浸環氧樹脂之玻璃環氧樹脂形成；複數之接合焊接區BL1及複數之球焊接區BL2，其形成於核心層CL之主面及背面；及阻焊層SFa與SFb，其覆蓋核心層CL之主面及背面。
雖然未圖示，但複數之接合焊接區BL1在搭載於配線基板SUB中央部之半導體晶片CP的周圍配置成環狀。此外，雖然未圖示，但複數之球焊接區BL2在配線基板SUB之背面SUBb中，在配線基板SUB之周圍配置成環狀多數列(在圖1中為3列)。
雖然未圖示，核心層CL之主面上配置有藉由與複數之接合焊接區BL1同層之配線層形成的複數之主面配線。此外，複數之主面配線被阻焊層SFa覆蓋，且以不與配置於其上之半導體晶片CP短路的方式電性分離。複數之接合焊接區BL1分別地連接接合線BW，因此由阻焊層SFa露出。
雖然未圖示，核心層CL之背面配置有藉由與複數之球焊接區BL2同層之配線層形成的複數之背面配線。此外，雖然複數之背面配線被阻焊層SFb覆蓋，但複數之球焊接區BL2由阻焊層SFb露出，且複數之球焊接區BL2連接由焊料材形成之焊料球SB。
此外，複數之接合焊接區BL1分別電性連接於對應之球焊接區BL2。複數之接合焊接區BL1及複數之球焊接區BL2包含例如銅(Cu)層及形成於其表面上之金(Au)鍍敷層。阻焊層SFa及SFb係由有機絕緣膜形成。
如圖1所示地，半導體晶片CP之背面CPb藉由黏著層AD黏著於配線基板SUB之主面SUBa。黏著層AD覆蓋半導體晶片CP之背面CPb的全區域(全面)且部份地覆蓋側面CPss。經過半導體晶片CP之全周，黏著層AD由半導體晶片CP之背面CPb連續地爬上側面CPss。即，經過半導體晶片CP之背面CPb的全區域，黏著層AD介於半導體晶片CP之背面CPb與配線基板SUB之主面SUBa間，因此孔洞(空孔)幾乎不存在。
複數之焊墊電極PA形成於半導體晶片CP上，且複數之焊墊電極PA藉由接合線BW連接於複數之接合焊接區BL1。接合線BW在其一端具有球形之球部BA，且該球部BA與焊墊電極PA連接。接合線BW係由例如銅(Cu)線形成，且焊墊電極PA係由例如鋁層形成。接合線BW亦可為金(Au)線。
此外，如圖1所示地，配線基板SUB之主面SUBa、半導體晶片CP、接合線BW被密封體EB覆蓋。密封體EB係由含有氧化矽等之填料的環氧樹脂形成。
如圖2所示地，半導體晶片CP在俯視時雖然其主面CPa具有包含4個邊CPs之正方形，但亦可為長方形(矩形)。此外，在此所謂四角形(正方形、長方形)包含各角部形成倒角之形狀。半導體晶片CP之主面CPa設有：電路形成區域CR；分劃區域SR，其包圍該分劃區域SR之周圍；及導環GR，其設於電路形成區域CR與分劃區域SR之邊界。導環GR具有連續地包圍電路形成區域CR之周圍的4角形環形狀。
沿著半導體晶片CP之各邊CPs，複數之焊墊電極PA排列在電路形成區域CR之周邊部。此外，在本實施形態中，被該周邊部包圍之區域，換言之，半導體晶片CP之主面CPa的中央部未配置焊墊電極PA。各焊墊電極PA具有：接合區域BR，其連接接合線BW之球部BA；及探測區域PBR，其形成抵接探針之痕跡的探測痕跡100。試驗半導體晶片CP之電特性時，雖然將探針抵接在各焊墊電極PA上進行檢查，但藉由令抵接探針之探測區域PBR為與接合區域BR不同之區域，可提高接合線BW之球部BA與焊墊電極PA的連接可靠性。另外，在探測區域PBR中殘留抵接探針之探測痕跡(外傷)100。
焊墊電極PA呈長方形或大略長方形，且其長邊方向上配置接合區域BR及探測區域PBR，並且其長邊具有長度L1。各焊墊電極PA之接合區域BR及探測區域PBR配置在焊墊電極PA與相鄰之邊CPs直交的方向上，且長方形之焊墊電極PA的長邊配置在焊墊電極PA與相鄰之邊CPs直交的方向上。在此，相鄰之邊CPs意味朝與焊墊電極PA長邊直交之方向延伸的邊CPs，即接近該焊墊電極PA之側的邊CPs。
在本實施形態中，焊墊電極PA包含外焊墊電極PA1及內焊墊電極PA2。外焊墊電極PA1配置成比內焊墊電極PA2更接近相鄰之邊CPs。外焊墊電極PA1配置成比內焊墊電極PA2更靠近半導體晶片CP之外側。
外焊墊電極PA1之接合區域BR配置成比探測區域PBR靠近相鄰之邊CPs。另一方面，內焊墊電極PA2之接合區域BR配置成比探測區域PBR遠離相鄰之邊CPs。換言之，外焊墊電極PA1之接合區域BR配置於半導體晶片CP之外側，且探測區域PBR配置於半導體晶片CP之內側。另一方面，內焊墊電極PA2之接合區域BR配置於半導體晶片CP之內側，且探測區域PBR配置於半導體晶片CP之外側。
如此，藉由偏移地配置外焊墊電極PA1及內焊墊電極PA2，可與相鄰之邊CPs平行地配置外焊墊電極PA1及內焊墊電極PA2之探測區域PBR成一列(在假想之直線上)，因此檢查時探針容易抵接。此外，由於可分離地配置外焊墊電極PA1及內焊墊電極PA2之探測區域BR，可減少在與相鄰邊CPs平行之方向上相鄰外焊墊電極PA1與內焊墊電極PA2的間隔。
如圖2所示地，除了焊墊電極PA以外，電路形成區域CR被由聚醯亞胺層等之有機絕緣膜形成的有機保護膜PI覆蓋。分劃區域SR及導環GR中未形成有機保護膜PI，且分劃區域SR及導環GR由有機保護膜PI露出。此外，如圖3所示地，由於導環GR被表面保護膜10覆蓋，為方便起見，在圖2中用虛線顯示。另外，如圖2所示地，電路形成區域CR被導環GR包圍。再者，如圖2所示地，導環GR被分劃區域SR(或者，位於分劃區域SR內之半導體晶片CP的主面CPa的邊CPs)包圍。此外，被沿著4個邊CPs之焊墊電極PA的列包圍的區域，換言之，半導體晶片CP之主面CPa的中央部大範圍地形成有機保護膜PI。另外，夾在電路形成區域CR之角部的焊墊電極PA間的區域及夾在內焊墊電極PA2與其兩側之外焊墊電極PA1間的區域中亦形成有機保護膜PI。再者，未在分劃區域SR中配置有機保護膜PI的原因是防止因切割刀之堵塞而發生問題。此外，未在外焊墊電極PA1與分劃區域SR之間配置有機保護膜PI的原因是防止因小面積聚醯亞胺之剝離而使製造良率降低。
接著，圖3係圖1之A部分的放大剖面圖，且係沿圖2之X-X線的剖面圖。即，沿著外焊墊電極PA1之剖面圖。在圖3中，雖然省略圖1所示之密封體EB，但由圖1可知，圖3所示之半導體晶片CP的主面CPa及側面CPss與密封體EB接觸。
如圖3所示地，半導體晶片CP具有形成於半導體基板1之主面1a中的n通道型MIS電晶體(Qn)及p通道型MIS電晶體(Qp)以及形成於該等MIS電晶體上之多層配線構造。
首先，說明電路形成區域CR。由例如p型單晶矽形成之半導體基板1中形成p型井(半導體區域)2P、n型井(半導體區域)2N及元件分離溝3，且元件分離溝3之內部埋入由例如氧化矽膜形成之元件分離膜3a。
上述p型井2P內形成複數之n通道型MIS電晶體(Qn)。n通道型MIS電晶體(Qn)具有：源極區域ns及汲極區域nd，其形成於由元件分離溝3界定之活性區域ACT中，且形成於p型井2P內；及閘極電極ng，其隔著閘極絕緣膜ni形成於p型井2P上。此外，上述n型井2N內形成複數之p通道型MIS電晶體(Qp)。p通道型MIS電晶體(Qp)具有：源極區域ps及汲極區域pd，其形成於由元件分離溝3界定之活性區域ACT中；及閘極電極pg，其隔著閘極絕緣膜pi形成於n型井2N上。
上述n通道型MIS電晶體(Qn)及p通道型MIS電晶體(Qp)之上部中形成由連接在半導體元件間之金屬膜形成的配線。連接在半導體元件間之配線雖然一般具有大約3層至10層之多層配線構造，但在圖3中顯示用以銅合金為主體之金屬膜構成的2層配線層(第一層Cu配線5、第二層Cu配線7)及用以Al合金為主體之金屬膜構成的1層配線層(第三層Al配線9)，作為多層配線之一例。所謂配線層係使用於共同地表示在各配線層形成之多數配線的情形。配線層之膜厚係第二層配線層比第一層配線層厚，且第三層配線層比第二層配線層厚。
n通道型MIS電晶體(Qn)及p通道型MIS電晶體(Qp)與第一層Cu配線5之間、第一層Cu配線5與第二層Cu配線7之間、及第二層Cu配線7與第三層Al配線9之間分別地形成由氧化矽膜等形成之層間絕緣膜4、5a、6、8及電性連接於3層配線間之插塞p1、p2、p3。
上述層間絕緣膜4例如以覆蓋半導體元件之方式形成於半導體基板上，且第一層Cu配線5形成於該層間絕緣膜4上之層間絕緣膜5a內。第一層Cu配線5例如隔著形成於層間絕緣膜4中之插塞p1電性連接於作為半導體元件之n通道型MIS電晶體(Qn)的源極區域ns、汲極區域nd、閘極電極ng。此外，第一層Cu配線5藉由形成於層間絕緣膜4中之插塞p1電性連接於作為半導體元件之p通道型MIS電晶體(Qp)的源極區域ps、汲極區域pd、閘極電極pg。在圖3中，未圖示閘極電極ng、pg與第一層Cu配線5之連接。插塞p1、p2、p3係由例如W(鎢)膜或銅(Cu)膜構成。第一層Cu配線5係藉由金屬鑲嵌法形成於層間絕緣膜5a之配線溝中，且第一層Cu配線5係由障壁導體膜及其上層之以銅為主體之導體膜的積層構造構成。障壁導體膜係由：鉭(Ta)、鈦(Ti)、釕(Ru)、鎢(W)、錳(Mn)及其氮化物或氮化矽化物、或其積層膜構成。以銅為主體之導體膜係由銅(Cu)或銅合金(銅(Cu)與鋁(Al)、鎂(Mg)、鈦(Ti)、錳(Mn)、鐵(Fe)、鋅(Zn)、鋯(Zr)、鈮(Nb)、鉬(Mo)、釕(Ru)、鈀(Pd)、銀(Ag)、金(Au)、In(銦)、鑭系金屬或錒系金屬等之合金)形成。
第二層Cu配線7例如藉由形成於層間絕緣膜6中之插塞p2電性連接於第一層Cu配線5。第三層Al配線9例如藉由形成於層間絕緣膜8中之p3電性連接於第二層Cu配線7。插塞p3係由金屬膜，例如鎢(W)膜構成。
第二層Cu配線7與插塞p2一體地形成於層間絕緣膜6中，且第二層Cu配線7及插塞p2係由障壁導體膜及其上層之以銅為主體之導體膜的積層構造構成。此外，障壁導體膜及以銅為主體之導體膜係由與第一層Cu配線5同樣之材料形成。
此外，第一層Cu配線5與層間絕緣膜6之間及第二層Cu配線7與層間絕緣膜8之間宜設置防止銅擴散至層間絕緣膜6或8之障壁絕緣膜，且障壁絕緣膜可使用SiCN膜或SiCN與SiCO膜之積層膜。
另外，第三層Al配線9雖然由鋁合金膜(例如，添加Si及Cu之Al膜)形成，但亦可為Cu配線。
此外，層間絕緣膜4、5a、6、8雖然由氧化矽膜(SiO2 )形成，但亦可使用比介電率比氧化矽膜低之稱為低k膜的絕緣膜。當然，亦可由例如，含碳之氧化矽膜(SiOC膜)、含氮及碳之氧化矽膜(SiCON膜)、含氟之氧化矽膜(SiOF膜)的單層膜或積層膜構成。
多層配線之最上層配線層的上述第三層Al配線9上部中形成由例如氧化矽膜、氮化矽膜等之單層膜、或該等2層膜形成的表面保護膜(保護膜、絕緣膜)10，作為最後鈍化膜。表面保護膜10係由無機絕緣膜形成。此外，在形成於該表面保護膜10中之墊開口(開口)10a的底部露出的最上層配線層，即第三層Al配線9構成焊墊電極(墊、電極墊)PA。焊墊電極PA具有接合區域BR及探測區域PBR，且接合區域BR連接接合線BW。
此外，在表面保護膜10上形成由聚醯亞胺層等之有機絕緣膜形成的有機保護膜PI。有機保護膜PI雖然比焊墊電極PA廣大地覆蓋電路形成區域CR之內側，但露出焊墊電極PA、導環GR及分劃區域SR。
接著，如圖3所示地，導環GR係由形成於半導體基板1之主面1a的活性區域ACT中的半導體區域SP、插塞電極p1、第一層Cu配線5、插塞電極p2、第二層Cu配線7、插塞電極p3及第三層Al配線9的積層構造構成。即，第三層Al配線9連接於電極插塞p3，插塞電極p3連接於第二層Cu配線7，第二層Cu配線7連接於插塞電極p2，插塞電極p2連接於第一層Cu配線5，且第一層Cu配線5連接於半導體區域SP。此外，如圖2所示地，導環GR連續地包圍電路形成區域CR之全周。即，構成導環GR之半導體區域SP、插塞電極p1、第一層Cu配線5、插塞電極p2、第二層Cu配線7、插塞電極p3及第三層Al配線9亦各自連續地包圍電路形成區域CR的全周。
接著，如圖3所示地，在分劃區域SR中形成半導體晶片CP之側面(側壁)CPss。側面CPss係位於半導體晶片CP之主面CPa與背面CPb間的面，且具有：側面GV1s，其相對地靠近導環GR、焊墊電極PA或電路形成區域CR；側面GV2s，其相對地遠離導環GR、焊墊電極PA或電路形成區域CR；及連接面GV1c，其連接側面GV1s及GV2s。換言之，靠近導環GR、焊墊電極PA或電路形成區域CR之側面GV1s與主面CPa交叉，且遠離導環GR、焊墊電極PA或電路形成區域CR之側面GV2s與背面CPb交叉，並且位於該2個側面GV1s、GV2s間之面(連接面GV1c)與該2個側面GV1s、GV2s交叉。
側面GV1s由半導體晶片CP之主面CPa連續地連接，且側面GV2s由半導體基板1之背面1b連續地連接。側面GV1s及GV2s相對於半導體基板1之背面1b為垂直，且連接面GV1c相對於半導體基板1之背面1b為平行。但是，亦可相對於半導體基板1之背面1b傾斜。即，連接於半導體晶片CP之主面CPa的側面GV1s之一端可比連接於連接面GV1c的側面GV1s之另一端更接近導環GR、焊墊電極PA或電路形成區域CR。此外，連接面GV1c亦可相對半導體基板1之背面1b傾斜。另外，連接面GV1c可非直線而為圓弧等之曲線。
藉由在側面GV1s與側面GV2s間設置成為段差之連接面GV1c，可用連接面GV1c阻擋由半導體晶片CP之背面CPb爬上側面CPss的黏著層AD，且可防止黏著層AD爬上側面GV1s。
在此，重要的是以半導體基板1之背面1b為基準，側面GV2s之長度(高度)H1比側面GV1s之長度(高度)(H2-H1)長(高)。在此，長度(高度)H2為在半導體晶片CP之側面CPss中，由半導體晶片CP之背面CPb到表面保護膜10之上面的長度(高度)。上述之關係是，換言之，側面GV2s之長度(高度)H1比由半導體晶片CP之背面CPb到表面保護膜10之上面的長度(高度)的1/2長(高)。此外，半導體晶片CP之背面CPb與半導體基板1之背面1b相等。
因此，藉由充分地確保側面GV2s，可使用多量黏著層AD將半導體晶片CP黏著在配線基板SUB上，因此可用黏著層AD覆蓋半導體晶片CP之背面CPb的全面，並可減少或防止在半導體晶片CP之背面CPb與配線基板SUB間的黏著層AD中產生孔洞。
此外，重要的是側面GV1s比元件分離膜3a之底部深。即，可防止由半導體晶片CP之背面CPb爬上側面CPss的黏著層AD到達半導體晶片CP之主面CPa附近，因此可減少或防止因伴隨黏著層AD收縮之應力而產生焊墊電極PA與接合線BW之接合部的裂縫。
此外，層間絕緣膜4、5a、6或8使用脆弱之低k膜時，亦有黏著層AD到達層間絕緣膜4、5a、6或8時，由於伴隨黏著層AD收縮之應力，裂縫沿著層間絕緣膜4、5a、6或8之界面由側面GV1s向電路形成區域CR產生、伸展的危險性。但是，在本實施形態中，由於黏著層AD未到達層間絕緣膜4、5a、6或8，可防止上述裂縫之產生、伸展。
此外，如圖3及圖1可知，在外焊墊電極PA1之內側(半導體晶片CP之主面CPa的中央部側、電路形成區域CR之中央部側)，表面保護膜10被有機保護膜PI覆蓋。即，有機保護膜PI接觸密封體EB。另一方面，在外焊墊電極PA1之外側(分劃區域SR側、導環GR側)，表面保護膜10未被有機保護膜PI覆蓋，表面保護膜(無機保護膜)10接觸密封體EB。此外，更詳細地說明分劃區域SR內之結構，如圖3所示地，密封體EB具有：與形成於分劃區域SR之一部份中的表面保護膜10接觸的部分；與藉由後述切割步驟露出之半導體晶片CP的連接面GV1c接觸的部分；及與位於上述分劃區域SR之一部份與半導體晶片CP之連接面GV1c間的側面GV1s接觸的部分。另外，外焊墊電極PA1配置成接近導環GR，且外焊墊電極PA1與導環GR之間隔L2比外焊墊電極PA1之長邊方向的寬度L1窄(L2＜L1)，因此成為難以在外焊墊電極PA1與分劃區域SR間配置有機保護膜PI的構造。
由於在外焊墊電極PA1之外側未配置有機保護膜PI，相較於外焊墊電極PA1之內側，在外焊墊電極PA1之外側，密封體EB與半導體晶片CP之主面CPa的黏著性低，例如，在溫度循環或實際使用時等，成為密封體EB容易由半導體晶片CP之主面CPa剝離的構造。此外，若密封體EB與半導體晶片CP之主面CPa間產生剝離，在溫度循環或實際使用時等，在接合線BW與外焊墊電極PA1之接合部容易產生裂縫。但是，覆蓋半導體晶片CP之側面CPss的黏著層AD未爬上側面GV2s，且未到達側面GV1s，因此可減少或防止因黏著層AD收縮產生之接合線BW與外焊墊電極PA1的接合部的裂縫。
因此，在外焊墊電極PA1之外側不存在有機保護膜PI之構造中，亦可減少或防止上述裂縫。此外，外焊墊電極PA1與分劃區域SR之間未配置有機保護膜PI時，由於可使外焊墊電極PA1接近分劃區域SR，可達成半導體晶片CP之小型化。另外，將圖2所示之內焊墊電極PA2更換成外焊墊電極PA1，亦可使全部焊墊電極PA成為外焊墊電極PA1，此時，半導體晶片CP可更進一步小型化。
＜半導體裝置之製造方法＞ 圖4係顯示本實施形態之半導體裝置製造步驟的流程圖。圖5係本實施形態之半導體裝置製造步驟中的俯視圖。圖6係沿著圖5之Y-Y線的剖面圖。圖7至圖8係本實施形態之半導體裝置製造步驟中的剖面圖。此外，圖6至圖8係半導體晶圓之概略剖面圖。圖9至圖11係本實施形態之半導體裝置製造步驟中的俯視圖。圖12係本實施形態之半導體裝置製造步驟中的剖面圖。
本實施形態之半導體裝置的製造方法包含圖4所示之製造步驟。
首先，實施圖4之製程中所示之「準備半導體晶圓WF」步驟(步驟S1)。
如圖5所示地，半導體晶圓WF具有配置成行列狀之複數之電路形成區域CR及配置於複數之電路形成區域CR間之格子狀的分劃區域SR。如圖3所示地，各電路形成區域CR中形成n通道型MIS電晶體(Qn)及p通道型MIS電晶體(Qp)、形成於該等MIS電晶體上之複數之配線構造及複數之焊墊電極PA。此外，如圖2及圖3所示地，在電路形成區域CR與分劃區域SR之間形成導環GR。
圖6係沿著圖5之Y-Y線的剖面圖。如圖6所示地，電路形成區域CR與分劃區域SR交互地配置，且導環GR配置在電路形成區域CR與分劃區域SR之邊界。
接著，實施圖4之製程中所示之「第一切割」步驟(步驟S2)。
如圖7所示地，使用寬度W1之切割刀DB1，在半導體晶圓WF之分劃區域SR內，形成深度D1、寬度W1之溝GV1。溝GV1形成於半導體晶圓WF之主面WFa中，且未到達背面WFb。溝GV1內形成側面GV1s及底面GV1b。在此，溝GV1之深度D1等於圖3所示之側面GV1s的長度(H2-H1)。
接著，實施圖4之製程中所示之「第二切割」步驟(步驟S3)。
如圖8所示地，使用寬度W2之切割刀DB2，在半導體晶圓WF之分劃區域SR內，形成深度D2、寬度W2之溝GV2。溝GV2之寬度W2比溝GV1之寬度W1窄(W2＜W1)，且溝GV2形成於溝GV1之內側。即，形成由溝GV1之底面GV1b到達半導體晶圓WF之背面WFb的溝GV2。溝GV2內形成側面GV2s，且側面GV2s與側面GV1s之間形成底面GV1b之一部份的連接面GV1c。在此，溝GV2之深度D2等於圖3所示之側面GV2s的長度H1。
如此對半導體晶圓WF實施「第一切割」步驟及「第二切割」步驟，可由半導體晶圓WF形成複數之半導體晶片CP。此外，各個半導體晶片CP具有包含側面GV1s、側面GV2s及連接面GV1c之側面CPss。
接著，實施圖4之製程中所示之「晶片接合」步驟(步驟S4)。
首先，如圖9所示地，準備基質基板(基材)20。基質基板20具有：裝置區域22，其配置成行列狀；框部21，其包圍配置成行列狀之複數之裝置區域22的周圍；切斷線DL，其設置在框部21與裝置區域22之間及在相鄰裝置區域22之間。接著，在裝置區域22中形成晶片搭載部23及配置於其周圍之複數之接合焊接區BL1。晶片搭載部23等於圖2所示之半導體晶片CP的平面形狀。
接著，如圖9所示地，在晶片搭載部23之中央部，圓形地塗布糊狀之黏著層AD。黏著層AD係由例如含有氧化鋁等之環氧樹脂構成。
接著，如圖10所示地，將半導體晶片CP按壓在圖9所示之晶片搭載部23上，並藉由黏著層AD將半導體晶片CP黏著在基質基板20之裝置區域22中。藉由加熱糊狀之黏著層AD使溶劑氣化，將半導體晶片CP黏著在裝置區域22中。此外，該裝置區域22相當於圖1所示之配線基板SUB。此時，如圖1所示地，以用黏著層AD覆蓋半導體晶片CP之背面CPb的全部的方式，使用比較多量之糊狀黏著層AD，因此如圖10所示地，黏著層AD經過半導體晶片CP之全周圍由半導體晶片CP之周圍擠出，如圖3所示地爬上半導體晶片CP之側面CPss。
但是，由於半導體晶片CP之側面CPss具有側面GV1s及側面GV2s，如圖3所示地，黏著層AD只覆蓋側面GV2s，未越過連接面GV1c到達側面GV1s。
接著，實施圖4之製程中所示之「線接合」步驟(步驟S5)。
如圖11所示地，使用接合線BW將形成於半導體晶片CP中之複數之外焊墊電極PA1及複數之內焊墊電極PA2連接於接合焊接區BL1。接合線BW雖然由例如銅(Cu)線形成，但亦可使用金(Au)線。
接著，實施圖4之製程中所示之「樹脂密封」步驟(步驟S6)。
如圖12所示地，「晶片接合」步驟及「線接合」步驟結束後，用密封體EB覆蓋基質基板20上之複數之半導體晶片CP及接合線BW。在「樹脂密封」步驟中，使用例如轉移模製法。此外，圖12中只顯示1個裝置區域22。
接著，實施圖4之製程中所示之「形成焊料球SB」步驟(步驟S7)及「單片化」步驟(步驟S8)。
接著，在圖12所示之基質基板20的球焊接區BL2上形成焊料球SB後，沿著圖9所示之切斷線DL，切斷密封體EB及基質基板20使之單片化，藉此形成圖1所示之半導體裝置SD。
(變形例) 以上，雖然依據實施形態具體地說明了由本發明人作成之發明，但本發明不限於上述實施形態，當然可在不脫離其要旨之範圍內進行各種變更。以下，雖然顯示多數變形例，但亦可適當組合各個變形例來實施。
＜變形例1＞ 圖13係上述實施形態之關於圖9的變形例。
在圖13中，以連結基質基板20之正方形晶片搭載部23的對向角部的方式塗布糊狀之黏著層AD1成十字形。藉由使黏著層AD1之塗布區域呈十字形，可在半導體晶片CP之背面CPb上以均一之膜厚形成黏著層AD1。
此外，在上述實施形態中，雖然以BGA型半導體裝置為例說明，但亦可適用於QFP(Quad Flat Package(四面扁平封裝))型之半導體裝置或SOP(Small Outline Package(小輪廓封裝))型之半導體裝置，在此情形中，上述實施形態之配線基板(基材)SUB更換成引線框(基材)，而接合焊接區BL1更換成引線(端子)。此外，半導體晶片CP藉由黏著層AD搭載於引線框之晶粒墊(舌片、晶片搭載部)的主面上。此外，晶粒墊及引線係由例如銅(Cu)材形成。
1‧‧‧半導體基板
1a‧‧‧主面
1b‧‧‧背面
2P‧‧‧p型井(半導體區域)
2N‧‧‧n型井(半導體區域)
3‧‧‧元件分離溝
3a‧‧‧元件分離膜
4‧‧‧層間絕緣膜
5‧‧‧第一層Cu配線
5a‧‧‧層間絕緣膜
6‧‧‧層間絕緣膜
7‧‧‧第二層Cu配線
8‧‧‧層間絕緣膜
9‧‧‧第三層Al配線
10‧‧‧表面保護膜
10a‧‧‧墊開口(開口)
20‧‧‧基質基板(基材)
21‧‧‧框部
22‧‧‧裝置區域
23‧‧‧晶片搭載部
100‧‧‧探測痕跡(外傷)
ACT‧‧‧活性區域
AD‧‧‧黏著層
BA‧‧‧球部
BL1‧‧‧接合焊接區(端子)
BL2‧‧‧球焊接區
BR‧‧‧接合區域
BW‧‧‧接合線
CL‧‧‧核心層
CP‧‧‧半導體晶片
CPa‧‧‧主面
CPb‧‧‧背面
CPs‧‧‧邊
CPss‧‧‧側面(側壁)
CR‧‧‧電路形成區域
DB1‧‧‧切割刀
DB2‧‧‧切割刀
DL‧‧‧切斷線
D1‧‧‧深度
D2‧‧‧深度
EB‧‧‧密封體
Fa‧‧‧應力
Fb‧‧‧應力
GR‧‧‧導環
GV1‧‧‧溝
GV2‧‧‧溝
GV1b‧‧‧底面
GV1c‧‧‧連接面
GV1s‧‧‧側面
GV2s‧‧‧側面
H1‧‧‧長度(高度)
H2‧‧‧長度(高度)
L1‧‧‧寬度
L2‧‧‧間隔
nd‧‧‧汲極區域
ng‧‧‧閘極電極
ni‧‧‧閘極絕緣膜
ns‧‧‧源極區域
p1‧‧‧插塞(插塞電極)
p2‧‧‧插塞(插塞電極)
p3‧‧‧插塞(插塞電極)
PA‧‧‧焊墊電極
PA1‧‧‧外焊墊電極
PA2‧‧‧內焊墊電極
PBR‧‧‧探測區域
pd‧‧‧汲極區域
pg‧‧‧閘極電極
PI‧‧‧有機保護膜
pi‧‧‧閘極絕緣膜
ps‧‧‧源極區域
Qn‧‧‧n通道型MIS電晶體
Qp‧‧‧p通道型MIS電晶體
SB‧‧‧焊料球
SD‧‧‧半導體裝置
SFa‧‧‧阻焊層
SFb‧‧‧阻焊層
SP‧‧‧半導體區域
SR‧‧‧分劃區域
SUB‧‧‧配線基板(基材)
SUBa‧‧‧主面
SUBb‧‧‧背面
S1~S8‧‧‧步驟
WF‧‧‧半導體晶圓
WFa‧‧‧主面
WFb‧‧‧背面
W1‧‧‧寬度
W2‧‧‧寬度
[圖1]係一實施形態之半導體裝置的剖面圖。 [圖2]係一實施形態之半導體裝置一部分的半導體晶片的俯視圖。 [圖3]係圖1之A部分的放大剖面圖。 [圖4]係顯示一實施形態之半導體裝置製造步驟的流程圖。 [圖5]係一實施形態之半導體裝置製造步驟中的俯視圖。 [圖6]係沿著圖5之Y-Y線的剖面圖。 [圖7]係接續圖5之半導體裝置製造步驟中的剖面圖。 [圖8]係接續圖7之半導體裝置製造步驟中的剖面圖。 [圖9]係接續圖8之半導體裝置製造步驟中的俯視圖。 [圖10]係接續圖9之半導體裝置製造步驟中的俯視圖。 [圖11]係接續圖10之半導體裝置製造步驟中的俯視圖。 [圖12]係接續圖11之半導體裝置製造步驟中的剖面圖。 [圖13]係顯示對圖9之變形例的俯視圖。 [圖14]係檢討例之半導體裝置的剖面圖。

Claims (16)

  1. 一種半導體裝置，包含： 基材； 複數之端子，位於該基材之周圍； 半導體晶片，藉由黏著層搭載於該基材上，且具有複數之第一焊墊電極； 複數之接合線，連接該複數之第一焊墊電極及該複數之端子；及 密封體，將該基材、該複數之端子、該半導體晶片及該複數之接合線予以密封； 該半導體晶片具有：第一主面；背面，其位於該第一主面之相反側；及側面，其位於該第一主面及該背面之間， 該第一主面由包含第一邊之形狀形成， 該第一主面具有電路形成區域及包圍該電路形成區域之分劃區域， 該複數之第一焊墊電極沿著該第一邊且配置在該電路形成區域之周邊部， 該半導體晶片具有： 第一保護膜，其由無機絕緣膜形成，露出該複數之第一焊墊電極且覆蓋該電路形成區域及該分劃區域之一部份；及 第二保護膜，其由有機絕緣膜形成，形成於該第一保護膜上，且露出該複數之第一焊墊電極及該分劃區域並覆蓋該電路形成區域， 該密封體在該電路形成區域中與該第二保護膜接觸，且在該分劃區域之一部份及該複數之第一焊墊電極與該分劃區域間之區域中未與該第二保護膜接觸而與該第一保護膜接觸， 該半導體晶片之該側面位於該分劃區域，且具有連接於該第一主面之第一側面及連接於該背面之第二側面，該第一側面比該第二側面更靠近該電路形成區域側，且該第二側面比該第一側面長， 該黏著層覆蓋該半導體晶片之該背面的全面且覆蓋該半導體晶片之該第二側面，該第一側面未被該黏著層覆蓋而與該密封體接觸。
  2. 如申請專利範圍第1項之半導體裝置，其中： 該半導體晶片包含：半導體基板，具有第二主面；及活性區域，形成於該第二主面中且被元件分離膜包圍， 該半導體晶片之該電路形成區域具有MISFET，該MISFET形成於該活性區域中且包含閘極電極、源極區域及汲極區域。
  3. 如申請專利範圍第2項之半導體裝置，其中： 該第一側面以該第一主面為基準，比該元件分離膜更接近該半導體晶片之該背面側。
  4. 如申請專利範圍第1項之半導體裝置，其中更具有： 導環，其在俯視時，位於該電路形成區域與該分劃區域之間，且連續地包圍該電路形成區域之周圍。
  5. 如申請專利範圍第4項之半導體裝置，其中更具有： 層間絕緣膜，其形成於該複數之第一焊墊電極的下方， 該層間絕緣膜與該複數之第一焊墊電極接觸， 該導環包含接觸該層間絕緣膜上而形成的配線層。
  6. 如申請專利範圍第5項之半導體裝置，其中： 該導環包含埋入該層間絕緣膜且連接於該配線層之插塞電極。
  7. 如申請專利範圍第4項之半導體裝置，其中： 該複數之第一焊墊電極各具有： 第一接合區域，連接於該接合線；及 第一探測區域，與該第一接合區域相鄰， 在與該第一邊直交之方向上，該第一接合區域配置在比該第一探測區域更靠近該第一邊之側。
  8. 如申請專利範圍第7項之半導體裝置，其中： 該複數之第一焊墊電極各自在與該第一邊直交之方向上具有第一寬度，且自沿著該第一邊延伸之該導環分開第一距離而配置， 該第一距離比該第一寬度小。
  9. 如申請專利範圍第7項之半導體裝置，其中更具有： 第二焊墊電極，其沿該第一邊配置， 該第二焊墊電極具有：第二接合區域，連接於該接合線；及第二探測區域，與該第二接合區域相鄰， 在與該第一邊直交之方向上，該第二探測區域配置在比該第二接合區域更靠近該第一邊之側。
  10. 如申請專利範圍第9項之半導體裝置，其中： 該第一探測區域與該第二探測區域在與該第一邊平行之方向上成直線地配置。
  11. 如申請專利範圍第9項之半導體裝置，其中： 在與該第一邊直交之方向上，於該第二焊墊電極與該第一邊之間形成該第二保護膜。
  12. 如申請專利範圍第1項之半導體裝置，其中： 該半導體晶片係由單晶矽形成， 該黏著層及該密封體分別由環氧樹脂形成。
  13. 一種半導體裝置之製造方法，包含以下步驟： (a)準備具有電路形成區域、包圍該電路形成區域之分劃區域及形成於該電路形成區域之周邊部的複數之焊墊電極的半導體晶圓； (b)沿該分劃區域，形成具有第一深度及第一寬度之第一溝； (c)沿該分劃區域，在該第一溝內，形成具有比該第一深度更深之第二深度及比該第一寬度狹窄之第二寬度的第二溝，並將該半導體晶圓分割成複數之半導體晶片； (d)在具有複數之端子之基材上，藉由黏著層，黏著該半導體晶片； (e)用複數之接合線連接該半導體晶片之該複數之焊墊電極與該複數之端子；及 (f)用樹脂密封該基材、該複數之端子、該半導體晶片及該複數之接合線，形成密封體， 該半導體晶片具有：第一主面；背面，位於該第一主面之相反側；及側面，位於該第一主面與該背面之間， 該第一主面由包含第一邊之形狀形成，且具有該電路形成區域及包圍該電路形成區域之該分劃區域， 該半導體晶片具有：第一保護膜，由無機絕緣膜形成，露出該複數之焊墊電極且覆蓋該電路形成區域及該分劃區域之一部份；及第二保護膜，由有機絕緣膜形成，形成於該第一保護膜上，且露出該複數之焊墊電極及該分劃區域並覆蓋該電路形成區域， 該密封體在該電路形成區域中與該第二保護膜接觸，且在該分劃區域之一部份及該複數之焊墊電極與該分劃區域間之區域中未與該第二保護膜接觸而與該第一保護膜接觸， 該半導體晶片之該側面具有：第一側面，由該第一溝形成；第二側面，其由該第二溝形成；及連接面，其連接該第一側面及該第二側面， 該黏著層覆蓋該半導體晶片之該背面的全面且覆蓋該半導體晶片之該第二側面，該第一側面未被該黏著層覆蓋而與該密封體接觸。
  14. 如申請專利範圍第13項之半導體裝置之製造方法，其中： 該(d)步驟具有以下步驟： (d-1)供給該黏著層至該基材上；及 (d-2)將該半導體晶片按壓在該黏著層上。
  15. 如申請專利範圍第14項之半導體裝置之製造方法，其中： 在該(d-1)步驟中，供給俯視圖中呈圓形之該黏著層。
  16. 如申請專利範圍第14項之半導體裝置之製造方法，其中： 該半導體晶片在俯視時呈矩形， 於該(d-1)步驟中，以俯視時呈連結該矩形半導體晶片之對向角部的方式供給十字形的該黏著層。
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TWI826237B (zh) * 2022-07-08 2023-12-11 南亞科技股份有限公司 具有固定構件以設置鍵合線的半導體元件

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US10651103B2 (en) * 2016-10-28 2020-05-12 Qorvo Us, Inc. Environmental protection for wafer level and package level applications
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