TWI702659B - 傳導阻障直接混合型接合 - Google Patents

傳導阻障直接混合型接合 Download PDF

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TWI702659B
TWI702659B TW105126081A TW105126081A TWI702659B TW I702659 B TWI702659 B TW I702659B TW 105126081 A TW105126081 A TW 105126081A TW 105126081 A TW105126081 A TW 105126081A TW I702659 B TWI702659 B TW I702659B
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conductive barrier
barrier material
conductive
contact
layer
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TW105126081A
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TW201715620A (zh
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保羅 恩奎特斯
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美商英帆薩斯邦德科技有限公司
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Abstract

形成直接混合型接合的方法和源自直接混合型接合的裝置，其包括：第一基板，其具有第一組金屬接合襯墊(其較佳而言連接到裝置或電路，而由傳導阻障所覆蓋)，並且具有第一非金屬區域(其相鄰於第一基板上的金屬接合襯墊)；第二基板，其具有第二組金屬接合襯墊(其由第二傳導阻障所覆蓋、對齊於第一組金屬接合襯墊、較佳而言連接到裝置或電路)，並且具有第二非金屬區域(其相鄰於第二基板上的金屬接合襯墊)；以及接觸接合介面，其在第一和第二組金屬接合襯墊之間、由傳導阻障所覆蓋、而藉由第一非金屬區域對第二非金屬區域的接觸接合所形成。

Description

傳導阻障直接混合型接合
本發明關於直接接合的領域，更特定而言關於混合型直接接合(較佳而言在室溫或低溫)；更特別而言關於半導體材料、裝置或電路的接合，而要用於堆疊半導體裝置和積體電路製作；甚至更特別而言關於製作消費者和商業產品中的附加價值零件，包括行動電話中的影像感測器、行動電話中的射頻(RF)前端、高效能圖形產品中的三維(three dimensional，3D)記憶體、伺服器中的3D記憶體。
對於以較小形式因素、較低成本來增加功能性的持續要求而言，晶粒、晶片或晶圓堆疊已經變成工業標準實務。一般而言，堆疊可以隨著堆疊諸層之間的電互連來做，而形成作為堆疊過程的一部分或在堆疊過程之後。在堆疊過程之後所形成的電互連之範例乃使用貫穿矽通孔(through silicon via，TSV)蝕刻，並且填充穿過堆疊中的一層而到堆疊中的相鄰層裡，以在堆疊的諸層之間做出電互連。形成作為堆疊過程之一部分的這些三維(3D)電互連的範例包括焊料凸塊和銅柱(其具有或沒有底填)、混合型接合、直接混合型接合。將3D電互連實現成堆疊過程的一部分則就許多原因來說是有利的，包括但不限於免除TSV(貫穿矽通孔)科技的成本和專屬需求。直接混合型接合也稱為直接接合互連(direct bonding interconnect， DBI®)，則就許多原因來說要比其他形式的堆疊來得有利，包括但不限於在金屬和介電表面構件上方有平坦的接合(其在低溫下提供高強度)以及能夠做到尺度達次微米的3D互連間距。
用於直接混合型接合的金屬和介電表面構件可以由金屬和介電質的各式各樣組合所組成，其以各式各樣的製作技術而形成各式各樣的圖案。金屬的非限制性範例包括銅、鎳、鎢、鋁。舉例而言見：P.Enquist的「用於三維積體電路應用的高密度直接接合互連(DBITM)科技」，材料研究協會研討會議事錄，第970冊，2007年，第13~24頁；P.Gueguen等人的「銅直接接合做的3D垂直互連」，材料研究協會研討會議事錄，第1112冊，2009年，第81頁；P.Enquist的「直接接合互連(DBI®)作為三維整合架構和應用之大量商業化的驅動器所擁有的縮放性和低成本優點」，材料研究協會研討會議事錄，第1112冊，2009年，第81頁；Di Cioccio等人的「歸功於鎢直接接合的垂直金屬互連」，第60屆ECTC的2010年議事錄，第1359~1363頁；H.Lin等人的「使用低溫晶圓接合的直接Al-Al接觸來整合MEMS和CMOS裝置」，微電子工程，第85期(2008年)，第1059~1061頁。介電質的非限制性範例包括氧化矽、氮化矽、氧氮化矽、氮化矽碳。舉例而言見：P.Enquist的「3D科技平臺──先進的直接接合科技」，C.S.Tan、K.N.Chen、S.J.Koester(編輯者)，「用於VLSI系統的3D整合」，Pan Stanford，ISBN 978-981-4303-81-1，2011年；J.A.Ruan、S.K.Ajmera、C.Jin、A.J.Reddy、T.S.Kim的「在蝕刻停止層和介電層之間具有改善附著和減少起泡的半導體裝置」，美國專利第7732324B2號。各式各樣圖案的非限制性範例包括通孔陣列或金屬線和空間的陣列，舉例而言如在互補式金屬氧化物半導體(CMOS) 生產線後端(back-end-of-line，BEOL)互連製作中的通孔和接線層所發現的。以這些範例來說，3D電互連可以藉由金屬通孔對金屬通孔、金屬通孔對金屬線、或金屬線對金屬線的對齊和接合而形成。建造適合混合型接合的表面之製作技術的非限制性範例是工業標準的單一和雙重鑲嵌過程，其若有需要的話則加以調整以滿足適合的拓樸規格。
基本上有二種CMOS BEOL製程。一種典型而言稱為鋁(Al)BEOL，另一種稱為銅(Cu)BEOL。於Al BEOL過程，具有適合之傳導阻障層的Al典型而言使用作為接線層，並且具有適合之傳導阻障層的鎢(W)則用於通孔層以在二相鄰Al接線層之間做電互連。Al接線層典型而言被乾式蝕刻，後續以介電質沉積來平坦化，接著再做化學機械拋光(chemo-mechanical polishing，CMP)。W通孔層典型而言是以單一鑲嵌過程所形成，其由以下所組成：介電質沉積、通孔圖案化和蝕刻到先前的接線層、藉由物理氣相沉積和W化學氣相沉積而以傳導阻障層來填充通孔、並且做W和傳導阻障層的CMP以隔離介電基質裡的W通孔或栓塞。於Cu BEOL過程，具有適合之傳導阻障層的Cu典型而言使用作為接線和通孔層。Cu接線和通孔層典型而言是以雙重鑲嵌過程所形成，其由以下所組成：介電質沉積、通孔圖案化和蝕刻部分穿過介電層、接著做接線圖案化(其重疊著通孔圖案化)並且同時繼續蝕刻(多個)通孔到先前的接線層，其中接線重疊著部分蝕刻的通孔，並且蝕刻出用於接線的溝槽，其連接到先前具有通孔的接線層。替代性的雙重鑲嵌過程是由以下所組成：介電質沉積、接線圖案化和蝕刻部分穿過介電層(其在到達先前的接線層則停止)、通孔圖案化和蝕刻到先前的接線層，其中通孔是在部分蝕刻的接線裡，並且蝕刻完成了 通孔蝕刻到先前的接線層。任一雙重蝕刻表面然後填充了傳導阻障層(舉例而言藉由物理氣相沉積來為之)，接著再做Cu填充(舉例而言藉由電鍍或物理氣相沉積加電鍍來為之)，最後做Cu和傳導阻障層的CMP以隔離介電基質裡的Cu接線。
使用上述工業標準的W或Cu鑲嵌流程則可以用來形成用於混合型接合的表面，而接受適合的表面拓樸，舉例而言如上所提供。然而，當這些表面用於混合型接合時，典型而言在一表面上的金屬和在另一表面上的介電質之間將有異質接合構件，舉例而言這是由於通孔表面未對齊的緣故。這可以導致來自一接合表面的通孔填充材料直接接觸來自另一接合表面的介電質，而沒有插入傳導阻障(其在Cu或W填充通孔和包圍介電質之間的其他地方)。
較佳的是具有用於直接混合型接合過程科技之低熱預算的寬製程窗口，而斟酌影響目前合格於CMOS BEOL半導體廠的材料和過程，以降低使直接混合型接合過程合格於該半導體廠的採行障礙。Cu BEOL過程是此種較佳能力的範例，因為Cu鑲嵌過程已經是多年的工業標準，並且Cu直接混合型接合科技能夠斟酌影響這基礎架構。斟酌影響Al BEOL工業標準過程已經是比較具挑戰性的，因為此過程中的二種主要金屬W和Al由於包括高降伏強度、熱膨脹係數(coeffieient of thermal expansion，CTE)、原生氧化物、小丘形成等因素的組合而對於發展W或Al的直接混合型接合科技來說是比較具挑戰性的材料。
本發明的具體態樣乃針對形成直接混合型接合表面的方 法，其包括：在第一基板的上表面中形成多個第一金屬接觸結構，其中所述結構的頂面是在該上表面之下；在該上表面和所述多個金屬接觸結構上方形成傳導阻障材料做的第一層；以及從該上表面移除傳導阻障材料做的該第一層。
1‧‧‧導體
2‧‧‧傳導阻障
3‧‧‧介電質
4‧‧‧金屬結構
5‧‧‧開口
6‧‧‧傳導阻障金屬層
7‧‧‧傳導阻障
8‧‧‧通孔構件
9‧‧‧連線構件
10、11‧‧‧未對齊
12‧‧‧直接混合型接合
13‧‧‧傳導部分
14‧‧‧介電部分
15‧‧‧直接混合型接合表面
16‧‧‧傳導阻障
17‧‧‧介電表面
18‧‧‧混合型接合表面
19‧‧‧連線構件
20、21‧‧‧未對齊
23‧‧‧傳導貫穿矽通孔(TSV)結構
24‧‧‧絕緣材料
25‧‧‧傳導TSV結構
26‧‧‧傳導阻障材料層
27‧‧‧阻障層
28‧‧‧絕緣阻障
30‧‧‧基板
31‧‧‧介電質表面
32~43‧‧‧基板
t1、t2‧‧‧碟化、距離
當關於伴隨圖示來考慮而參考以下詳細敘述時，由於更加了解則將輕易獲得對本發明的更完整體會和其達成的許多優點，其中：圖1是單一或雙重鑲嵌過程所形成的傳導層之靠近表面區域的示意截面圖，其具有填充的通孔和/或接線，而在填充的通孔和/或接線與包圍介電質之間則有傳導阻障；圖2是圖1在從包圍介電質的表面移除傳導層之後的示意截面圖；圖3是圖2在形成傳導阻障材料層之後的示意截面圖；圖4是圖3在從包圍介電質的表面移除傳導阻障層材料層之後的示意截面圖；圖5是二個混合型直接接合表面正在接合的示意圖；圖6是二個混合型直接接合表面在接觸個別的介電層之後的示意圖；圖7是二個混合型直接接合表面已直接接合的示意圖；圖8是傳導阻障材料的上表面因為碟化而彎曲的示意圖；圖9是根據本發明之一對基板的示意圖，其中類似的通孔結構未對齊於傳導阻障，並且通孔對齊於針對具有傳導阻障之接線結構的傳導阻障；圖10是表面之靠近表面區域的示意截面圖，該表面由圖案化的金屬層所組成，其以包圍介電質加以平坦化，而平坦化暴露圖案化的金屬層，在 金屬層和包圍介電質的側向之間沒有傳導阻障層；圖11是圖10的示意截面圖，其中圖案化的金屬層之暴露表面的傳導部分根據本發明而覆蓋了傳導阻障金屬；圖12是根據本發明之一對接觸基板的示意圖，其舉的例子是在金屬層和包圍介電質的側向之間沒有傳導阻障下將沒有對於接線結構之傳導阻障的接線結構加以對齊；圖13是本發明之另一具體態樣的示意圖，其具有貫穿矽通孔結構；圖14是圖13之結構的示意圖，其具有第二傳導阻障材料層；以及圖15是本發明之另一具體態樣的示意圖，其具有貫穿矽通孔結構而在側壁上具有介電層。
現在參見圖式，其中全篇相同的參考數字指稱相同或對應的零件，並且特別參見圖1，其顯示在根據本發明之直接混合型接合過程中的基板30之表面的截面，其由導體1、傳導阻障2、介電質3、金屬結構4所組成。金屬結構4形成在介電質3中。金屬結構4位在介電質3裡，並且可以是接觸、襯墊、線或其他金屬互連結構。開口形成在金屬結構4上方的介電質3中，接著形成阻障2和導體1。導體1、傳導阻障2、金屬結構4的尺寸和厚度並未按照比例，而是為了示範本發明所繪製。雖然開口和金屬結構顯示成有相同的尺寸和形狀，不過它們的尺寸和形狀可以有所不同，此視設計或需要而定。
用於導體1的可能是各式各樣的金屬，包括但不限於Cu和W，其分別常見於Cu和Al BEOL半導體廠。Cu可以藉由物理氣相沉積 (physical vapor deposition，PVD)或電鍍(electroplating，EP)而沉積，並且W可以藉由化學氣相沉積(chemical vapor deposition，CVD)而沉積。用於傳導阻障材料2的也可能是各式各樣的傳導阻障，其常見於Cu和Al BEOL半導體廠。Cu BEOL過程中的傳導阻障包括鉭(Ta)、氮化鈦(TiN)、氮化鉭(TaN)、氮化鎢(WN)、氧化釕(RuO2)、氮化鉭矽(TaSiN)、氮化鈦矽(TiSiN)、氮化鎢硼(TBN)、硼化鈷鎢(CoWB)、磷化鈷鎢或其組合(舉例而言為Ti/TiN和Ta/TaN)，其可以藉由各式各樣的技術來沉積，包括PVD、CVD、金屬有機CVD(metal organic CVD，MOCVD)。有各式各樣的PVD技術可用，包括直流(DC)磁控濺鍍、準直濺鍍、離子化金屬電漿(ionized metal plasma，IMP)。Al BEOL過程中的傳導阻障包括Ti/TiN。其他材料也有可能作為阻障，舉例而言為鎳(Ni)。
也可能有各式各樣的介電質，包括但不限於氧化矽、氮化矽、碳氮化矽，其常見於Cu和Al BEOL半導體廠。生成圖1截面所述表面的常見方法是上述的鑲嵌過程。
圖1的上表面接受CMP以移除介電質3的頂部上之部分的導體1和傳導阻障2。圖2示範在CMP之後的結構。導體1和傳導阻障2相對於介電質3的相對高度可以藉由鑲嵌過程的CMP部分來控制。
導體1和傳導阻障2相對於介電質3的高度則有許多組態。導體1和阻障2的頂面可以在介電質3的表面之下、甚至之中、名義上甚至之中或之上。一般而言，直接混合型接合有可能具有所有的組態。然而，較佳的組態則是導體1和傳導阻障2的相對高度是在介電質3之下的距離t1。這組態有助於形成無空洞的接合介面，並且對於跨越接合表面的相對高 度變化而言是更可製造的。對於最適合直接混合型接合的表面來說，跨越傳導層的接合表面而在介電質3之下的相對高度變化之範例是在介電質3之下一到十奈米，雖然也可能有較小和較大的變化。這凹陷典型而言稱為碟化(dishing)。所得表面稱為沒有傳導阻障2的混合型接合表面。
相容於混合型接合的典型碟化量是0到20奈米，其稱為標準碟化。標準碟化的增加量乃相當於圖4所示之後續傳導阻障7(其形成在圖2所示這增加碟化形成開口5的頂部上)的厚度，所導致的碟化則相當於標準碟化並且相容於直接混合型接合所要的。標準碟化增加的範例是5~20奈米，導致約5~40奈米的總碟化t1。這標準碟化的增加可以用各式各樣的方式來形成，舉例而言增加用來生成標準碟化的CMP直到達成所要的增加碟化為止。這CMP的增加可以由CMP時間的增加來完成，該時間量可以由常規的校正所決定，並且可以是CMP襯墊、漿液、向下力、承載器和桌臺旋轉、混合型表面上之導體和介電質的圖案等的函數。
如圖3所示，傳導阻障金屬層6形成在結構上方而在圖2所示的介電質表面31上。阻障6的材料可以相同或不同於傳導阻障2。增加碟化之後在導體1的頂部上形成阻障6則可以用許多方式來形成，舉例而言為鑲嵌過程，其包括在整個表面上方沉積傳導阻障，接著做CMP以從較高的介電表面移除傳導阻障，而不從凹陷裡移除層6之顯著量或所有的傳導阻障材料。阻障的形成也可以用選擇性過程來形成，舉例而言為無電鍍鎳。所得結構在導體1和傳導阻障2之頂部上的每個開口5中具有傳導阻障7。這所得的碟化較佳而言相容於直接混合型接合所需者，亦即傳導阻障7的表面是在介電質3的表面之下小於20奈米，較佳而言為1~10奈米。 圖4示意所示之所得表面的截面稱為具有傳導阻障7的混合型接合表面。
層6的厚度可以小於導體1/阻障2的碟化量，如圖3所示，或者可以相同或厚於這碟化量。於前者情形，僅從凹陷移除部分的層6或不移除。於層6相同或厚於凹陷量的情形，層6藉由CMP而從凹陷裡移除。層6在所有情形下被移除，如此則所得的碟化在形成阻障7中小於20奈米，較佳而言1~10奈米。
基板30的每個混合型接合表面可以包含裝置和/或積體電路(未顯示)，使得這些裝置和/或積體電路在完成混合型接合之後可以彼此連接。裝置和電路可以包含金屬結構4，或者可以經由未示範之進一步的互連結構而連接到金屬結構4。
皆具有傳導阻障7而有例如圖4所示的示意截面之基板30和32的二個混合型接合表面現在可以彼此做直接混合型接合，如圖5和6的截面所示，以形成直接混合型接合12。將基板30和32對齊(圖5)並且放置成直接接觸，使得基板30和32中的介電層3彼此接觸(圖6)。對齊和接觸可以在室溫下進行，而在室內氣氛或真空下。雖然圖式示意顯示在基板30和32的阻障7之間有間隙，但是在對齊和接觸之後，阻障7之間可以有部分或顯著的接觸。雖然一對一的連接安排顯示於圖6，不過可能有其他的安排，例如一基板中的多個金屬結構接合於另一基板中的單一金屬結構。
基板30和32的介電表面較佳而言如美國專利申請案第09/505,283、10/359,608、11/201,321號所述的製備。簡言之，表面可加以蝕刻、拋光、活化和/或終端有所要的接合物種，以促進和提升基板30和32上的介電質3之間的化學接合。製造出粗糙度方均根為0.1到3奈米之介電 質3的平滑表面，其經由溼式或乾式過程來活化和/或終端化。
隨著基板表面在室溫接觸，基板表面的介電質3開始在一或多個接觸點形成接合，並且晶圓之間的吸引接合力隨著化學接合面積增加而增加。這接觸可以包括阻障7或不包括阻障7。如果接觸包括阻障7，則介電質3中之基板對基板化學接合所產生的壓力導致有使阻障7之接觸區域強烈結合的力，並且基板30和32中的介電質3之間的化學接合在二個不同晶圓上的金屬襯墊之間產生電連接。
阻障7抵靠著彼此的內部壓力(源自基板30和32的介電質3之間的接合)可能不適合達成較佳而言具有低電阻的電連接，舉例而言這是由於原生氧化物或其他汙染(舉例而言為烴)的緣故。改善的接合或較佳而言為較低電阻的電連接可以藉由移除阻障7上的原生氧化物來達成。舉例而言，可以使用稀釋的氫氟酸來清潔表面；或者在移除原生氧化物之後直到進行接合為止，基板30和32的表面可以暴露於惰性氣氛，舉例而言為氮或氬。
內部壓力也可能不足以使阻障7的足夠表面彼此接觸。替代或附帶而言，阻障7之間的改善接合或較佳而言為較低電阻的電連接可以藉由加熱來達成。加熱的範例包括範圍在100~400℃的溫度、在10分鐘和2小時之間的時間，此視用於接觸結構4、阻障6、導體1的材料而定。有可能對於給定的材料組合做時間和溫度的最佳化。舉例而言，較短的加熱時間可能可以有較高的溫度，並且較低的溫度可能可以有較長的加熱時間。加熱時間可以減到最少和/或加熱溫度可以減到最少的程度則將取決於特定的結構和材料組合，並且可以由常見的製程最佳化實務來決定。舉例而 言，如果阻障7是鎳，則300℃的溫度達二小時或者350℃的溫度達15分鐘可以是足以改善接合和改善電連接。也可能有較高和較低的溫度和/或時間，此視阻障7的材料和阻障7底下的其他材料而定。溫度增加可以藉由減少原生氧化物或其他汙染或者藉由增加阻障7之間的內部壓力(因為導體1和阻障7的熱膨脹)而導致較佳而言為低電阻的電連接。材料4和在材料4之下的其他材料(未示範)也可以增加在阻障7底下的結構熱膨脹，並且對應的增加相對阻障7之間的壓力。舉例而言，如果材料4是具有關聯之CTE和楊氏模數的鋁，則相較於具有較低CTE和/或楊氏模數的替代性材料4可以產生較高的壓力。加熱也可以增加阻障7之間的交互擴散以產生較佳的較低電阻電連接。
如果基板30和32的介電質3之間的起初接合不包括阻障7，則可以使用加熱以導致阻障7之間的接觸，因為阻障7的CTE高於介電質3。加熱或溫度上升的量則取決於阻障7之間的分離、阻障7和導體1和金屬結構4的厚度、CTE、楊氏模數，因為對於給定的溫度上升來說，這些參數影響相對阻障7之間的壓力。舉例而言，相較於20奈米的分離，使阻障7之間的分離減到最小(舉例而言小於10奈米)則可以減少加熱。舉進一步範例來說，阻障7和/或導體1的高度或厚度將增加壓力，因為阻障7和導體1的熱膨脹將隨著厚度而增加。舉例而言，阻障7和導體1的典型膨脹增加是與厚度成正比。舉進一步範例來說，具有較高楊氏模數的導體1預期要比具有較低楊氏模數的替代性導體1產生更高的壓力，因為較高楊氏模數的材料在當產生壓力時較不可能降伏。具有較低楊氏模數的阻障7可以不需要像它可以藉由在較低壓力下降伏而便於形成連接的那麼多的加 熱。當基板30和32的表面起初接觸時，如果阻障7不是緊密接觸，則在加熱之後，導體1和阻障7的熱膨脹因此導致有緊密接觸的低電阻連接，如圖7所示。
雖然導體1/阻障2和阻障7的表面在上面的範例中顯示成平坦的，不過該一或二者由於CMP過程的緣故而可以具有某些彎曲。輪廓顯示於圖8，其中二者都具有彎曲。於圖8，顯示的基板33具有阻障7和導體1/阻障2，其表面有所變化。阻障7的厚度較佳而言是夠厚以容納導體1之粗糙度的涵蓋範圍，但不是太厚而使製作變得複雜。典型的厚度範圍可以是5~20奈米。阻障在彎曲之中間和邊緣的相對厚度可以較厚或較薄，此視在阻障7沉積在導體1之前的接觸1表面形成的彎曲和阻障7形成的彎曲而定，舉例而言這是因為用來形成接觸1之表面的CMP過程和用來形成阻障7之表面的CMP過程有不同的特徵之緣故。阻障7的中央乃凹陷在介電質3的表面之下小於20奈米，較佳而言為1~10奈米。
圖9示範具有混合型接合表面之二個基板34和35的上部。具有傳導阻障的混合型接合表面可以包括通孔構件8，其連接到底下的連線構件(未顯示)；或者包括連線構件9，其連接到底下的通孔構件(未顯示)。在接合之後，在個別混合型接合表面之間典型而言有些未對齊於傳導阻障。這未對齊可以導致第一混合型接合表面上的傳導阻障7接觸第二混合型接合表面上的介電表面31，以及導致第一混合型接合表面上的介電表面31接觸第二混合型接合表面上的傳導阻障7，如圖9的10所示。這未對齊也可以導致一混合型接合表面上的傳導阻障7接觸另一表面上的介電表面31，以及導致來自一表面之傳導阻障7的整個表面接觸另一混合型接合表 面上之傳導阻障7的部分表面，如圖9的11所示。
儘管有這未對齊，根據本發明，第一或第二混合型接合表面上之介電質3的表面接觸另一混合型接合表面上的傳導阻障7，並且在第一或第二混合型接合表面上的傳導阻障7接觸另一混合型接合表面上之傳導阻障7或介電質3的表面。儘管未對齊，導體1之頂部上的傳導阻障7因此避免導體2和介電質3之間有所接觸。舉例而言當Cu使用作為導體1而具有Cu BEOL所建造的Cu單一或雙重鑲嵌直接混合型接合表面，本發明的這特色可以改善直接混合型接合的可靠度，舉例而言對於考量如果Cu直接接觸介電質3則Cu會擴散到介電質3裡的應用來說便是如此。該特色對於某些結構來說也可以便於跨越接合介面而形成電連接，舉例而言，當導體1是Al BEOL所建造的W栓塞單一鑲嵌直接混合型接合表面，則在相對表面上的導體1之間做出電連接要比在相對表面上之導體1的頂部上的傳導阻障7之間做出電連接還更有挑戰性。
圖2所示的碟化量可以影響使用這些表面而具有凹陷傳導部分之後續直接混合型接合的熱預算。舉例而言，在將直接混合型接合表面起初放置成直接接觸之後，介電部分可以呈直接接觸，並且所有或某些的凹陷傳導部分可以因為凹陷而不直接接觸。加熱具有凹陷傳導部分的這些直接混合型接合表面可以導致凹陷傳導部分膨脹，如此則它們在高於直接混合型接合表面被帶去接觸的溫度下，甚至在更高的溫度下，被帶去直接接觸，並且產生顯著壓力以便於相對凹陷傳導部分之間有電連接。這些更高的溫度可以便於在相對的凹陷傳導部分之間形成電互連並且完成直接混合型接合。將凹陷部分帶去直接接觸並且產生顯著壓力以便於相對凹陷 傳導部分之間有電連接所需的溫度則是傳導材料、傳導材料上的殘餘或原生氧化物、傳導材料的降伏強度、傳導材料的碟化或凹陷等的組合。舉例而言，較少的碟化可以導致在低溫或室溫下起初直接接合相對介電表面之後需要較低的熱預算來完成混合型接合，這是因為需要較少的導體1和傳導阻障7的膨脹以在相對傳導阻障7的表面之間形成金屬接合。
舉例而言，當使用Ni作為傳導阻障時，可以藉由加熱到約350℃而容納10奈米的凹陷；相較而言，如果使用銅而無覆蓋傳導阻障，則約200℃便可以是足夠的。為了減少熱預算，一般來說使用較高CTE(熱膨脹係數)的材料而具有較低降伏強度和較少的碟化則是有用的。一般而言，CTE和降伏強度是由選擇的阻障所給定，並且碟化是可變的，其可加以變化來達成適合的熱預算。熱預算也可以受到在導體底下之材料的影響。舉例而言，在導體1底下而具有較高CTE(亦即每℃高於15ppm)的導體1(舉例而言為金屬結構4，如圖4所示)要形成混合型接合電連接所具有的熱預算可以低於具有較低CTE的導體1和/或金屬結構4。每℃高於15ppm之高CTE金屬的範例包括Cu和Al，其是常見於Al和Cu BEOL過程中的導體。
於根據本發明的第二具體態樣，由介電部分14所包圍的傳導部分13則包括在基板36中的直接混合型接合表面15，如圖10所示。傳導部分13的範例是鋁，並且介電部分14的範例是層間介電質，其範例為用於Al BEOL的氧化矽和其他介電質，其乃用於Al BEOL之典型材料的範例。金屬部分13可以包括通孔和/或接線圖案，其連接到底下的互連層。介電部分14可以是連續鄰接的，舉例而言如果傳導部分僅由通孔所組成的話； 或者介電部分14可以不是連續鄰接的，舉例而言如果傳導部分是由接線圖案所分開的話。於此具體態樣，直接混合型接合表面15較佳而言具有在直接混合型接合規格裡的碟化傳導部分。這表面可以藉由Al金屬化、介電質沉積、CMP平坦化的組合而形成，以形成具有圖10所示截面的表面。Al金屬化可以包括在頂部上的傳導阻障，舉例而言為Ti。如果有傳導阻障並且它藉由CMP平坦化而移除，則表面將具有圖10所示的截面。如果傳導阻障是夠厚以致它未被CMP平坦化所整個移除，並且有適合的碟化r2(舉例而言為用於混合型接合的混合型接合表面有0~20奈米的傳導阻障部分)，則這表面(譬如圖11所示)可以適合直接混合型接合，而不必額外的傳導阻障沉積和CMP。
圖10所述的碟化t2所增加的量則相當於後續傳導阻障16(其形成在這增加之碟化的頂部上)的厚度，而導致相當於圖10並且相容於直接混合型接合(圖10)所需的碟化。這厚度的增加是在約5~20奈米的範圍。這標準碟化的增加可以用各式各樣的方式來形成，舉例而言增加用來相容於直接混合型接合所需之CMP的量。在增加碟化的頂部上形成阻障則可以用許多方式來形成，舉例而言為鑲嵌過程，其包括在整個表面上方沉積傳導阻障(類似於圖3)，接著做CMP以從較高的介電表面17移除傳導阻障，而不從凹陷裡移除顯著量或所有的傳導阻障(圖11)。形成的阻障厚度可以相當於、大於或小於增加的碟化厚度，舉例而言小於約40奈米。在形成阻障之後，最終的阻障厚度和碟化則可以由CMP來控制。
於此具體態樣，這造成的碟化較佳而言乃相容於直接混合型接合所需者。所得表面的截面乃示意顯示於圖11，其示範基板37並且稱為 混合型接合表面18，其所具有的傳導阻障16不接觸底下的傳導阻障。阻障的形成也可以用選擇性過程來形成，舉例而言為無電鍍鎳。
具有傳導阻障16而形成如圖11所示的示意截面圖之基板38和39的二個混合型接合表面現在可以彼此做直接混合型接合，如圖12的截面所示，以形成具有傳導阻障16的直接混合型接合而無底下的傳導阻障。每個混合型接合表面是基板的表面，並且每個基板可以包含裝置和/或積體電路，使得這些裝置和/或積體電路在完成混合型接合之後可以彼此連接。具有傳導阻障的混合型接合表面可以包括連接到底下連線構件(未顯示)的通孔構件或連接到底下通孔構件(未顯示)的連線構件19。
在接合之後，在個別混合型接合表面之間典型而言有些未對齊於傳導阻障。這未對齊可以導致第一混合型接合表面上的傳導阻障16接觸基板36中之第二混合型接合表面上的介電表面17，並且導致第一混合型接合表面上的介電表面17接觸第二混合型接合表面上的傳導阻障16，如圖12的20所示。這未對齊也可以導致一混合型接合表面上的傳導阻障16接觸另一表面上的介電表面17，並且導致來自一表面之傳導阻障16的表面接觸另一混合型接合表面上之傳導阻障16的部分表面，如圖12的21所示。
儘管有這未對齊，根據本發明，在第一或第二混合型接合表面上的介電表面17接觸另一混合型接合表面上的傳導阻障16，並且在第一或第二混合型接合表面上的傳導阻障16接觸另一混合型接合表面上的傳導阻障16或介電表面17。這特色對於某些結構而言可以便於形成跨越接合介面的電連接，舉例而言當導體13是Al BEOL所建造的Al接線表面，則在相對表面上的導體13之間做出電連接要比在相對表面上的導體13之頂部上 的傳導阻障16之間做出電連接還更具挑戰性。
圖11所示的碟化量可以影響使用這些表面之後續直接混合型接合的熱預算。舉例而言，在低溫或室溫下起初直接接合相對的介電表面之後，較少的碟化可以導致需要較低的熱預算來完成混合型接合，這是因為需要較少的導體13膨脹來在相對的傳導阻障16表面之間形成金屬接合。
於根據本發明的第三具體態樣，混合型表面包括傳導貫穿矽通孔(TSV)結構23和25，如圖13~15所示。每張圖為了方便釋例而顯示二種不同的結構，其具有(25)和沒有(23)傳導阻障材料層26，該層的形成方式類似於上面圖1~4。TSV延伸穿過基板40以接觸基板41中的金屬導體4。TSV 23和25的傳導材料可以由像是Cu或W的金屬或像是多晶矽的非金屬所組成。傳導材料可以相鄰於絕緣材料24，如圖13所示；或者如包括基板42的圖14所示，可以具有插置在傳導材料和絕緣材料之間的阻障層27。
於另一範例，TSV 23和25可以具有插置在傳導材料和半導體基板43之間的絕緣阻障28，如圖15所示。TSV可以凹陷成具有增加的碟化，如第一和第二具體態樣所述，並且傳導阻障26形成在這增加的碟化裡，如第一和第二具體態樣所述，以形成具有適合直接混合型接合之碟化的混合型接合表面。這些類型的表面可以彼此做直接混合型接合，舉例而言如果TSV表面穿過CMOS結構的背部而暴露，則造成所謂背對背的直接混合型接合。也有可能使用這些混合型接合表面中的某一者來形成對於形成在CMOS結構正面上之混合型接合表面的直接混合型接合，舉例而言在Cu BEOL或Al BEOL的頂部上，以形成所謂前對背的直接混合型接合。
於本發明，BEOL通孔填充金屬可以完全由傳導阻障所包封。進一步而言，本發明允許混合型接合製作來利用介電質和傳導阻障材料而做直接混合型接合。可以改善用於直接混合型接合過程的過程窗口，而斟酌影響目前合格於CMOS BEOL半導體廠的材料和/或過程。本發明也允許降低製造商要使直接混合型接合科技合格的採行障礙、使用CMOS BEOL所用之絕緣介電質和傳導阻障材料的組合來製造直接混合型接合表面、可以提供抑制小丘形成之直接混合型接合表面的方法和結構、可以減少直接混合型接合中的熱預算。
本發明的應用包括但不限於經處理之積體電路的垂直整合，而用於3D SOC、微襯墊封裝、低成本和高效能的取代覆晶接合，晶圓級封裝、熱管理、獨特裝置結構(例如金屬基底裝置)。應用進一步包括但不限於積體電路(像是背面照明的影像感測器)、RF前端、微機電結構(micro-electrical mechanical structure，MEMS)(包括但不限於皮米投影器(pico-projector)和陀螺儀)、3D堆疊記憶體(包括但不限於混合型記憶方塊)、高頻寬記憶體、DIRAM、2.5D(包括但不限於在插置物上傾斜的FPGA)和當中使用這些電路的產品(包括但不限於行動電話和其他行動裝置、膝上型電腦、伺服器)。
鑒於以上教導，本發明可能有許多的修改和變化。因此要了解在所附的申請專利範圍裡，本發明可以不如在此特定所述的來實施。
1‧‧‧導體
2‧‧‧傳導阻障
3‧‧‧介電質
4‧‧‧金屬結構
7‧‧‧傳導阻障
30、32‧‧‧基板

Claims (24)

  1. 一種形成元件的經建構以接觸另一元件之直接混合型接合表面的方法，其包括：在第一基板的上表面中形成多個第一金屬接觸結構，其中所述結構的頂面是在該上表面之下；在該上表面和所述多個金屬接觸結構上方形成傳導阻障材料做的第一層，所述傳導阻障材料做的該第一層包含在所述上表面上方的第一接觸部分和在所述多個金屬接觸結構上方的第二接觸部分；以及從該上表面移除傳導阻障材料做的該第一層以留下所述傳導阻障材料做的該第一層的所述第二接觸部分於所述多個金屬接觸結構上並且經建構以形成所述直接混合型接合表面，所述傳導阻障材料做的該第一層的所述第二接觸部分包含配置於所述上表面之下的接觸表面。
  2. 根據申請專利範圍第1項的方法，其中，在所述移除之後，所述多個金屬接觸結構上之該傳導阻障材料的接觸表面是在該基板的該上表面之下小於20奈米。
  3. 根據申請專利範圍第1項的方法，其中，在所述移除之後，所述多個金屬接觸結構上之該傳導阻障材料的接觸表面是在該基板的該上表面之下約1~10奈米的範圍。
  4. 根據申請專利範圍第1項的方法，其包括：在該上表面之下約5~40奈米形成所述多個金屬接觸結構的該頂面，其中，在所述移除之後，所述多個金屬接觸結構上之該傳導阻障材料的接觸表面是在該上表面之下1~10奈米。
  5. 根據申請專利範圍第1項的方法，其包括：在所述金屬接觸結構的底部和側面上形成傳導阻障材料做的第二層。
  6. 根據申請專利範圍第5項的方法，其包括：形成傳導阻障材料做的所述第一和第二層以完全包圍所述金屬接觸結構。
  7. 根據申請專利範圍第1項的方法，其包括：在該基板上的介電層中形成所述金屬接觸結構。
  8. 一種接合基板的方法，其包括：在個別的第一和第二元件的第一和第二基板的個別上表面中形成多個第一和第二金屬接觸結構，其中所述多個第一金屬接觸結構的第一頂面是在該第一基板的該上表面之下，並且所述多個第二金屬接觸結構的第二頂面是在該第二基板的該上表面之下；在所述個別上表面和所述第一和第二多個金屬接觸結構及所述第一和第二基板上方形成傳導阻障材料做的個別的第一層，所述傳導阻障材料做的個別的所述第一層包含在所述第一和第二基板的所述個別上表面上方的個別第一接觸部分；從所述第一和第二基板的所述上表面移除傳導阻障材料做的所述第一層的所述第一接觸部分，以在所述多個第一和第二金屬接觸結構上留下該傳導阻障材料的個別的第二接觸部分，所述傳導阻障材料做的所述第一層的所述第二接觸部分包含配置於所述個別上表面之下的接觸表面；將所述第一基板的該上表面直接接合到所述第二基板的該上表面；以及 將在所述第一和第二多個金屬接觸結構上的所述傳導阻障材料的個別的所述第二接觸部分直接接合。
  9. 根據申請專利範圍第8項的方法，其包括：在所述第一和第二基板的所述上表面之下約5~40奈米分別形成所述第一和第二頂面，其中，在所述移除之後，所述多個第一和第二金屬接觸結構上之該傳導阻障材料的頂面分別是在所述第一和第二上表面之下1~10奈米。
  10. 根據申請專利範圍第8項的方法，其包括：在所述多個第一和第二金屬接觸結構的底部和側面上形成傳導阻障材料做的個別的第二層。
  11. 根據申請專利範圍第10項的方法，其包括：形成傳導阻障材料做的所述第一和第二層以完全包圍所述金屬接觸結構。
  12. 根據申請專利範圍第8項的方法，其包括：在所述第一和第二基板上的個別介電層中形成所述多個第一和第二金屬接觸結構。
  13. 根據申請專利範圍第8項的方法，其包括：移除傳導阻障材料做的該第一層，使得所述多個金屬接觸結構上之該傳導阻障材料的頂面分別是在所述第一和第二基板的所述上表面之下小於20奈米。
  14. 根據申請專利範圍第8項的方法，其包括：移除傳導阻障材料做的個別的該第一層，使得所述第一和第二多個金 屬接觸結構上之該傳導阻障材料的頂面分別是在所述第一和第二基板的所述上表面之下約1~10奈米的範圍。
  15. 一種經建構以直接接合到另一結構而不需要中介黏著劑的結構，其包括：基板的直接混合型接合表面，所述直接混合型接合表面包括：介電層，其具有經拋光的上表面，傳導接觸結構，以及第一傳導阻障材料層，其直接形成在所述傳導接觸結構之每一者的上表面上，其中該第一傳導阻障層的接觸表面是凹陷在該介電層的該經拋光的上表面下方，所述接觸表面經建構以接觸且直接接合到另一個結構的元件。
  16. 根據申請專利範圍第15項的結構，其中，所述傳導接觸結構的所述上表面是在所述介電層的該經拋光的上表面之下約5~40奈米。
  17. 根據申請專利範圍第15項的結構，其包括：傳導阻障材料做的第二層，其在每個所述傳導接觸結構的底部和側面上。
  18. 根據申請專利範圍第17項的結構，其中：傳導阻障材料做的所述第一和第二層完全包圍所述傳導接觸結構。
  19. 根據申請專利範圍第15項的結構，其中：所述第一傳導阻障材料層的所述接觸表面凹陷在該介電層的該經拋光的上表面下方約一到十奈米。
  20. 一種接合結構，其包括： 在個別的第一和第二元件上的第一和第二直接混合型接合表面，所述第一和第二直接混合型接合表面中的每一者包括：介電層，傳導接觸結構，以及第一傳導阻障材料層，其直接形成在所述傳導接觸結構之每一者的上表面上，所述第一傳導阻障材料層包含接觸表面，其中所述傳導阻障材料層被設置於每個所述第一和第二直接混合型接合表面的所述傳導接觸結構的所述上表面之間，以及所述第一和第二直接混合型接合表面中的所述介電層乃彼此直接接觸並且彼此直接接合，並且所述第一和第二直接混合型接合表面中的所述傳導阻障材料層的所述接觸表面是彼此直接接觸以及彼此直接接合。
  21. 根據申請專利範圍第20項的結構，其包括：第二傳導阻障材料層，其配置在所述傳導接觸結構的底部和側面上。
  22. 根據申請專利範圍第21項的結構，其中：所述第一和第二傳導阻障材料層完全包圍所述傳導接觸結構。
  23. 根據申請專利範圍第20項的結構，其中所述介電層被設置為圍繞所述第一傳導阻障材料層。
  24. 根據申請專利範圍第21項的結構，其中在所述傳導接觸結構的所述側面上的所述第二傳導阻障材料層被設置為沿著所述導電結構的周邊的至少一部分，所述導電結構的周邊不平行地延伸到所述介電層的接合表面。
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