CN114944376A - 传导阻障直接混合型接合 - Google Patents

传导阻障直接混合型接合 Download PDF

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Publication number
CN114944376A
CN114944376A CN202210544308.7A CN202210544308A CN114944376A CN 114944376 A CN114944376 A CN 114944376A CN 202210544308 A CN202210544308 A CN 202210544308A CN 114944376 A CN114944376 A CN 114944376A
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Prior art keywords
conductive
layer
dielectric layer
contact
barrier
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CN202210544308.7A
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保罗·M·恩奎斯特
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Adeia Semiconductor Bonding Technologies Inc
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Invensas Bonding Technologies Inc
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Publication of CN114944376A publication Critical patent/CN114944376A/zh
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Abstract

本发明提供一种传导阻障直接混合型接合，接合结构包括第一组件，第一组件包括：具有第一抛光接触面的第一介电层；形成于第一介电层的一部分中的第一传导接触结构；第二组件，直接接合到第一组件而没有插入黏着剂，包括：第二介电层，具有与第一抛光接触面接触且直接接合的第二抛光接触面；第二传导接触结构；传导阻障材料层，具有第一部分，第一部分至少设置在第一传导接触结构和第二传导接触结构之间，第一部分接触第一介电层和第二介电层，该第一部分直接接触第一传导接触结构的上表面和/或第二传导接触结构的上表面，第一介电层、第二介电层、第一传导接触结构、第二传导接触结构以及传导阻障材料层形成直接混合型接合件的部分。

Description

传导阻障直接混合型接合
本申请为申请日2016年08月25日、申请号201680048737.8、发明创造名称“传导阻障直接混合型接合”的分案申请。
技术领域
本发明关于直接接合的领域，更特定而言关于混合型直接接合(较佳而言在室温或低温)；更特别而言关于半导体材料、装置或电路的接合，而要用于堆栈半导体装置和集成电路制作；甚至更特别而言关于制作消费者和商业产品中的附加价值零件，包括移动电话中的影像传感器、移动电话中的射频(RF)前端、高效能图形产品中的三维(threedimensional，3D)内存、服务器中的3D内存。
背景技术
对于以较小形式因素、较低成本来增加功能性的持续要求而言，晶粒、芯片或晶圆堆栈已经变成工业标准实务。一般而言，堆栈可以随着堆栈诸层之间的电互连来做，而形成作为堆栈过程的一部分或在堆栈过程之后。在堆栈过程之后所形成的电互连的范例使用贯穿硅通孔(through silicon via，TSV)蚀刻，并且填充穿过堆栈中的一层而到堆栈中的相邻层里，以在堆栈的诸层之间做出电互连。形成作为堆栈过程的一部分的这些三维(3D)电互连的范例包括焊料凸块和铜柱(其具有或没有底填)、混合型接合、直接混合型接合。将3D电互连实现成堆栈过程的一部分则就许多原因来说是有利的，包括但不限于免除TSV(贯穿硅通孔)科技的成本和专属需求。直接混合型接合也称为直接接合互连(direct bondinginterconnect，
Figure BDA0003649266560000011
)，则就许多原因来说要比其他形式的堆栈来得有利，包括但不限于在金属和介电表面构件上方有平坦的接合(其在低温下提供高强度)以及能够做到尺度达次微米的3D互连间距。
用于直接混合型接合的金属和介电表面构件可以由金属和介电质的各式各样组合所组成，其以各式各样的制作技术而形成各式各样的图案。金属的非限制性范例包括铜、镍、钨、铝。举例而言见：P.Enquist的「用于三维集成电路应用的高密度直接接合互连(DBITM)科技」，材料研究协会研讨会议事录，第970册，2007年，第13～24页；P.Gueguen等人的「铜直接接合做的3D垂直互连」，材料研究协会研讨会议事录，第1112册，2009年，第81页；P.Enquist的「直接接合互连
Figure BDA0003649266560000021
作为三维整合架构和应用的大量商业化的驱动器所拥有的缩放性和低成本优点」，材料研究协会研讨会议事录，第1112册，2009年，第81页；DiCioccio等人的「归功于钨直接接合的垂直金属互连」，第60届ECTC的2010年议事录，第1359～1363页；H.Lin等人的「使用低温晶圆接合的直接Al–Al接触来整合MEMS和CMOS装置」，微电子工程，第85期(2008年)，第1059～1061页。介电质的非限制性范例包括氧化硅、氮化硅、氧氮化硅、氮化硅碳。举例而言见：P.Enquist的「3D科技平台——先进的直接接合科技」，C.S.Tan、K.N.Chen、S.J.Koester(编辑者)，「用于VLSI系统的3D整合」，Pan Stanford，ISBN978-981-4303-81-1，2011年；J.A.Ruan、S.K.Ajmera、C.Jin、A.J.Reddy、T.S.Kim的「在蚀刻停止层和介电层之间具有改善附着和减少起泡的半导体装置」，美国专利第7732324B2号。各式各样图案的非限制性范例包括通孔数组或金属线和空间的数组，举例而言如在互补式金属氧化物半导体(CMOS)生产线后端(back-end-of-line，BEOL)互连制作中的通孔和接线层所发现的。以这些范例来说，3D电互连可以通过金属通孔对金属通孔、金属通孔对金属线、或金属线对金属线的对齐和接合而形成。建造适合混合型接合的表面的制作技术的非限制性范例是工业标准的单一和双重镶嵌过程，其若有需要的话则加以调整以满足适合的拓扑规格。
基本上有二种CMOS BEOL制程。一种典型而言称为铝(Al)BEOL，另一种称为铜(Cu)BEOL。于Al BEOL过程，具有适合的传导阻障层的Al典型而言使用作为接线层，并且具有适合的传导阻障层的钨(W)则用于通孔层以在二相邻Al接线层之间做电互连。Al接线层典型而言被干式蚀刻，后续以介电质沉积来平坦化，接着再做化学机械抛光(chemo-mechanicalpolishing，CMP)。W通孔层典型而言是以单一镶嵌过程所形成，其由以下所组成：介电质沉积、通孔图案化和蚀刻到先前的接线层、通过物理气相沉积和W化学气相沉积而以传导阻障层来填充通孔、并且做W和传导阻障层的CMP以隔离介电基质里的W通孔或栓塞。于Cu BEOL过程，具有适合的传导阻障层的Cu典型而言使用作为接线和通孔层。Cu接线和通孔层典型而言是以双重镶嵌过程所形成，其由以下所组成：介电质沉积、通孔图案化和蚀刻部分穿过介电层、接着做接线图案化(其重迭着通孔图案化)并且同时继续蚀刻(多个)通孔到先前的接线层，其中接线重迭着部分蚀刻的通孔，并且蚀刻出用于接线的沟槽，其连接到先前具有通孔的接线层。替代性的双重镶嵌过程是由以下所组成：介电质沉积、接线图案化和蚀刻部分穿过介电层(其在到达先前的接线层则停止)、通孔图案化和蚀刻到先前的接线层，其中通孔是在部分蚀刻的接线里，并且蚀刻完成了通孔蚀刻到先前的接线层。任一双重蚀刻表面然后填充了传导阻障层(举例而言通过物理气相沉积来为之)，接着再做Cu填充(举例而言通过电镀或物理气相沉积加电镀来为之)，最后做Cu和传导阻障层的CMP以隔离介电基质里的Cu接线。
使用上述工业标准的W或Cu镶嵌流程则可以用来形成用于混合型接合的表面，而接受适合的表面拓扑，举例而言如上所提供。然而，当这些表面用于混合型接合时，典型而言在一表面上的金属和在另一表面上的介电质之间将有异质接合构件，举例而言这是由于通孔表面未对齐的缘故。这可以导致来自一接合表面的通孔填充材料直接接触来自另一接合表面的介电质，而没有插入传导阻障(其在Cu或W填充通孔和包围介电质之间的其他地方)。
较佳的是具有用于直接混合型接合过程科技的低热预算的宽制程窗口，而斟酌影响目前合格于CMOS BEOL半导体厂的材料和过程，以降低使直接混合型接合过程合格于该半导体厂的实行障碍。Cu BEOL过程是此种较佳能力的范例，因为Cu镶嵌过程已经是多年的工业标准，并且Cu直接混合型接合科技能够斟酌影响这基础架构。斟酌影响Al BEOL工业标准过程已经是比较具挑战性的，因为此过程中的二种主要金属W和Al由于包括高降伏强度、热膨胀系数(coefficient of thermal expansion，CTE)、原生氧化物、小丘形成等因素的组合而对于发展W或Al的直接混合型接合科技来说是比较具挑战性的材料。
发明内容
本发明的具体态样针对形成直接混合型接合表面的方法，其包括：在第一基板的上表面中形成多个第一金属接触结构，其中所述结构的顶面是在该上表面之下；在该上表面和所述多个金属接触结构上方形成传导阻障材料做的第一层；以及从该上表面移除传导阻障材料做的该第一层。
附图说明
当关于伴随图示来考虑而参考以下详细叙述时，由于更加了解则将轻易获得对本发明的更完整体会和其达成的许多优点，其中：
图1是单一或双重镶嵌过程所形成的传导层的靠近表面区域的示意截面图，其具有填充的通孔和/或接线，而在填充的通孔和/或接线与包围介电质之间则有传导阻障；
图2是图1在从包围介电质的表面移除传导层之后的示意截面图；
图3是图2在形成传导阻障材料层之后的示意截面图；
图4是图3在从包围介电质的表面移除传导阻障层材料层之后的示意截面图；
图5是二个混合型直接接合表面正在接合的示意图；
图6是二个混合型直接接合表面在接触个别的介电层之后的示意图；
图7是二个混合型直接接合表面已直接接合的示意图；
图8是传导阻障材料的上表面因为碟化而弯曲的示意图；
图9是根据本发明的一对基板的示意图，其中类似的通孔结构未对齐于传导阻障，并且通孔对齐于针对具有传导阻障的接线结构的传导阻障；
图10是表面的靠近表面区域的示意截面图，该表面由图案化的金属层所组成，其以包围介电质加以平坦化，而平坦化暴露图案化的金属层，在金属层和包围介电质的侧向之间没有传导阻障层；
图11是图10的示意截面图，其中图案化的金属层的暴露表面的传导部分根据本发明而覆盖了传导阻障金属；
图12是根据本发明的一对接触基板的示意图，其举的例子是在金属层和包围介电质的侧向之间没有传导阻障下将没有对于接线结构的传导阻障的接线结构加以对齐；
图13是本发明的另一具体态样的示意图，其具有贯穿硅通孔结构；
图14是图13的结构的示意图，其具有第二传导阻障材料层；以及
图15是本发明的另一具体态样的示意图，其具有贯穿硅通孔结构而在侧壁上具有介电层。
具体实施方式
现在参见图式，其中全篇相同的参考数字指称相同或对应的零件，并且特别参见图1，其显示在根据本发明的直接混合型接合过程中的基板30的表面的截面，其由导体1、传导阻障2、介电质3、金属结构4所组成。金属结构4形成在介电质3中。金属结构4位于介电质3里，并且可以是接触、衬垫、线或其他金属互连结构。开口形成在金属结构4上方的介电质3中，接着形成传导阻障2和导体1。导体1、传导阻障2、金属结构4的尺寸和厚度并未按照比例，而是为了示范本发明所绘制。虽然开口和金属结构显示成有相同的尺寸和形状，不过它们的尺寸和形状可以有所不同，此视设计或需要而定。
用于导体1的可能是各式各样的金属，包括但不限于Cu和W，其分别常见于Cu和AlBEOL半导体厂。Cu可以通过物理气相沉积(physical vapor deposition，PVD)或电镀(electroplating，EP)而沉积，并且W可以通过化学气相沉积(chemical vapordeposition，CVD)而沉积。用于传导阻障材料2的也可能是各式各样的传导阻障，其常见于Cu和Al BEOL半导体厂。Cu BEOL过程中的传导阻障包括钽(Ta)、氮化钛(TiN)、氮化钽(TaN)、氮化钨(WN)、氧化钌(RuO2)、氮化钽硅(TaSiN)、氮化钛硅(TiSiN)、氮化钨硼(TBN)、硼化钴钨(CoWB)、磷化钴钨或其组合(举例而言为Ti/TiN和Ta/TaN)，其可以通过各式各样的技术来沉积，包括PVD、CVD、金属有机CVD(metal organic CVD，MOCVD)。有各式各样的PVD技术可用，包括直流(DC)磁控溅镀、准直溅镀、离子化金属电浆(ionized metal plasma，IMP)。Al BEOL过程中的传导阻障包括Ti/TiN。其他材料也有可能作为阻障，举例而言为镍(Ni)。
也可能有各式各样的介电质，包括但不限于氧化硅、氮化硅、碳氮化硅，其常见于Cu和Al BEOL半导体厂。生成图1截面所述表面的常见方法是上述的镶嵌过程。
图1的上表面接受CMP以移除介电质3的顶部上的部分的导体1和传导阻障2。图2示范在CMP之后的结构。导体1和传导阻障2相对于介电质3的相对高度可以通过镶嵌过程的CMP部分来控制。
导体1和传导阻障2相对于介电质3的高度则有许多组态。导体1和阻障2的顶面可以在介电质3的表面之下、甚至之中、名义上甚至之中或之上。一般而言，直接混合型接合有可能具有所有的组态。然而，较佳的组态则是导体1和传导阻障2的相对高度是在介电质3之下的距离t1。这组态有助于形成无空洞的接合接口，并且对于跨越接合表面的相对高度变化而言是更可制造的。对于最适合直接混合型接合的表面来说，跨越传导层的接合表面而在介电质3之下的相对高度变化的范例是在介电质3之下一到十奈米，虽然也可能有较小和较大的变化。这凹陷典型而言称为碟化(dishing)。所得表面称为没有传导阻障2的混合型接合表面。
兼容于混合型接合的典型碟化量是0到20奈米，其称为标准碟化。标准碟化的增加量相当于图4所示的后续传导阻障7(其形成在图2所示这增加碟化形成开口5的顶部上)的厚度，所导致的碟化则相当于标准碟化并且兼容于直接混合型接合所要的。标准碟化增加的范例是5～20奈米，导致约5～40奈米的总碟化t1。这标准碟化的增加可以用各式各样的方式来形成，举例而言增加用来生成标准碟化的CMP直到达成所要的增加碟化为止。这CMP的增加可以由CMP时间的增加来完成，该时间量可以由常规的校正所决定，并且可以是CMP衬垫、浆液、向下力、承载器和桌台旋转、混合型表面上的导体和介电质的图案等的函数。
如图3所示，传导阻障金属层6形成在结构上方而在图2所示的介电质表面31上。阻障6的材料可以相同或不同于传导阻障2。增加碟化之后在导体1的顶部上形成阻障6则可以用许多方式来形成，举例而言为镶嵌过程，其包括在整个表面上方沉积传导阻障，接着做CMP以从较高的介电表面移除传导阻障，而不从凹陷里移除层6的显著量或所有的传导阻障材料。阻障的形成也可以用选择性过程来形成，举例而言为无电镀镍。所得结构在导体1和传导阻障2的顶部上的每个开口5中具有传导阻障7。这所得的碟化较佳而言兼容于直接混合型接合所需者，亦即传导阻障7的表面是在介电质3的表面之下小于20奈米，较佳而言为1～10奈米。图4示意所示的所得表面的截面称为具有传导阻障7的混合型接合表面。
层6的厚度可以小于导体1/阻障2的碟化量，如图3所示，或者可以相同或厚于这碟化量。于前者情形，仅从凹陷移除部分的层6或不移除。于层6相同或厚于凹陷量的情形，层6通过CMP而从凹陷里移除。层6在所有情形下被移除，如此则所得的碟化在形成阻障7中小于20奈米，较佳而言1～10奈米。
基板30的每个混合型接合表面可以包含装置和/或集成电路(未显示)，使得这些装置和/或集成电路在完成混合型接合之后可以彼此连接。装置和电路可以包含金属结构4，或者可以经由未示范的进一步的互连结构而连接到金属结构4。
皆具有传导阻障7而有例如图4所示的示意截面的基板30和32的二个混合型接合表面现在可以彼此做直接混合型接合，如图5和6的截面所示，以形成直接混合型接合12。将基板30和32对齐(图5)并且放置成直接接触，使得基板30和32中的介电层3彼此接触(图6)。对齐和接触可以在室温下进行，而在室内气氛或真空下。虽然图式示意显示在基板30和32的阻障7之间有间隙，但是在对齐和接触之后，阻障7之间可以有部分或显著的接触。虽然一对一的连接安排显示于图6，不过可能有其他的安排，例如一基板中的多个金属结构接合于另一基板中的单一金属结构。
基板30和32的介电表面较佳而言如美国专利申请案第09/505,283、10/359,608、11/201,321号所述的制备。简言之，表面可加以蚀刻、抛光、活化和/或终端有所要的接合物种，以促进和提升基板30和32上的介电质3之间的化学接合。制造出粗糙度方均根为0.1到3奈米的介电质3的平滑表面，其经由湿式或干式过程来活化和/或终端化。
随着基板表面在室温接触，基板表面的介电质3开始在一或多个接触点形成接合，并且晶圆之间的吸引接合力随着化学接合面积增加而增加。这接触可以包括阻障7或不包括阻障7。如果接触包括阻障7，则介电质3中的基板对基板化学接合所产生的压力导致有使阻障7的接触区域强烈结合的力，并且基板30和32中的介电质3之间的化学接合在二个不同晶圆上的金属衬垫之间产生电连接。
阻障7抵靠着彼此的内部压力(源自基板30和32的介电质3之间的接合)可能不适合达成较佳而言具有低电阻的电连接，举例而言这是由于原生氧化物或其他污染(举例而言为烃)的缘故。改善的接合或较佳而言为较低电阻的电连接可以通过移除阻障7上的原生氧化物来达成。举例而言，可以使用稀释的氢氟酸来清洁表面；或者在移除原生氧化物之后直到进行接合为止，基板30和32的表面可以暴露于惰性气氛，举例而言为氮或氩。
内部压力也可能不足以使阻障7的足够表面彼此接触。替代或附带而言，阻障7之间的改善接合或较佳而言为较低电阻的电连接可以通过加热来达成。加热的范例包括范围在100～400℃的温度、在10分钟和2小时之间的时间，此视用于接触结构4、阻障6、导体1的材料而定。有可能对于给定的材料组合做时间和温度的优化。举例而言，较短的加热时间可能可以有较高的温度，并且较低的温度可能可以有较长的加热时间。加热时间可以减到最少和/或加热温度可以减到最少的程度则将取决于特定的结构和材料组合，并且可以由常见的制程优化实务来决定。举例而言，如果阻障7是镍，则300℃的温度达二小时或者350℃的温度达15分钟可以是足以改善接合和改善电连接。也可能有较高和较低的温度和/或时间，此视阻障7的材料和阻障7底下的其他材料而定。温度增加可以通过减少原生氧化物或其他污染或者通过增加阻障7之间的内部压力(因为导体1和阻障7的热膨胀)而导致较佳而言为低电阻的电连接。材料4和在材料4之下的其他材料(未示范)也可以增加在阻障7底下的结构热膨胀，并且对应的增加相对阻障7之间的压力。举例而言，如果材料4是具有关联的CTE和杨氏模数的铝，则相较于具有较低CTE和/或杨氏模数的替代性材料4可以产生较高的压力。加热也可以增加阻障7之间的交互扩散以产生较佳的较低电阻电连接。
如果基板30和32的介电质3之间的起初接合不包括阻障7，则可以使用加热以导致阻障7之间的接触，因为阻障7的CTE高于介电质3。加热或温度上升的量则取决于阻障7之间的分离、阻障7和导体1和金属结构4的厚度、CTE、杨氏模数，因为对于给定的温度上升来说，这些参数影响相对阻障7之间的压力。举例而言，相较于20奈米的分离，使阻障7之间的分离减到最小(举例而言小于10奈米)则可以减少加热。举进一步范例来说，阻障7和/或导体1的高度或厚度将增加压力，因为阻障7和导体1的热膨胀将随着厚度而增加。举例而言，阻障7和导体1的典型膨胀增加是与厚度成正比。举进一步范例来说，具有较高杨氏模数的导体1预期要比具有较低杨氏模数的替代性导体1产生更高的压力，因为较高杨氏模数的材料在当产生压力时较不可能降伏。具有较低杨氏模数的阻障7可以不需要像它可以通过在较低压力下降伏而便于形成连接的那么多的加热。当基板30和32的表面起初接触时，如果阻障7不是紧密接触，则在加热之后，导体1和阻障7的热膨胀因此导致有紧密接触的低电阻连接，如图7所示。
虽然导体1/阻障2和阻障7的表面在上面的范例中显示成平坦的，不过该一或二者由于CMP过程的缘故而可以具有某些弯曲。轮廓显示于图8，其中二者都具有弯曲。于图8，显示的基板33具有阻障7和导体1/阻障2，其表面有所变化。阻障7的厚度较佳而言是够厚以容纳导体1的粗糙度的涵盖范围，但不是太厚而使制作变得复杂。典型的厚度范围可以是5～20奈米。阻障在弯曲的中间和边缘的相对厚度可以较厚或较薄，此视在阻障7沉积在导体1之前的接触1表面形成的弯曲和阻障7形成的弯曲而定，举例而言这是因为用来形成接触1的表面的CMP过程和用来形成阻障7的表面的CMP过程有不同的特征的缘故。阻障7的中央凹陷在介电质3的表面之下小于20奈米，较佳而言为1～10奈米。
图9示范具有混合型接合表面的二个基板34和35的上部。具有传导阻障的混合型接合表面可以包括通孔构件8，其连接到底下的联机构件(未显示)；或者包括联机构件9，其连接到底下的通孔构件(未显示)。在接合之后，在个别混合型接合表面之间典型而言有些未对齐于传导阻障。这未对齐可以导致第一混合型接合表面上的传导阻障7接触第二混合型接合表面上的介电表面31，以及导致第一混合型接合表面上的介电表面31接触第二混合型接合表面上的传导阻障7，如图9的10所示。这未对齐也可以导致一混合型接合表面上的传导阻障7接触另一表面上的介电表面31，以及导致来自一表面的传导阻障7的整个表面接触另一混合型接合表面上的传导阻障7的部分表面，如图9的11所示。
尽管有这未对齐，根据本发明，第一或第二混合型接合表面上的介电质3的表面接触另一混合型接合表面上的传导阻障7，并且在第一或第二混合型接合表面上的传导阻障7接触另一混合型接合表面上的传导阻障7或介电质3的表面。尽管未对齐，导体1的顶部上的传导阻障7因此避免导体2和介电质3之间有所接触。举例而言当Cu使用作为导体1而具有CuBEOL所建造的Cu单一或双重镶嵌直接混合型接合表面，本发明的这特色可以改善直接混合型接合的可靠度，举例而言对于考虑如果Cu直接接触介电质3则Cu会扩散到介电质3里的应用来说便是如此。该特色对于某些结构来说也可以便于跨越接合接口而形成电连接，举例而言，当导体1是Al BEOL所建造的W栓塞单一镶嵌直接混合型接合表面，则在相对表面上的导体1之间做出电连接要比在相对表面上的导体1的顶部上的传导阻障7之间做出电连接还更有挑战性。
图2所示的碟化量可以影响使用这些表面而具有凹陷传导部分的后续直接混合型接合的热预算。举例而言，在将直接混合型接合表面起初放置成直接接触之后，介电部分可以呈直接接触，并且所有或某些的凹陷传导部分可以因为凹陷而不直接接触。加热具有凹陷传导部分的这些直接混合型接合表面可以导致凹陷传导部分膨胀，如此则它们在高于直接混合型接合表面被带去接触的温度下，甚至在更高的温度下，被带去直接接触，并且产生显著压力以便于相对凹陷传导部分之间有电连接。这些更高的温度可以便于在相对的凹陷传导部分之间形成电互连并且完成直接混合型接合。将凹陷部分带去直接接触并且产生显著压力以便于相对凹陷传导部分之间有电连接所需的温度则是传导材料、传导材料上的残余或原生氧化物、传导材料的降伏强度、传导材料的碟化或凹陷等的组合。举例而言，较少的碟化可以导致在低温或室温下起初直接接合相对介电表面之后需要较低的热预算来完成混合型接合，这是因为需要较少的导体1和传导阻障7的膨胀以在相对传导阻障7的表面之间形成金属接合。
举例而言，当使用Ni作为传导阻障时，可以通过加热到约350℃而容纳10奈米的凹陷；相较而言，如果使用铜而无覆盖传导阻障，则约200℃便可以是足够的。为了减少热预算，一般来说使用较高CTE(热膨胀系数)的材料而具有较低降伏强度和较少的碟化则是有用的。一般而言，CTE和降伏强度是由选择的阻障所给定，并且碟化是可变的，其可加以变化来达成适合的热预算。热预算也可以受到在导体底下的材料的影响。举例而言，在导体1底下而具有较高CTE(亦即每℃高于15ppm)的导体1(举例而言为金属结构4，如图4所示)要形成混合型接合电连接所具有的热预算可以低于具有较低CTE的导体1和/或金属结构4。每℃高于15ppm的高CTE金属的范例包括Cu和Al，其是常见于Al和Cu BEOL过程中的导体。
于根据本发明的第二具体态样，由介电部分14所包围的传导部分13则包括在基板36中的直接混合型接合表面15，如图10所示。传导部分13的范例是铝，并且介电部分14的范例是层间介电质，其范例为用于Al BEOL的氧化硅和其他介电质，其用于Al BEOL的典型材料的范例。金属部分13可以包括通孔和/或接线图案，其连接到底下的互连层。介电部分14可以是连续邻接的，举例而言如果传导部分仅由通孔所组成的话；或者介电部分14可以不是连续邻接的，举例而言如果传导部分是由接线图案所分开的话。于此具体态样，直接混合型接合表面15较佳而言具有在直接混合型接合规格里的碟化传导部分。这表面可以通过Al金属化、介电质沉积、CMP平坦化的组合而形成，以形成具有图10所示截面的表面。Al金属化可以包括在顶部上的传导阻障，举例而言为Ti。如果有传导阻障并且它通过CMP平坦化而移除，则表面将具有图10所示的截面。如果传导阻障是够厚以致它未被CMP平坦化所整个移除，并且有适合的碟化t2(举例而言为用于混合型接合的混合型接合表面有0～20奈米的传导阻障部分)，则这表面(譬如图11所示)可以适合直接混合型接合，而不必额外的传导阻障沉积和CMP。
图10所述的碟化t2所增加的量则相当于后续传导阻障16(其形成在这增加的碟化的顶部上)的厚度，而导致相当于图10并且兼容于直接混合型接合(图10)所需的碟化。这厚度的增加是在约5～20奈米的范围。这标准碟化的增加可以用各式各样的方式来形成，举例而言增加用来兼容于直接混合型接合所需的CMP的量。在增加碟化的顶部上形成阻障则可以用许多方式来形成，举例而言为镶嵌过程，其包括在整个表面上方沉积传导阻障(类似于图3)，接着做CMP以从较高的介电表面17移除传导阻障，而不从凹陷里移除显著量或所有的传导阻障(图11)。形成的阻障厚度可以相当于、大于或小于增加的碟化厚度，举例而言小于约40奈米。在形成阻障之后，最终的阻障厚度和碟化则可以由CMP来控制。
于此具体态样，这造成的碟化较佳而言兼容于直接混合型接合所需者。所得表面的截面示意显示于图11，其示范基板37并且称为混合型接合表面18，其所具有的传导阻障16不接触底下的传导阻障。阻障的形成也可以用选择性过程来形成，举例而言为无电镀镍。
具有传导阻障16而形成如图11所示的示意截面图的基板38和39的二个混合型接合表面现在可以彼此做直接混合型接合，如图12的截面所示，以形成具有传导阻障16的直接混合型接合而无底下的传导阻障。每个混合型接合表面是基板的表面，并且每个基板可以包含装置和/或集成电路，使得这些装置和/或集成电路在完成混合型接合之后可以彼此连接。具有传导阻障的混合型接合表面可以包括连接到底下联机构件(未显示)的通孔构件或连接到底下通孔构件(未显示)的联机构件19。
在接合之后，在个别混合型接合表面之间典型而言有些未对齐于传导阻障。这未对齐可以导致第一混合型接合表面上的传导阻障16接触基板36中的第二混合型接合表面上的介电表面17，并且导致第一混合型接合表面上的介电表面17接触第二混合型接合表面上的传导阻障16，如图12的20所示。这未对齐也可以导致一混合型接合表面上的传导阻障16接触另一表面上的介电表面17，并且导致来自一表面的传导阻障16的表面接触另一混合型接合表面上的传导阻障16的部分表面，如图12的21所示。
尽管有这未对齐，根据本发明，在第一或第二混合型接合表面上的介电表面17接触另一混合型接合表面上的传导阻障16，并且在第一或第二混合型接合表面上的传导阻障16接触另一混合型接合表面上的传导阻障16或介电表面17。这特色对于某些结构而言可以便于形成跨越接合接口的电连接，举例而言当导体13是Al BEOL所建造的Al接线表面，则在相对表面上的导体13之间做出电连接要比在相对表面上的导体13的顶部上的传导阻障16之间做出电连接还更具挑战性。
图11所示的碟化量可以影响使用这些表面的后续直接混合型接合的热预算。举例而言，在低温或室温下起初直接接合相对的介电表面之后，较少的碟化可以导致需要较低的热预算来完成混合型接合，这是因为需要较少的导体13膨胀来在相对的传导阻障16表面之间形成金属接合。
于根据本发明的第三具体态样，混合型表面包括传导贯穿硅通孔(TSV)结构23和25，如图13～15所示。每张图为了方便释例而显示二种不同的结构，其具有(25)和没有(23)传导阻障材料层26，该层的形成方式类似于上面图1～4。TSV延伸穿过基板40以接触基板41中的金属导体4。TSV 23和25的传导材料可以由像是Cu或W的金属或像是多晶硅的非金属所组成。传导材料可以相邻于绝缘材料24，如图13所示；或者如包括基板42的图14所示，可以具有插置在传导材料和绝缘材料之间的阻障层27。
于另一范例，TSV 23和25可以具有插置在传导材料和半导体基板43之间的绝缘阻障28，如图15所示。TSV可以凹陷成具有增加的碟化，如第一和第二具体态样所述，并且传导阻障26形成在这增加的碟化里，如第一和第二具体态样所述，以形成具有适合直接混合型接合的碟化的混合型接合表面。这些类型的表面可以彼此做直接混合型接合，举例而言如果TSV表面穿过CMOS结构的背部而暴露，则造成所谓背对背的直接混合型接合。也有可能使用这些混合型接合表面中的某一个来形成对于形成在CMOS结构正面上的混合型接合表面的直接混合型接合，举例而言在Cu BEOL或Al BEOL的顶部上，以形成所谓前对背的直接混合型接合。
于本发明，BEOL通孔填充金属可以完全由传导阻障所包封。进一步而言，本发明允许混合型接合制作来利用介电质和传导阻障材料而做直接混合型接合。可以改善用于直接混合型接合过程的过程窗口，而斟酌影响目前合格于CMOS BEOL半导体厂的材料和/或过程。本发明也允许降低制造商要使直接混合型接合科技合格的实行障碍、使用CMOS BEOL所用的绝缘介电质和传导阻障材料的组合来制造直接混合型接合表面、可以提供抑制小丘形成的直接混合型接合表面的方法和结构、可以减少直接混合型接合中的热预算。
本发明的应用包括但不限于经处理的集成电路的垂直整合，而用于3DSOC、微衬垫封装、低成本和高效能的取代覆晶接合，晶圆级封装、热管理、独特装置结构(例如金属基底装置)。应用进一步包括但不限于集成电路(像是背面照明的影像传感器)、RF前端、微机电结构(micro-electrical mechanical structure，MEMS)(包括但不限于皮米投影器(pico-projector)和陀螺仪)、3D堆栈内存(包括但不限于混合型记忆方块)、高带宽内存、DIRAM、2.5D(包括但不限于在插置物上倾斜的FPGA)和当中使用这些电路的产品(包括但不限于移动电话和其他行动装置、膝上型计算机、服务器)。
鉴于以上教导，本发明可能有许多的修改和变化。因此要了解在所附的权利要求里，本发明可以不如在此特定所述的来实施。

Claims (63)

1.一种接合结构，其特征在于，包括：
第一组件，所述第一组件包括：
第一介电层，所述第一介电层具有第一抛光接触面；以及
第一传导接触结构，所述第一传导接触结构形成在所述第一介电层的一部分中；
第二组件，所述第二组件直接接合到所述第一组件而没有插入黏着剂，所述第二组件包括：
第二介电层，所述第二介电层具有第二抛光接触面，所述第二抛光接触面接触且直接接合到所述第一抛光接触面；以及
第二传导接触结构；以及
传导阻障材料层，所述传导阻障材料层具有第一部分，所述第一部分至少设置在所述第一传导接触结构和所述第二传导接触结构之间，所述第一部分接触所述第一介电层和所述第二介电层，所述传导阻障材料层的所述第一部分直接接触所述第一传导接触结构的上表面以及所述第二传导接触结构的上表面中的至少一个，其中
所述第一介电层、所述第二介电层、所述第一传导接触结构、所述第二传导接触结构以及所述传导阻障材料层形成直接混合型接合件的部分。
2.根据权利要求1所述的接合结构，其特征在于，所述第二组件还包括第三传导接触结构，所述第三传导接触结构通过所述第二介电层与所述第二传导接触结构横向分隔开。
3.根据权利要求2所述的接合结构，其特征在于，所述传导阻障材料层还具有第二部分，所述传导阻障材料层的所述第二部分设置在所述第一传导接触结构的所述上表面和所述第三传导接触结构的上表面之间并且接触所述第一传导接触结构的所述上表面和所述第三传导接触结构的所述上表面。
4.根据权利要求3所述的接合结构，其特征在于，所述传导阻障材料层还包括第三部分，所述传导阻障材料层的所述第三部分设置在所述第一传导接触结构和所述第二介电层之间。
5.根据权利要求4所述的接合结构，其特征在于，所述第一组件还包括第四传导接触结构，所述第四传导接触结构通过所述第一介电层与所述第一传导接触结构横向分隔开。
6.根据权利要求5所述的接合结构，其特征在于，所述传导阻障材料层还包括第四部分，所述传导阻障材料层的所述第四部分设置在所述第三传导接触结构的所述上表面和所述第四传导接触结构的上表面之间并且接触所述第三传导接触结构的所述上表面和所述第四传导接触结构的所述上表面。
7.根据权利要求1所述的接合结构，其特征在于，所述传导阻障材料层沿着所述第一传导接触结构的侧边设置。
8.根据权利要求7所述的接合结构，其特征在于，所述传导阻障材料层完全围绕所述第一传导接触结构及所述第二传导接触结构。
9.根据权利要求1所述的接合结构，其特征在于，所述传导阻障材料层的所述第一部分包括第一阻障层及第二阻障层，所述第一阻障层直接接触所述第一传导接触结构的所述上表面并且所述第二阻障层直接接触所述第二传导接触结构的所述上表面。
10.根据权利要求1所述的接合结构，其特征在于，所述传导阻障材料层的所述第一部分接触所述第一介电层的侧壁的一部分。
11.根据权利要求1所述的接合结构，其特征在于，所述传导阻障材料层的所述第一部分设置在所述第一传导接触结构上方并且接触所述第二介电层的接触表面。
12.一种结构，其特征在于，包括：
基板的直接混合型接合表面，所述直接混合型接合表面包括：
介电层，所述介电层具有抛光上表面，以及
第一传导阻障材料层，所述第一传导阻障材料层直接形成在第一传导接触结构上；
其中所述第一传导阻障材料层的上表面凹陷在所述介电层的所述抛光上表面下方，所述第一传导阻障材料层的所述上表面包括接触面，所述接触面被设置以接触且直接接合到组件的第一部分，并且所述介电层的所述抛光上表面被设置以直接接触所述组件的第二部分。
13.根据权利要求12所述的结构，其特征在于，所述组件的所述第一部分包括第二传导接触结构，并且所述第一传导接触结构被配置以电性连接所述组件的所述第二传导接触结构。
14.根据权利要求13所述的结构，其特征在于，所述组件包括第二传导阻障材料层，所述第二传导阻障材料层直接形成在所述第二传导接触结构上。
15.根据权利要求13所述的结构，其特征在于，所述第一传导接触结构被配置以电性连接所述组件的第三传导接触结构，所述第三传导接触结构通过介电材料与所述第二传导接触结构横向分隔开。
16.根据权利要求12所述的结构，其特征在于，所述接触表面接触所述组件的传导部分和非传导部分。
17.根据权利要求12所述的结构，其特征在于，所述第一传导阻障材料层形成在所述第一传导接触结构的底部和侧面上。
18.根据权利要求12所述的结构，其特征在于，所述第一传导接触结构包括通孔，所述通孔垂直延伸且至少部分穿过所述介电层。
19.根据权利要求18所述的结构，其特征在于，所述通孔具有锥形侧壁。
20.根据权利要求12所述的结构，其特征在于，所述第一传导阻障材料层的所述上表面是在所述介电层的所述抛光上表面之下凹1奈米到10奈米。
21.根据权利要求12所述的结构，其特征在于，所述第一传导阻障材料层的所述上表面是凹陷的，使得凹腔被形成在所述第一传导阻障材料层的所述上表面上。
22.一种接合结构，其特征在于，包括：
第一基板，所述第一基板包括：
第一介电层；以及
第一传导接触结构；
第二基板，所述第二基板直接接合到所述第一基板而没有插入黏着剂，所述第二基板包括：
第二介电层；以及
第二传导接触结构；以及
阻障材料层，所述阻障材料层具有第一部分，所述第一部分设置在所述第一传导接触结构和所述第二传导接触结构之间，所述传导阻障材料层的所述第一部分直接接触所述第一传导接触结构的上表面及所述第二传导接触结构的上表面中的至少一个，其中所述第一介电层、所述第二介电层、所述第一传导接触结构、所述第二传导接触结构以及所述传导材料层形成直接混合型接合件的部分；
其中，所述阻障材料层包括金属氮化物。
23.根据权利要求22所述的接合结构，其特征在于，所述第一介电层具有第一抛光接触面并且所述第二介电层具有第二抛光接触面，所述第二抛光接触面接触所述第一抛光接触面。
24.一种结构，其特征在于，包括：
组件的直接混合型接合表面，所述直接混合型接合表面包括：
介电层；
第一传导阻障材料层，所述第一传导阻障材料层直接形成在传导接触结构的上表面上；
其中，所述第一传导阻障材料层的上表面凹陷于所述介电层上表面下方，所述第一传导阻障材料层的所述上表面包括接触表面，所述接触表面被配置用以接触且直接接合到其他组件的基板。
25.根据权利要求24所述的结构，其特征在于，所述传导接触结构的所述上表面在所述介电层的所述上表面之下5-40奈米。
26.一种接合结构，其特征在于，包括：
第一组件及第二组件，所述第一组件及所述第二组件分别界定第一直接混合型接合表面及第二直接混合型接合表面，所述第一组件及所述第二组件各自包括：
介电层；以及
传导接触结构；以及
第一传导阻障材料层，所述第一传导阻障材料层直接形成在所述第一组件的所述传导接触结构中的至少一个传导接触结构的上表面上；
其中，所述第一组件及所述第二组件的所述第一直接混合型接合表面及所述第二直接混合型接合表面是沿着接合接口而直接混合接合，使得：
所述第一组件及所述第二组件的所述介电层是彼此直接接触且直接接合；并且
所述第一组件及所述第二组件的所述传导接触结构通过所述接合接口相互电性连接，所述第一传导阻障材料层插入在所述第一组件的所述传导接触结构中的至少一个传导接触结构以及所述第二组件的所述传导接触结构中的对应的传导接触结构之间；
其中，所述第一组件的所述传导接触结构中的至少一个传导接触结构上方没有传导阻障材料层。
27.根据权利要求26所述的接合结构，其特征在于，所述第一传导阻障材料层在所述接合接口处直接接触所述第二组件的所述介电层。
28.根据权利要求26所述的接合结构，其特征在于，所述第一组件的所述传导接触结构中的至少一个传导接触结构相较于所述第二组件的所述传导接触结构中的所述对应的传导接触结构具有较宽的尺寸。
29.根据权利要求26所述的接合结构，其特征在于，还包括第二传导阻障材料层，所述第二传导阻障材料层直接形成在所述传导接触结构中的所述对应的传导接触结构的上表面上，使得所述第一传导阻障材料层和所述第二传导阻障材料层直接接触。
30.一种组件，其特征在于，包括：
第一介电层，所述第一介电层具有上表面，所述上表面被配置以直接接合到另一组件的第二介电层；
第一传导结构，所述第一传导结构形成在所述第一介电层的第一部分中；
第二传导结构，所述第二传导结构形成在与所述第一部分横向分隔开的所述第一介电层的第二部分中，所述第二传导结构具有与所述第一传导结构不同的横向尺寸；以及
阻障层，所述阻障层的第一部分至少形成在所述第一传导结构的上表面上，所述阻障层凹陷在所述第一介电层的所述上表面下方。
31.根据权利要求30所述的组件，其特征在于，所述阻障层的第二部分被进一步设置在所述第二传导结构上。
32.根据权利要求30所述的组件，其特征在于，所述第一传导结构的横向尺寸大于所述第二传导结构的横向尺寸。
33.根据权利要求32所述的组件，其特征在于，所述第一传导结构是联机件并且所述第二传导结构是通孔。
34.根据权利要求30所述的组件，其特征在于，所述阻障层具有接触表面，所述接触表面被配置以接触且直接接合到其他组件的传导材料。
35.根据权利要求30所述的组件，其特征在于，所述第一介电层的所述上表面包括抛光表面。
36.根据权利要求35所述的组件，其特征在于，所述抛光表面的表面粗糙度方均根为0.1到3奈米。
37.根据权利要求30所述的组件，其特征在于，所述第一介电层的所述上表面包括活化表面。
38.根据权利要求30所述的组件，其特征在于，所述阻障层还沿着所述第一传导结构的侧面设置。
39.根据权利要求38所述的组件，其特征在于，所述阻障层完全围绕所述第一传导结构。
40.一种接合结构，其特征在于，包括：
第一组件，所述第一组件包括具有接触表面的第一介电层、形成在所述第一介电层的第一部分中的第一传导结构以及形成在与所述第一部分横向分隔开的所述第一介电层的第二部分中的第二传导结构；
第二组件，所述第二组件包括具有与所述第一介电层的所述接触表面直接接触的接触表面的第二介电层以及形成在所述第二介电层的第三部分中并且与所述第一传导结构和所述第二传导结构电性耦接的第三传导结构；以及
阻障层，所述阻障层至少设置在所述第一传导结构和所述第三传导结构之间。
41.根据权利要求40所述的接合结构，其特征在于，所述阻障层直接接触所述第一传导结构。
42.根据权利要求40所述的接合结构，其特征在于，所述阻障层也是设置在所述第二传导结构和所述第三传导结构之间。
43.根据权利要求40所述的接合结构，其特征在于，所述第三传导结构包括传导联机件。
44.根据权利要求43所述的接合结构，其特征在于，所述第一传导结构和所述第二传导结构包括传导通孔。
45.根据权利要求40所述的接合结构，其中所述阻障层包括多层结构，在所述多层结构中，第一阻障层直接接合到第二阻障层。
46.根据权利要求40所述的接合结构，其特征在于，所述第一介电层、所述第二介电层、所述第一传导结构、所述第二传导结构以及所述阻障层形成直接混合型接合件的部分。
47.根据权利要求40所述的接合结构，其特征在于，所述第一传导结构的横向尺寸大于所述第二传导结构的横向尺寸。
48.根据权利要求40所述的接合结构，其特征在于，所述阻障层的至少一部分接触所述第一介电层。
49.一种接合结构，其特征在于，包括：
第一组件，所述第一组件包括具有接触表面的第一介电层、形成在所述第一介电层的第一部分中的第一传导结构以及阻障层，所述阻障层至少设置在所述第一传导结构上方，所述阻障层的至少一部分接触所述第一介电层；以及
第二组件，所述第二组件包括具有接触表面的第二介电层，所述接触表面直接接合到所述第一介电层的所述接触表面；以及传导材料，所述传导材料至少部分设置在所述第二介电层的第二部分中并且直接接合到所述阻障层。
50.根据权利要求49所述的接合结构，其特征在于，所述传导材料包括第二传导特征，所述第二传导特征形成在所述第二介电层的所述第二部分。
51.根据权利要求49所述的接合结构，其特征在于，所述传导材料包括第二阻障层，所述第二阻障层形成在第二传导特征上，所述第二传导特征形成在所述第二介电层的所述第二部分中，所述第二阻障层直接接合到所述第一组件的所述阻障层。
52.根据权利要求51所述的接合结构，其特征在于，所述第一组件进一步包括第三传导结构，所述第三传导结构与所述第一传导结构横向分隔开，所述第三传导结构电性连接到所述第二传导特征。
53.一种形成组件的方法，其特征在于，所述方法包括：
形成传导结构于介电层中，使得所述传导结构的顶表面在所述介电层的上表面之下；
形成阻障层于所述传导结构的所述顶表面上方，使得所述阻障层凹陷于所述上表面之下；
准备所述介电层的所述上表面以用于直接接合，使得至少所述上表面和所述阻障层界定直接混合型接合表面，所述直接混合型接合表面被配置以接合到另一组件。
54.根据权利要求53所述的方法，其特征在于，形成所述传导结构包括形成开口于所述介电层中以及至少沉积传导材料于所述开口中。
55.根据权利要求54所述的方法，其特征在于，沉积所述传导材料包括至少沉积所述传导材料于所述介电层的所述上表面上方，并且形成所述传导结构还包括移除所述传导材料在所述介电层的所述上表面上方的一部分。
56.根据权利要求55所述的方法，其特征在于，形成所述阻障层包括提供阻障材料于所述传导结构的所述顶表面以及所述介电层的所述上表面上方并且移除在所述介电层的所述上表面上方的所述阻障材料的一部分。
57.根据权利要求53所述的方法，其特征在于，准备所述介电层的所述上表面以用于直接接合包括抛光所述上表面以界定抛光表面，所述抛光表面的表面粗糙度方均根为0.1到3奈米。
58.根据权利要求53所述的方法，其特征在于，准备所述介电层的所述上表面以用于直接接合包括活化所述介电层的所述上表面。
59.一种形成接合结构的方法，其特征在于，所述方法包括：
提供第一组件，所述第一组件包括具有接触表面的第一介电层、形成在所述第一介电层的第一部分中的第一传导结构以及设置在所述第一传导结构的顶表面上方的阻障层，所述阻障层凹陷于所述接触表面之下；
将第二组件直接接合到所述第一组件，使得所述第二组件的第二介电层的接触表面沿着接合接口直接接合到所述第一介电层的所述接触表面而没有插入黏着剂，并且所述阻障层沿着所述接合接口而接合到所述第二组件的第二传导结构。
60.根据权利要求59所述的方法，其特征在于，还包括形成所述第一组件包括形成传导结构于介电层中，使得所述传导结构的所述顶表面是在所述介电层的所述接触表面之下并且形成所述阻障层于所述传导结构的所述顶表面上方，使得所述阻障层是凹陷于所述接触表面之下。
61.根据权利要求60所述的方法，其特征在于，还包括准备所述介电层的所述接触表面以用于直接接合，使得至少所述接触表面和所述阻障层界定直接混合型接合表面，所述直接混合型接合表面被设置以接合所述第二组件。
62.根据权利要求59所述的方法，其特征在于，直接接合所述第二组件到所述第一组件包括直接接合所述阻障层到所述第二传导结构。
63.根据权利要求59所述的方法，其特征在于，直接接合所述第二组件到所述第一组件包括直接接合所述阻障层到第二阻障层，所述第二阻障层形成在所述第二传导结构上。
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