CN103548120A - 最优化环形穿透基板通路 - Google Patents
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Abstract
本公开提供热机械可靠铜穿透基板通路(TSV)以及在BEOL工艺过程中形成此TSV的技术。TSV构成一环型沟槽,其延伸通过半导体基板。基板定义沟槽的内及外侧壁,其中侧壁由在5至10微米的范围内的一距离所分隔。包含铜或铜合金的传导路径于沟槽内从第一介电层的上表面延伸通过基板。基板厚度可为60微米或更少。具有传导地连接至传导路径的互连金属化的介电层直接地形成于环型沟槽之上。
Description
技术领域
本发明总地涉及集成电路中的穿透基板通路(TSV,through substratevia),更具体地,涉及在具有至少两个垂直堆叠基板的三维集成电路中的TSV。
背景技术
为了持续改善集成电路的效能及功能,企业最近已发展出使半导体器件芯片垂直集成的技术,一般称作三维(3D)堆叠技术。堆叠基板可为完整或部分的晶片,其每一者一般具有多个芯片。3D堆叠在连结后可被切块以分隔多个单元,每一单元具有垂直连结在一起的两个以上的芯片。一般来说,半导体芯片包括建立于半导体基板上的数层集成电路(如处理器、可编程器件、存储器件等)。连结堆叠的顶层可利用穿透基板的互连或通路(TSV)而连接至堆叠的底层。TSV的形成被认为是特别的挑战(请参考Dukovic等人的3D集成的穿透硅通路技术(Through-Silicon-Via Technology for3DIntegration))。
此外,延伸通过半导体基板的通路一般必须具有高纵横比。形成这样一深度特征而无损害剩余基板、且接着形成一传导路径于深度特征内(其与基板电性绝缘)是极度困难的。已有建议蚀刻孔洞于基板中,接着将基板暴露在非常高温中,由此形成氧化层于整体暴露表面上,其为可靠的绝缘层。这些温度与CMOS BEOL(后端工艺)工艺不相容,因此如此形成的氧化层必须在形成任何半导体器件(FEOL)或互连布线(BEOL)之前以“先通路(via first)”方式完成(参考Andry等人的US2010/0032764)。铜对TSV来说为优选,因为其具有高导电率。然而,“先通路”方式对铜通路来说是有问题的,因为半导体器件非常容易受到铜迁移到基板中所造成的损害的影响。
铜更相容于后端或“中间通路(via middle)”工艺,但TSV的铜与周围材料之间的热膨胀失配可产生过度热应力并造成破裂。Edelstein等人的US7,276,787(“'787”)建议通过利用环型TSV解决此问题。特别地,'787教示蚀刻大孔洞、形成一系列的层于侧壁上而无需填充孔洞(例如电性绝缘体、各种阻障层、传导层、及隔离层)。最后,孔洞的核心可由选择为具有类似基板的热特征的材料所填充,使得整体结构具有一等效CTE,其系紧密匹配基板的CTE及弹性模量。
然而,即使是环型铜TSV在CMOS BEOL工艺过程中遭遇到热循环时也容易挤压(例如请参考Cho的“TSV集成的技术挑战(Technical Challenges inTSV Integration)”)。由TSV的挤压可压迫上覆金属化层、减弱或短路任何内嵌互连布线。Cho提供SEM照片,其显示由暴露至用于互连金属化的形成(BEOL)的工艺温度而造成的铜TSV的挤压。由此类挤压所造成的损害绘示于图1A及1B。图1A显示固态TSV110的铜核心突出至钝化层102的CMP表面104之上,其抬起上覆层120且压迫嵌入于其中的互连布线122。图1B描述通过内部核心的裂痕105及开始于环型铜TSV130的下方内部角落的裂痕106。Cho建议通过最后形成通路而最小化铜挤压。
虽然“最后通路(via last)”工艺一般开始于足够低的温度以避免铜挤压,但“最后通路”消耗通过所有BEOL层的整体TSV覆盖区(footprint),使其效率远低于对工艺集成及芯片设计的目的。确定形成可在BEOL工艺过程中形成的可靠铜TSV的技术是非常有利的。
发明内容
在本发明的一方面中,提供TSV结构,其中TSV可在BEOL工艺过程中形成且可容许暴露至进一步的BEOL工艺。
在本发明一实施例中,提供了包括TSV的集成电路结构。该结构包括具有至少一半导体器件形成于其顶表面中的基板,以及设置于此顶表面上的第一介电层。TSV构成环型沟槽,其延伸通过基板及第一介电层,其中基板定义了沟槽的内及外侧壁,内侧壁和外侧壁由在5至10微米的范围内的一距离所分隔。包含铜或铜合金的传导路径于沟槽内从第一介电层的上表面延伸通过基板,其可具有90微米或更少的厚度。具有传导地连接至传导路径的互连金属化的第二介电层直接地形成于第一介电层上且上覆于环型沟槽。沟槽的内部直径可在4至9微米的范围内。侧壁分隔可在5.5至9微米的范围内,且沟槽的内部直径可在5至8微米的范围内。侧壁可具有轻微的倾斜,其可在相对于顶表面的85至90度内,优选范围在87至90度之间。传导路径可具有在2微米以上的平均晶粒尺寸。具有厚度在0.4至1.5微米范围中的介电衬垫可分隔传导路径与基板。
在本发明实施例中,提供一种集成电路(IC),其包括具有至少一半导体器件形成于其顶表面中的半导体基板以及在顶表面之上的第一介电层。IC还包括环型沟槽,其从第一介电层的上表面延伸至基板的底表面,此环型沟槽具有定义基板核心的内侧壁,基板核心在顶表面具有在5至8微米之间的直径,其中内侧壁相对于顶表面在85至90度之间倾斜。IC包括环型沟槽内的传导路径,该路径通过介电衬垫而与半导体基板隔离。IC包括第二介电层,其含有传导地连接至至少一半导体器件的互连金属化且上覆于环型沟槽。在实施例中,传导路径包括铜或铜合金,且半导体基板包含单晶硅。介电衬垫靠近沟槽底部的厚度为靠近顶表面的厚度的至少50%。介电衬垫可由SACVD及PECVD的组合所形成,且可具有5或更小的介电质常数或k值。
根据本发明另一实施例,提供一种形成坚固TSV结构的方法。该方法包括形成环型沟槽于基板中,其中基板包括形成于其顶表面中的至少一半导体器件,且沟槽具有以少于10微米分隔且延伸至90微米或更小的深度的内侧壁及外侧壁。该方法包括以共形介电衬垫为内及外侧壁加衬;以包括铜或铜合金的传导材料填充沟槽;以及在350℃以上退火填充的沟槽至少20分钟。退火可开始于350℃及430℃之间的温度,且可延长至1小时或更久。该方法的实施例可包括形成环型沟槽通过设置于顶表面之上的至少一BEOL层,以及形成第二BEOL层于该至少一BEOL层上以及该环型沟槽之上。该方法可还包括基板的后侧薄化以暴露填充的沟槽的传导材料。
附图说明
有关组织及操作方法两者的示范性实施例可通过参照结合附图的详细描述而有最佳理解。
图1A及1B描述由暴露至CMOS工艺的传统TSV所造成的损害。
图2A为根据本发明的环型TSV的垂直剖面图。
图2B及2D为根据本发明的TSV的详细视图。
图2C为图2A的TSV在AA的截面。
具体实施方式
本发明提供一种热机械可靠的铜TSV及在BEOL工艺过程中形成此TSV的技术,现在将结合附图对其详细描述。需注意,类似的附图标记在不同的实施例中指代类似的元件。附图并不必然依比例绘示。
将理解到,当一元件(如一层、区域或基板)被称作是在另一元件“上(on)”或“之上(over)”,其可直接地在另一元件上或是也可存在中介元件。相反地,当一元件被称作“直接在另一元件上”或“直接在另一元件之上”,则不存在中介元件。亦将理解到,当一元件被称作“连接”或“耦合”至另一元件,其可直接地连接或耦合至其他元件,或可存在中介元件。相反地,当一元件被称作“直接地连接”或“直接地耦合”至另一元件,则不存在中介元件。
如所指出的,本发明确定一TSV结构以及可靠地形成此结构的方法,此结构可承受CMOS BEOL热循环,而不会使周围材料破裂,由此提供一可靠的3D集成电路。
现在参考图2A,其描述了具有初始厚度202的半导体基板201。一或多个半导体器件(图未示)可形成于基板的顶表面211中及上。一或多个介电层210可设置于顶表面211之上。利用传统的后端相容光刻及蚀刻,环型沟槽230可形成通过介电层210,延伸通过顶表面211并进入基板201。一般来说,沟槽230由Bosch蚀刻所形成,其通过在各向异性反应性离子蚀刻及聚合物沉积步骤之间交替而进行,但本发明并不受限于此。环型沟槽230此时并不接触在其底端的其他特征,因此其可称作“盲孔(blind via)”。
本文中的基板可包括任何半导体,例如硅(Si)、硅锗(SiGe)、硅锗碳(SiGeC)、碳化硅(SiC)、锗合金、砷化镓(GaAs)、砷化铟(InAs)、磷化铟(InP)及其他III/V族或II/VI族化合物半导体。除了这些所列举的半导体材料类型,本发明也考虑半导体基板为层状半导体的情况,例如硅/硅锗、硅/碳化硅、绝缘层上硅(SOI)或绝缘层上硅锗(SGOI)。此外,基板201可为单晶、多晶、非晶、或具有单晶部分、多晶部分、及非晶部分的至少两者的组合。在一优选实施例中,基板201包含单晶硅部分。
介电层210可包括直接设置于半导体基板上的一钝化层(其包含例如二氧化硅(SiO2))。选择性地,介电层210可包括设置于钝化层之上的一或多个额外层,其包含电介质及传导材料212的一组合,例如多层互连结构的一或多个BEOL互连等级。介电层210可由此技艺中已知的任何介电材料的其中之一或组合而形成,例如有机绝缘体(例如聚亚酰胺)、无机绝缘体(例如氮化硅或二氧化硅)、低K电介质(例如SiLKTM)、掺杂或未掺杂硅酸盐玻璃、有机硅酸盐、BLoKTM、NBLoKTM、热固性聚芳醚(所指为芳基成分或惰性取代芳基成分,其通过化学键、稠环、或惰性链接组(例如氧、硫、砜、亚砜、羰基及类似者)而链接在一起)、或可设置或形成于基板上的其他类型的介电材料。在实施例中,介电材料具有5或更低的k值。
再次参考图2A,环型沟槽230的长度204小于基板201的初始厚度202。长度204可小于90微米,且优选在60微米或更小的范围中。在顶表面211,环型沟槽的宽度203(其为内侧壁206及外侧壁205的分隔)在5至10微米的范围内。优选地,在顶表面211的环型沟槽的内及外侧壁由在5.5至9微米范围内的一距离所分隔。
形成环型沟槽230的蚀刻程序可名义上形成直侧壁,虽然侧壁实际上可能具有扇形轮廓,每一“扇形”对应Bosch工艺的单一蚀刻/聚合物沉积循环。沿侧壁表面的高度变化或“粗糙度”优选最小化,例如在0至0.5微米之间。特别地,针对单一扇形的一给定垂直长度“S”,该沟槽的宽度差异小于百分之十,即小于或等于0.2×S(说明在两侧壁上的百分之十的变化)。侧壁可垂直于顶表面211或可轻微地倾斜。参考图2B,侧壁205及206可具有相同的相对于一般平面顶表面211的斜率,但205及206并不必然具有相同斜率。每一侧壁及顶表面211优选形成范围在87至90度中的一角度208。根据本发明的实施例,侧壁205及206朝沟槽的中心倾斜,使得环型通孔230随着深度变窄。
图2C为图2A在AA的截面。环型沟槽230定义一内基板核心,其可具有圆形的横截面,使得核心构成一般圆柱形的外形。在顶表面211的基板核心的直径209可在4至9微米的范围,且优选在5至8微米的范围。在顶表面211的环型沟槽230的外直径219可在18至25微米的范围,且优选在19至23微米的范围。
层232的放大图显示于图2D中。层232包括一绝缘衬垫233,且也可包括数个其他层用于各种功能,例如用以避免扩散。绝缘衬垫233可具有高共形性(conformality)且可例如通过二氧化硅的次常压化学气相沉积(SACVD)沉积或可流动氧化物的沉积而形成。在某些实施例中,绝缘层233在第一(或顶)端“T”的厚度在0.4至1.5微米之间。绝缘衬垫233可形成于环型沟槽230的侧壁上,使得邻近远端“R”的侧壁上的厚度相对于邻近顶表面211的侧壁上的厚度为至少百分之50或在百分之65至百分之百之间。在实施例中,绝缘衬垫233可具有5或更小的k值。
介电盖234可形成以保护绝缘衬垫233。在实施例中,氧化物盖234可形成以完全地覆盖沟槽230内的绝缘衬垫233。盖层234可通过等离子体增强化学气相沉积(PECVD)而形成,在邻近顶表面211的侧壁上量测的一名义厚度在1000至之间,而在远端的厚度为该名义厚度的至少百分之15或在百分之20至百分之30的范围中。
层232可包括一或多个阻障或粘着层235。阻障层可例如包含钽(Ta)、氮化钽(TaN)、钛(Ti)、氮化钛(TiN)、钌(Ru)、氮化钌(RuN)、钌钽(RuTa)、氮化钌钽(RuTaN)、钨(W)、氮化钨(WN)、或可作为阻障以避免传导材料扩散通过其中的任何其他材料。实际阻障材料可基于传导TSV核心(例如铜)及绝缘衬垫233的材料而选择。在某些实施例中,阻障235可通过钽/氮化钽的沉积而形成,其厚度在20至约之间,更典型为在50至之间。扩散阻障可通过已知方法形成,例如等离子体增强化学气相沉积(PECVD)、ALD、PVD、溅射、化学溶液沉积或电镀。针对电镀,层232也将包括一种子层236。针对铜TSV,种子层236可通过传统工艺(例如通过PVD或ALD)而形成至范围在1000至或范围在1500至的厚度。
无孔洞填充工艺(例如可由Novellus或Nexx获得)可用以将TSV以铜填充。传导填充可包含铜或任何其他传导金属、包含至少一传导金属的合金、传导金属硅化物或其组合。优选地,传导材料为传导金属,例如铜、钨或铝,在本发明中优选为铜或铜合金(例如铝铜(AlCu))。填充工艺可受控以导致最小的覆盖层(over burden)。选择性地,覆盖层可使用化学湿蚀刻而降低至约2微米或更低。
接着将结构退火以增加平均晶粒尺寸至约2微米或至范围在3至5微米的尺寸。退火可在300℃以上的温度下进行。结构可维持在高温超过15分钟或在20至120分钟的范围。在某些实施例中,结构维持在335至410℃的范围至少50分钟。结构可维持在350至430℃的范围20至100分钟。
在退火后,可移除剩余的覆盖层。一般来说,覆盖层可通过CMP及随后的抛光而移除。选择性地,可通过传统的BEOL工艺形成进一步的BEOL层于TSV的顶端之上。结构可依附至顶侧以实现晶片处理。后侧可被研磨或蚀刻至60到90微米或更少的厚度,因而暴露TSV的底端,根据需求而再形成后侧连接至TSV,包括例如钝化及接触垫。
示例1
环型铜电镀TSV以最小工艺复杂度集成以最大化布线性(wireability)。小于100微米深度、最小节距50微米、具有接近垂直侧壁的盲孔由Bosch工艺所制成。在TSV底部具有良好覆盖范围的沉积共形氧化物用于绝缘。溅射沉积用于阻障及种子层,接着自底向上的无孔洞铜电镀、退火及CMP以移除最小的电镀覆盖层。厚Cu布线等级利用TSV所观察到的较低电压降但导致额外的翘曲。并入高度压缩ILD膜的工艺用于关键通路等级以补偿增加的翘曲。完成的晶片连结至玻璃处理机且由研磨、磨光、RIE而薄化。沉积PECVD氧化物/氮化物。在CMP暴露TSV金属后,电沉积铜且定义后侧重分配等级。晶片使用管芯等级C4接合而于有机层叠上切割及组装。执行可靠度测试。在399℃浸泡后,薄氮化硅盖(顶侧)层维持完整。在-65℃及150℃之间500个循环的热循环之后,针对ILD损害的测试无发现泄漏的变化。热循环亦显示TSV阻抗或邻近TSV的器件的功能并无劣化。
虽然本发明已相对于优选实施例而特别地显示及描述,本领域的技术人员将了解到可做出形式及细节上的前述及其他变化而无偏离本发明的精神及范围。因此,本发明并不意欲限制于所描述及说明的精确形式及细节,而应落入所附权利要求的范围内。
Claims (10)
1.一种集成电路结构,包括:
基板,具有形成于该基板的顶表面中的至少一半导体器件,且第一介电层设置于该顶表面之上;
环型沟槽,通过该第一介电层且延伸通过该基板,其中该基板构成该沟槽的内侧壁及外侧壁,该内侧壁及该外侧壁由在5至10微米的范围内的一距离所分隔;
该沟槽内的传导路径,从该第一介电层的上表面延伸通过该基板,该路径包括铜或铜合金;以及
第二介电层,包含互连金属化,该互连金属化传导地连接至该传导路径,该第二介电层直接地形成于该第一介电层上且上覆于该环型沟槽。
2.如权利要求1所述的结构,其中该内侧壁及该外侧壁由在5.5至9微米的范围内的一距离所分隔且该直径在5至8微米的范围内。
3.如权利要求1所述的结构,其中该内侧壁及该外侧壁相对于该顶表面以85至90度内的一角度倾斜。
4.如权利要求1所述的结构,其中该传导路径具有大于2微米的平均晶粒尺寸。
5.一种集成电路,包括:
半导体基板,具有形成于该半导体基板的顶表面中的至少一半导体器件;
环型沟槽,从该顶表面延伸至该半导体基板的底表面,该环型沟槽具有定义该半导体基板的核心的内侧壁,该核心在该顶表面具有在5至8微米之间的直径,该内侧壁相对于该顶表面在87至90度之间倾斜;
该环型沟槽内的传导路径,该传导路径通过介电衬垫而与该半导体基板隔离;以及
介电层,包含传导地连接至该至少一半导体器件的互连金属化,该介电层上覆于该环型沟槽。
6.如权利要求5所述的结构,其中
该传导路径包括铜或铜合金,且
该半导体基板包括单晶硅,且
该介电衬垫在该内侧壁上具有一厚度,靠近该底表面的该厚度为在该顶表面的该厚度的至少50%。
7.如权利要求5所述的结构,其中在该顶表面处该环形沟槽的外部直径在19至23微米之间。
8.一种形成坚固TSV结构的方法,该方法包括:
在基板中形成环型沟槽,该基板具有形成于其顶表面中的至少一半导体器件,该沟槽具有以小于10微米分隔且延伸至90微米或更小的深度的内侧壁及外侧壁;
以共形介电衬垫为该内侧壁及该外侧壁加衬;
以包括铜或铜合金的传导材料填充该沟槽;以及
在350℃以上退火填充的该沟槽至少20分钟。
9.如权利要求8所述的方法,还包括该基板的后侧薄化以暴露填充的该沟槽的该传导材料。
10.如权利要求8所述的方法,其中该侧壁具有粗糙度小于10%的扇形轮廓。
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Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20120000748A (ko) * | 2010-06-28 | 2012-01-04 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
US8709936B2 (en) * | 2012-07-31 | 2014-04-29 | International Business Machines Corporation | Method and structure of forming backside through silicon via connections |
US9245790B2 (en) * | 2013-01-23 | 2016-01-26 | GlobalFoundries, Inc. | Integrated circuits and methods of forming the same with multiple embedded interconnect connection to same through-semiconductor via |
CN103985666A (zh) * | 2013-02-07 | 2014-08-13 | 中芯国际集成电路制造(上海)有限公司 | 一种环形硅深孔及环形硅深孔电极的制备方法 |
US9184041B2 (en) | 2013-06-25 | 2015-11-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit with backside structures to reduce substrate warp |
KR102114340B1 (ko) | 2013-07-25 | 2020-05-22 | 삼성전자주식회사 | Tsv 구조 및 디커플링 커패시터를 구비한 집적회로 소자 및 그 제조 방법 |
US8980746B2 (en) * | 2013-08-13 | 2015-03-17 | Lam Research Corporation | Adhesion layer for through silicon via metallization |
US20150069608A1 (en) * | 2013-09-11 | 2015-03-12 | International Business Machines Corporation | Through-silicon via structure and method for improving beol dielectric performance |
JP6404787B2 (ja) * | 2014-09-26 | 2018-10-17 | 信越化学工業株式会社 | ウエハ加工体、ウエハ加工用仮接着材、及び薄型ウエハの製造方法 |
US9548273B2 (en) | 2014-12-04 | 2017-01-17 | Invensas Corporation | Integrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other purposes, and methods of fabricating such assemblies |
KR101644266B1 (ko) * | 2015-04-08 | 2016-07-29 | 주식회사 스탠딩에그 | 캡 기판의 제조 방법, 이를 이용한 mems 장치의 제조 방법, 및 mems 장치 |
KR101672640B1 (ko) * | 2015-06-23 | 2016-11-03 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 |
KR102379165B1 (ko) | 2015-08-17 | 2022-03-25 | 삼성전자주식회사 | Tsv 구조를 구비한 집적회로 소자 및 그 제조 방법 |
US10199461B2 (en) * | 2015-10-27 | 2019-02-05 | Texas Instruments Incorporated | Isolation of circuit elements using front side deep trench etch |
US9899260B2 (en) | 2016-01-21 | 2018-02-20 | Micron Technology, Inc. | Method for fabricating a semiconductor device |
EP3223063A1 (en) | 2016-03-24 | 2017-09-27 | Thomson Licensing | Device for forming a field intensity pattern in the near zone, from incident electromagnetic waves |
EP3223062A1 (en) * | 2016-03-24 | 2017-09-27 | Thomson Licensing | Device for forming at least one focused beam in the near zone, from incident electromagnetic waves |
US9892970B2 (en) | 2016-06-02 | 2018-02-13 | Globalfoundries Inc. | Integrated circuit structure having deep trench capacitor and through-silicon via and method of forming same |
US9929085B2 (en) | 2016-06-02 | 2018-03-27 | Globalfoundries Inc. | Integrated circuit structure having deep trench capacitor and through-silicon via and method of forming same |
US10727138B2 (en) | 2016-06-28 | 2020-07-28 | Intel Corporation | Integration of single crystalline transistors in back end of line (BEOL) |
EP3312646A1 (en) | 2016-10-21 | 2018-04-25 | Thomson Licensing | Device and method for shielding at least one sub-wavelength-scale object from an incident electromagnetic wave |
EP3312660A1 (en) | 2016-10-21 | 2018-04-25 | Thomson Licensing | Device for forming at least one tilted focused beam in the near zone, from incident electromagnetic waves |
EP3385219B1 (en) | 2017-04-07 | 2021-07-14 | InterDigital CE Patent Holdings | Method for manufacturing a device for forming at least one focused beam in a near zone |
US10867905B2 (en) * | 2017-11-30 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structures and methods of forming the same |
TWI691038B (zh) * | 2018-01-30 | 2020-04-11 | 聯華電子股份有限公司 | 半導體裝置及其形成方法 |
KR20220133013A (ko) * | 2021-03-24 | 2022-10-04 | 삼성전자주식회사 | 관통 비아 구조물을 갖는 반도체 장치 |
CN113410175B (zh) * | 2021-06-15 | 2023-06-02 | 西安微电子技术研究所 | 一种tsv导电通孔结构制备方法 |
CN114959606A (zh) * | 2022-05-13 | 2022-08-30 | 赛莱克斯微系统科技(北京)有限公司 | 硅通孔种子层的制备方法及芯片的制备方法 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002043502A (ja) * | 2000-07-25 | 2002-02-08 | Toshiba Corp | マルチチップ半導体装置、ならびにマルチチップ半導体装置用チップ及びその製造方法 |
CN1684256A (zh) * | 2003-12-05 | 2005-10-19 | 国际商业机器公司 | 具有导电穿透通道的硅芯片载体及其制造方法 |
CN1745471A (zh) * | 2003-02-03 | 2006-03-08 | 国际商业机器公司 | 用于铜互连的牺牲金属衬层 |
US20070096321A1 (en) * | 1999-10-15 | 2007-05-03 | Ivo Raaijmakers | Conformal lining layers for damascene metallization |
US20100164062A1 (en) * | 2008-12-31 | 2010-07-01 | Industrial Technology Research Institute | Method of manufacturing through-silicon-via and through-silicon-via structure |
CN101789390A (zh) * | 2009-01-23 | 2010-07-28 | 财团法人工业技术研究院 | 硅导通孔的制造方法与硅导通孔结构 |
US20100237472A1 (en) * | 2009-03-18 | 2010-09-23 | International Business Machines Corporation | Chip Guard Ring Including a Through-Substrate Via |
US20110095435A1 (en) * | 2009-10-28 | 2011-04-28 | International Business Machines Corporation | Coaxial through-silicon via |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003318178A (ja) * | 2002-04-24 | 2003-11-07 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
US6790775B2 (en) * | 2002-10-31 | 2004-09-14 | Hewlett-Packard Development Company, L.P. | Method of forming a through-substrate interconnect |
WO2004064159A1 (ja) * | 2003-01-15 | 2004-07-29 | Fujitsu Limited | 半導体装置及び三次元実装半導体装置、並びに半導体装置の製造方法 |
JP2006019455A (ja) * | 2004-06-30 | 2006-01-19 | Nec Electronics Corp | 半導体装置およびその製造方法 |
WO2007110799A2 (en) | 2006-03-27 | 2007-10-04 | Philips Intellectual Property & Standards Gmbh | Low ohmic through substrate interconnection for semiconductor carriers |
US7625814B2 (en) | 2006-03-29 | 2009-12-01 | Asm Nutool, Inc. | Filling deep features with conductors in semiconductor manufacturing |
US7863189B2 (en) | 2007-01-05 | 2011-01-04 | International Business Machines Corporation | Methods for fabricating silicon carriers with conductive through-vias with low stress and low defect density |
US20100044853A1 (en) | 2007-01-17 | 2010-02-25 | Nxp, B.V. | System-in-package with through substrate via holes |
US7902069B2 (en) | 2007-08-02 | 2011-03-08 | International Business Machines Corporation | Small area, robust silicon via structure and process |
JP2009055004A (ja) * | 2007-08-24 | 2009-03-12 | Honda Motor Co Ltd | 貫通配線構造 |
US7821107B2 (en) * | 2008-04-22 | 2010-10-26 | Micron Technology, Inc. | Die stacking with an annular via having a recessed socket |
US7741226B2 (en) | 2008-05-06 | 2010-06-22 | International Business Machines Corporation | Optimal tungsten through wafer via and process of fabricating same |
JP2010010324A (ja) * | 2008-06-26 | 2010-01-14 | Toshiba Corp | 半導体装置及び半導体装置の製造方法 |
US8138036B2 (en) | 2008-08-08 | 2012-03-20 | International Business Machines Corporation | Through silicon via and method of fabricating same |
JP5246103B2 (ja) * | 2008-10-16 | 2013-07-24 | 大日本印刷株式会社 | 貫通電極基板の製造方法 |
US8329578B2 (en) * | 2009-03-27 | 2012-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Via structure and via etching process of forming the same |
US8062975B2 (en) | 2009-04-16 | 2011-11-22 | Freescale Semiconductor, Inc. | Through substrate vias |
JP5644242B2 (ja) * | 2009-09-09 | 2014-12-24 | 大日本印刷株式会社 | 貫通電極基板及びその製造方法 |
FR2951017A1 (fr) | 2009-10-05 | 2011-04-08 | St Microelectronics Crolles 2 | Via de connexion electrique pour substrat de dispositif semi-conducteur |
-
2011
- 2011-06-23 US US13/167,107 patent/US8487425B2/en active Active
-
2012
- 2012-06-19 JP JP2014517076A patent/JP2014517547A/ja active Pending
- 2012-06-19 KR KR1020137030358A patent/KR20140014251A/ko active IP Right Grant
- 2012-06-19 CA CA2828498A patent/CA2828498A1/en not_active Abandoned
- 2012-06-19 CN CN201280024501.2A patent/CN103548120B/zh active Active
- 2012-06-19 WO PCT/US2012/043052 patent/WO2012177585A2/en active Application Filing
- 2012-06-19 DE DE112012001870.2T patent/DE112012001870B4/de active Active
- 2012-06-19 GB GB1318982.4A patent/GB2505576B/en not_active Expired - Fee Related
- 2012-06-20 TW TW101122019A patent/TWI525776B/zh active
-
2013
- 2013-05-09 US US13/890,322 patent/US8658535B2/en active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070096321A1 (en) * | 1999-10-15 | 2007-05-03 | Ivo Raaijmakers | Conformal lining layers for damascene metallization |
JP2002043502A (ja) * | 2000-07-25 | 2002-02-08 | Toshiba Corp | マルチチップ半導体装置、ならびにマルチチップ半導体装置用チップ及びその製造方法 |
CN1745471A (zh) * | 2003-02-03 | 2006-03-08 | 国际商业机器公司 | 用于铜互连的牺牲金属衬层 |
CN1684256A (zh) * | 2003-12-05 | 2005-10-19 | 国际商业机器公司 | 具有导电穿透通道的硅芯片载体及其制造方法 |
US20100164062A1 (en) * | 2008-12-31 | 2010-07-01 | Industrial Technology Research Institute | Method of manufacturing through-silicon-via and through-silicon-via structure |
CN101789390A (zh) * | 2009-01-23 | 2010-07-28 | 财团法人工业技术研究院 | 硅导通孔的制造方法与硅导通孔结构 |
US20100237472A1 (en) * | 2009-03-18 | 2010-09-23 | International Business Machines Corporation | Chip Guard Ring Including a Through-Substrate Via |
US20110095435A1 (en) * | 2009-10-28 | 2011-04-28 | International Business Machines Corporation | Coaxial through-silicon via |
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TW201306218A (zh) | 2013-02-01 |
CN103548120B (zh) | 2016-12-07 |
CA2828498A1 (en) | 2012-12-27 |
WO2012177585A3 (en) | 2013-04-25 |
US20130244420A1 (en) | 2013-09-19 |
US20120326309A1 (en) | 2012-12-27 |
WO2012177585A2 (en) | 2012-12-27 |
GB201318982D0 (en) | 2013-12-11 |
KR20140014251A (ko) | 2014-02-05 |
US8658535B2 (en) | 2014-02-25 |
GB2505576A (en) | 2014-03-05 |
TWI525776B (zh) | 2016-03-11 |
DE112012001870T5 (de) | 2014-03-27 |
DE112012001870B4 (de) | 2018-09-13 |
US8487425B2 (en) | 2013-07-16 |
GB2505576B (en) | 2016-03-23 |
JP2014517547A (ja) | 2014-07-17 |
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