WO2022000385A1 - 显示面板的制作方法、显示面板及显示装置 - Google Patents

显示面板的制作方法、显示面板及显示装置 Download PDF

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WO2022000385A1
WO2022000385A1 PCT/CN2020/099791 CN2020099791W WO2022000385A1 WO 2022000385 A1 WO2022000385 A1 WO 2022000385A1 CN 2020099791 W CN2020099791 W CN 2020099791W WO 2022000385 A1 WO2022000385 A1 WO 2022000385A1
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metal
layer
sub
sublayer
display panel
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PCT/CN2020/099791
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English (en)
French (fr)
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翟峰
唐彪
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重庆康佳光电技术研究院有限公司
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Priority to PCT/CN2020/099791 priority Critical patent/WO2022000385A1/zh
Priority to US17/480,725 priority patent/US12040431B2/en
Publication of WO2022000385A1 publication Critical patent/WO2022000385A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/42—Transparent materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating

Definitions

  • the present invention relates to the field of display technology, and in particular, to a manufacturing method of a display panel, a display panel, and a display device including the display panel.
  • the epitaxial structure on the growth substrate is generally transferred to the circuit substrate through the wafer bonding technology.
  • the traditional wafer bonding technology often selects metal to bond at 400 °C, and the thermal expansion coefficient of the circuit substrate and the growth substrate is different.
  • the delamination problem caused by thermal mismatch often occurs in the high-temperature bonding process, which affects the display quality.
  • the purpose of the present application is to provide a method for fabricating a display panel, a display panel, and a display device including the display panel, aiming to solve the problem that when the epitaxial structure on the growth substrate is transferred to the circuit substrate at high temperature, Due to the obvious difference in thermal expansion coefficient between the circuit substrate and the growth substrate, the delamination problem caused by thermal mismatch occurs in the high-temperature bonding process.
  • the present application provides a method for fabricating a display panel, comprising: providing a first substrate and a second substrate, wherein the first substrate includes a growth substrate, an epitaxial structure, and a first metal layered in sequence. layer, the second substrate includes a circuit substrate and a second metal layer stacked on the circuit substrate; activation treatment is performed on the first metal layer, and activation treatment is performed on the second metal layer; bonding activation The processed first metal layer and the activated second metal layer, so that the growth substrate, the epitaxial structure, the first metal layer, the second metal layer and the circuit
  • the substrates are stacked in sequence; the growth substrates are peeled off.
  • the activated first metal layer and the second metal layer are in contact with each other at room temperature.
  • the atomic diffusion phenomenon makes the first metal layer and the second metal layer adhere to each other to realize bonding, so as to transfer the epitaxial structure to the circuit substrate.
  • the bonding process of the present application is carried out at room temperature, which avoids the delamination problem caused by thermal mismatch due to the large difference in thermal expansion coefficient between the circuit substrate and the growth substrate in the current high-temperature bonding process, which is beneficial to the display performance of the display panel. improvement.
  • the first metal layer includes a first surface facing away from the growth substrate, and the second metal layer includes a second surface facing away from the circuit substrate; and performing activation treatment on the first metal layer Including activating the first surface; activating the second metal layer including activating the second surface; bonding the activated first metal layer and the activated
  • the second metal layer includes bonding the first surface and the second surface.
  • the method of surface activation treatment may include ion beam activation. During the surface activation treatment, the first surface and the second surface are first subjected to activation, the metal atoms of the first surface and the second surface are activated, and the first surface and the second surface are activated. When in contact with each other, the activated metal atoms diffuse to achieve bonding.
  • the first metal layer includes a first metal sublayer, a second metal sublayer, and a third metal sublayer that are stacked in sequence, and the first metal sublayer is stacked on the epitaxial structure;
  • the The second metal layer includes a fourth metal sublayer, a fifth metal sublayer and a sixth metal sublayer that are stacked in sequence, and the sixth metal sublayer is stacked on the circuit substrate;
  • the third metal sublayer and the fourth metal sublayer are completely etched away, and the second metal sublayer and the fifth metal sublayer are bonded connect.
  • the third metal sublayer and the fourth metal sublayer on the surface layer can be completely etched away.
  • the partial etching is to ensure that the third metal sub-layer remaining in the valley is not higher than the peak of the wave to ensure that the second metal sub-layer and the fifth metal sub-layer
  • the layers can be in contact with each other, so the partial etching controls the activation process conditions (such as time) more strictly, which increases the difficulty of operation, while the full etching can choose a longer activation etching time, without considering the third metal sublayer and the third metal sublayer.
  • the residual state of the four metal sub-layers has greater process flexibility and is convenient for operation.
  • the first metal layer includes a first metal sublayer, a second metal sublayer, and a third metal sublayer that are stacked in sequence, and the first metal sublayer is stacked on the epitaxial structure;
  • the The second metal layer includes a fourth metal sublayer, a fifth metal sublayer and a sixth metal sublayer that are stacked in sequence, and the sixth metal sublayer is stacked on the circuit substrate;
  • the third metal sub-layer is partially etched away to expose the second metal sub-layer
  • the fourth metal sub-layer is partially etched away to expose all the metal sub-layers.
  • the fifth metal sublayer, the remaining third metal sublayer is bonded to the remaining fourth metal sublayer, and the exposed second metal sublayer is bonded to the exposed fifth metal sublayer combined connection.
  • the third metal sublayer and the fourth metal sublayer on the surface layer will be etched away.
  • the metal sublayer and the fourth metal sublayer are not completely etched (that is, a part of the third metal sublayer remains on the first metal layer, and a part of the fourth metal sublayer remains on the second metal layer). and the control of the surface roughness of the fifth metal sublayer, so that the second metal sublayer and the fifth metal sublayer have greater roughness, so that the surfaces of the second metal sublayer and the fifth metal sublayer have peaks and valleys,
  • part of the third metal sublayer and the fourth metal sublayer on the surfaces of the second metal sublayer and the fifth metal sublayer can be retained.
  • the second metal sublayer and the fifth metal sublayer The partially remaining third metal sublayer and the fourth metal sublayer on the surface are bonded to each other and the second metal sublayer and the fifth metal sublayer are bonded to each other. Since the second metal sublayer and the fifth metal sublayer and the residual The double bonding of the third metal sublayer and the remaining fourth metal sublayer increases the bonding strength.
  • the surface of the second metal sub-layer facing the third metal sub-layer includes a first wave crest and a first wave trough
  • the fifth metal sub-layer faces the third metal sub-layer.
  • the surface of the fourth metal sub-layer includes a second wave peak and a second wave trough
  • the third metal sub-layer is partially etched away,
  • the fourth metal sublayer is partially etched to expose the first crest and part of the first trough of the second metal sub-layer and leave part of the third metal sub-layer in the rest of the first trough removed to expose the second crest and part of the second trough of the fifth metal sub-layer and part of the fourth metal sub-layer remains in the remaining second trough
  • the exposed first crest and The exposed part of the first wave trough is bonded to the exposed second wave crest and the exposed part of the second wave trough
  • the third metal sublayer remaining in the first wave trough is
  • materials of the first metal sublayer, the third metal sublayer, the fourth metal sublayer and the sixth metal sublayer include titanium.
  • the first metal layer and the second metal layer are three-layer metal structures with the same structure. Since titanium has a certain bonding effect, the second metal sub-layer is directly deposited on the epitaxial structure or the fifth metal sub-layer is directly deposited on the epitaxial structure. The bonding effect is not ideal when the circuit substrate is used.
  • the second metal sublayer and the sixth metal sublayer can be bonded.
  • the epitaxial structure and the functions of the fifth metal sub-layer and the circuit substrate increase the bonding strength between layers.
  • the third metal sublayer and the fourth metal sublayer are titanium metal.
  • titanium metal will protect the second metal sublayer and the fifth metal sublayer, avoiding the second metal sublayer and the fifth metal sublayer.
  • an organic film layer or other impurities are formed or adhered to the surface.
  • the organic film layer will cause the activation of the surface of the second metal sublayer and the fifth metal sublayer to be difficult to handle.
  • a part of the titanium metal of the third metal sublayer and the fourth metal sublayer is reserved, so that the double bonding effect of the second metal sublayer and the fifth metal sublayer and the remaining third metal sublayer and the fourth metal sublayer is increased. bond strength.
  • materials of the second metal sub-layer and the fifth metal sub-layer include one of platinum, gold, copper, and aluminum, and are the same metal.
  • Metals such as platinum, gold, copper, and aluminum are easy to activate, and the activated platinum atoms, gold atoms, copper atoms or aluminum atoms are prone to atomic diffusion to achieve bonding.
  • the roughness of the second metal sublayer and the fifth metal sublayer are both 1 nm-10 nm.
  • the roughness of the second metal sublayer and the fifth metal sublayer will affect the bonding process.
  • the roughness of the second metal sublayer and the fifth metal sublayer is greater than 10 nm, and the roughness is too large.
  • the surface undulation of the metal sub-layer is large, the contact area of the second metal sub-layer and the fifth metal sub-layer when they are butt-bonded to each other is small, which affects the bonding strength, and the roughness of the second metal sub-layer and the fifth metal sub-layer It is less than 1nm, which is not conducive to the adhesion of other materials.
  • the thicknesses of the first metal sublayer and the sixth metal sublayer are both 20nm-100nm.
  • the thickness of the first metal sub-layer and the sixth metal sub-layer is less than 20 nm, the adhesion is weak, the thickness of the first metal sub-layer and the sixth metal sub-layer is greater than 100 nm, the ohmic contact resistance is high, and the thickness of the display panel is increased, It is not conducive to the thinning of the display panel.
  • the thicknesses of the second metal sub-layer and the fifth metal sub-layer are both 50 nm-150 nm.
  • the thickness of the second metal sublayer and the fifth metal sublayer is less than 50 nm, due to the low conductivity of platinum metal in the second metal sublayer and the fifth metal sublayer, the second metal sublayer and the fifth metal sublayer are too thin.
  • the thickness is thin, the resistance of the second metal sublayer and the fifth metal sublayer is large, and the thermal effect is obvious.
  • the thicknesses of the third metal sub-layer and the fourth metal sub-layer before etching are both 10 nm-50 nm.
  • the thickness of the third metal sublayer and the fourth metal sublayer is less than 10 nm, the thickness is too thin, the distribution of the third metal sublayer and the fourth metal sublayer is not uniform, and there may be some areas where the third metal sublayer and the fourth metal sublayer are not deposited.
  • the thicknesses of the third metal sublayer and the fourth metal sublayer are greater than 50 nm, the thickness is too thick, which affects the activation effect of the second metal layer.
  • the step of fabricating the display panel further includes: etching the display panel after peeling off the growth substrate, depositing a passivation layer on the etched outer surface; depositing indium tin oxide on the passivation layer (Indium Tin Oxide, ITO) layer; perform high temperature annealing treatment on the ITO layer.
  • etching the display panel after peeling off the growth substrate, depositing a passivation layer on the etched outer surface; depositing indium tin oxide on the passivation layer (Indium Tin Oxide, ITO) layer; perform high temperature annealing treatment on the ITO layer.
  • ITO Indium Tin Oxide
  • the passivation layer can be a silicon dioxide passivation layer, in the process of annealing ITO at high temperature (at this time, the growth substrate has been peeled off, and there is no delamination problem caused by the large difference in thermal expansion coefficient between the growth substrate and the circuit substrate at high temperature) , the bonding layer is also in a high temperature environment, and the first metal layer and the second metal layer after low temperature bonding can be further bonded and strengthened to enhance the bonding strength.
  • the present application further provides a display panel, characterized in that it includes a plurality of epitaxial structures and a second substrate, and the epitaxial structure array is arranged on the second substrate;
  • Each of the epitaxial structures includes an epitaxial structure and a first metal layer stacked in sequence
  • the second substrate includes a circuit substrate and a second metal layer stacked on the circuit substrate, the first metal layer and the second metal layer are stacked on the circuit substrate.
  • the second metal layer is bonded and connected, wherein the first metal layer is activated and the second metal layer is activated.
  • the first metal layer and the second metal layer are bonded at room temperature. Specifically, atomic diffusion occurs when the first metal layer and the second metal layer are in contact with each other at room temperature, so that the first metal layer and the second metal layer are in contact with each other at room temperature.
  • the two metal layers are bonded to each other to realize bonding, so as to transfer the epitaxial structure to the circuit substrate.
  • the bonding process of the present application is carried out at room temperature, which avoids the delamination problem caused by thermal mismatch due to the large difference in thermal expansion coefficient between the circuit substrate and the growth substrate in the current high-temperature bonding process, which is beneficial to the display performance of the display panel. improvement.
  • the circuit substrate includes a plurality of grooves, and the bottom of each groove is provided with a first electrode; the second metal layer is laminated on the plurality of the circuit substrates and fills the groove and the groove.
  • the first electrode is in contact; the first metal layer and the second metal layer are bonded to form a conductor, and the epitaxial structure is electrically connected to the first electrode through the conductor.
  • the first electrode is a positive electrode
  • the first electrode can be an aluminum electrode
  • the first metal layer and the second metal layer are conductors
  • the epitaxial structure is electrically connected to the first electrode through the conductors to realize the conduction of the circuit and avoid the need to set other
  • the operation of the conductive structure to electrically connect the epitaxial structure and the first electrode simplifies the process and reduces the cost.
  • a side of the epitaxial structure away from the first metal layer is provided with a second electrode, and the epitaxial structure is electrically connected to the second electrode.
  • the two sides of the epitaxial structure are respectively electrically connected with the first electrode and the second electrode to realize the conduction of the circuit.
  • the epitaxial structure includes a P-type epitaxial layer, a multiple quantum well layer, and an N-type epitaxial layer that are stacked in sequence, the P-type epitaxial layer is located on the first metal layer, and the P-type epitaxial layer passes through the layer.
  • the conductor is electrically connected to the first electrode
  • the N-type epitaxial layer is electrically connected to the second electrode
  • the holes of the P-type epitaxial layer and the electrons of the N-type epitaxial layer are in the multiple layers.
  • Quantum well layer recombination produces photons, which are used to emit light.
  • the P-type epitaxial layer is electrically connected to the first electrode through the bonded first metal layer and the second metal layer, and the N-type epitaxial layer is directly electrically connected to the second electrode.
  • the display panel of the present application may adopt a common cathode design.
  • the second electrode is an ITO conductive layer.
  • the present application further provides a display device, including the display panel provided by any of the above-mentioned optional embodiments.
  • FIG. 1 is a schematic structural diagram of a display panel of the present application applied to a display device
  • FIG. 2 is a flowchart of a method for manufacturing a display panel provided by an embodiment of the present application
  • 3a to 3d are schematic structural diagrams of the display panel after each step in FIG. 2 is performed;
  • FIGS. 4a to 4c are schematic diagrams of a partially etched bonding structure according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of bonding after partial etching provided by another embodiment of the present application.
  • FIG. 6 is a flowchart of a method for manufacturing a display panel after epitaxial structure transfer provided by an embodiment of the present application
  • 7a to 7f are schematic structural diagrams of the display panel after each step in FIG. 6 is performed.
  • the epitaxial structure on the growth substrate is generally transferred to the circuit substrate through the wafer bonding technology.
  • the traditional wafer bonding technology often selects metal to bond at 400 °C, and the thermal expansion coefficient of the circuit substrate and the growth substrate is different.
  • the delamination problem caused by thermal mismatch often occurs in the high-temperature bonding process, which affects the display quality.
  • FIG. 1 is a schematic structural diagram of a display panel applied to a display device.
  • the display panel 10 is located in a display device 20, and the display device 20 can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a navigator, and the like.
  • the present application provides a method for manufacturing a display panel.
  • the method for manufacturing a display panel in an embodiment specifically includes the following steps:
  • T10 providing a first substrate and a second substrate.
  • the first substrate 110 includes a growth substrate 111 , an epitaxial structure 112 and a first metal layer 113 stacked in sequence
  • the second substrate 120 includes a circuit substrate 121 and a second metal layer stacked on the circuit substrate 121 122, the epitaxial structure 112 is etched to form a light emitting diode.
  • T20 performing activation treatment on the first metal layer and performing activation treatment on the second metal layer.
  • the growth substrate 111 , the epitaxial structure 112 , the first metal layer 113 , the second metal layer 122 and the circuit substrate 121 are stacked in sequence.
  • the epitaxial structure 112 is transferred to the circuit substrate 121 .
  • the activated first metal layer 113 and the second metal layer 122 are at room temperature Atomic diffusion occurs when they are in contact with each other, so that the first metal layer 113 and the second metal layer 122 are bonded to each other to achieve bonding, so as to transfer the epitaxial structure 112 to the circuit substrate 121 .
  • the bonding process of the present application is performed at room temperature, which avoids the delamination problem caused by thermal mismatch due to the large difference in the thermal expansion coefficients of the circuit substrate 121 and the growth substrate 111 in the current high-temperature bonding process, which is beneficial to the display panel. 10 shows improved performance.
  • the first metal layer 113 includes a first surface 1131 facing away from the growth substrate 111, and the second metal layer 122 includes a second surface 1221 facing away from the circuit substrate 121;
  • Activation treatment at 113 includes activation treatment for the first surface 1131;
  • activation treatment for the second metal layer 122 includes activation treatment for the second surface 1221; bonding the activated first metal layer 113 with the activated second metal layer 113;
  • the second metal layer 122 includes bonding the first surface 1131 and the second surface 1221 .
  • the surface activation treatment method may include ion beam activation.
  • the first surface 1131 and the second surface 1221 are first subjected to activation, the metal atoms of the first surface 1131 and the second surface 1221 are activated, and the first surface 1131 and the second surface 1221 are activated first.
  • the activated metal atoms diffuse to achieve bonding.
  • the first metal layer 113 and the second metal layer 122 of the present application are three-layer metal structures with the same structure, and the first metal layer 113 includes a first metal sub-layer 1132 and a second metal sub-layer 1132 and a second metal layer that are stacked in sequence.
  • the second metal layer 122 includes a fourth metal sub-layer 1222, a fifth metal sub-layer 1223 and The sixth metal sub-layer 1224 , wherein the sixth metal sub-layer 1224 is stacked on the circuit substrate 121 .
  • the first metal sublayer 1132, the second metal sublayer 1133, and the third metal sublayer 1134 may be sequentially deposited on the epitaxial structure 112 by electron beam evaporation technology.
  • the five metal sub-layers 1223 and the sixth metal sub-layer 1224 can be sequentially deposited on the circuit substrate 121 by electron beam evaporation technology.
  • the first metal sublayer 1132 and the third metal sublayer 1134 of the first metal layer 113 and the fourth metal sublayer 1222 and the sixth metal sublayer 1224 of the second metal layer 122 may be titanium.
  • the first metal sub-layer 1132 and the sixth metal sub-layer 1224 are titanium. Since titanium has a certain bonding effect, the second metal sub-layer 1133 is directly deposited on the epitaxial structure 112 or the fifth metal sub-layer 1223 is directly deposited on the circuit substrate 121 When the bonding effect is not ideal, by disposing a layer of titanium metal on the circuit substrate 121 and the epitaxial structure 112 (that is, the first metal sub-layer 1132 and the sixth metal sub-layer 1224 are titanium metal), the second metal sub-layer can be bonded.
  • the role of the layer 1133 and the epitaxial structure 112 and the fifth metal sub-layer 1223 and the circuit substrate 121 increases the bonding strength between layers.
  • the third metal sublayer 1134 and the fourth metal sublayer 1222 are titanium metal.
  • titanium metal will protect the second metal sublayer 1133 and the fifth metal sublayer 1223 to avoid the When the fifth metal sublayer 1223 is directly exposed to the environment, the surface forms or adheres to an organic film layer or other impurities. The organic film layer will cause the activation of the surfaces of the second metal sublayer 1133 and the fifth metal sublayer 1223 to be difficult to handle.
  • a part of the titanium metal of the third metal sublayer 1134 and the fourth metal sublayer 1222 may be retained during the activation process, so that the second metal sublayer 1133 and the fifth metal sublayer 1223 and the remaining third metal sublayer 1134 The double bonding with the remaining fourth metal sublayer 1222 increases the bonding strength.
  • the second metal sub-layer 1133 of the first metal layer 113 and the fifth metal sub-layer 1223 of the second metal layer 122 can be one of platinum, gold, copper, and aluminum, and they are the same metal.
  • Metals such as platinum, gold, copper, and aluminum are easy to activate, and the activated platinum atoms, gold atoms, copper atoms or aluminum atoms are prone to atomic diffusion to achieve bonding.
  • the third metal sublayer 1134 and the fourth metal sublayer 1222 are completely etched away, and the second metal sublayer 1133 Bonding and connection with the fifth metal sublayer 1223 .
  • the third metal sublayer 1134 and the fourth metal sublayer 1222 on the surface layer can be completely etched away.
  • the requirements for etching are small.
  • part of the etching is to ensure that the third metal sub-layer 1134 remaining in the valley is not higher than the peak to ensure that the second metal sub-layer is 1133 and the fifth metal sub-layer 1223 can be in contact with each other, so the control of activation process conditions (such as time) for partial etching is relatively strict, which increases the difficulty of operation, while for complete etching, a longer activation etching time can be selected without considering
  • the residual state of the third metal sub-layer 1134 and the fourth metal sub-layer 1222 has greater process flexibility and is convenient for operation.
  • the third metal sub-layer 1134 is partially etched away, The second metal sub-layer 1133 is exposed, and the fourth metal sub-layer 1222 is partially etched away to expose the fifth metal sub-layer 1223.
  • the remaining third metal sub-layer 1134 is bonded to the remaining fourth metal sub-layer 1222.
  • the exposed second metal sub-layer 1133 is bonded to the exposed fifth metal sub-layer 1223 .
  • the third metal sublayer 1134 and the fourth metal sublayer 1222 on the surface layer will be etched away.
  • the third metal sublayer 1134 and the fourth metal sublayer 1222 may not be completely etched (ie, a part of the third metal sublayer 1134 remains on the first metal layer 113 , and a part of the fourth metal sublayer remains on the second metal layer 122 ) 1222), by controlling the surface roughness of the second metal sub-layer 1133 and the fifth metal sub-layer 1223, the second metal sub-layer 1133 and the fifth metal sub-layer 1223 have greater roughness, so that the second metal sub-layer 1133 and the fifth metal sub-layer 1223 have greater roughness.
  • the surfaces of the layer 1133 and the fifth metal sublayer 1223 have peaks and valleys, and part of the third metal sublayer 1134 and the fourth metal sublayer on the surfaces of the second metal sublayer 1133 and the fifth metal sublayer 1223 can be retained during the activation process.
  • the third metal sublayer 1134 and the fourth metal sublayer 1222 remaining on the surfaces of the second metal sublayer 1133 and the fifth metal sublayer 1223 are bonded to each other and corresponding to the second metal sublayer 1134 and the fourth metal sublayer 1222
  • the metal sublayer 1133 and the fifth metal sublayer 1223 are bonded to each other, due to the double bonding effect of the second metal sublayer 1133 and the fifth metal sublayer 1223 and the remaining third metal sublayer 1134 and the fourth metal sublayer 1222 Increased bond strength.
  • the surface of the second metal sub-layer 1133 facing the third metal sub-layer 1134 includes a first wave peak 1141 and a first wave trough 1142
  • the surface of the fifth metal sub-layer 1223 facing the fourth metal sub-layer 1222 includes a second wave peak 1143 and a second wave trough 1144.
  • the third metal sub-layer Part 1134 is etched away to expose the first crest 1141 and part of the first trough 1142 of the second metal sub-layer 1133 and part of the third metal sub-layer 1134 remains in the remaining first troughs 1142, and the fourth metal sub-layer 1222 is partially etched removed to expose the second crest 1143 and part of the second trough 1144 of the fifth metal sub-layer 1223 and part of the fourth metal sub-layer 1222 remains in the remaining second trough 1144, the exposed first crest 1141 and the exposed part of the first trough 1142 is bonded and connected to the exposed second wave peak 1143 and the exposed part of the second wave valley 1144, and the third metal sub-layer 1134 remaining in the first wave valley 1141 is bonded and connected to the fourth metal sub-layer 1222 remaining in the second wave valley 1144.
  • the roughness of the second metal sub-layer 1133 and the fifth metal sub-layer 1223 is crucial to the bonding process, and the roughness of the second metal sub-layer 1133 and the fifth metal sub-layer 1223 are both 1 nm-10 nm.
  • the roughness of the second metal sub-layer 1133 and the fifth metal sub-layer 1223 will affect the bonding process.
  • the roughness of the second metal sub-layer 1133 and the fifth metal sub-layer 1223 is greater than 10 nm.
  • the surface undulations of the layer 1133 and the fifth metal sub-layer 1223 are relatively large, and the contact area of the second metal sub-layer 1133 and the fifth metal sub-layer 1223 is small when they are butt-bonded to each other, which affects the bonding strength.
  • the second metal sub-layer 1133 When the roughness of the second metal sublayer 1133 and the fifth metal sublayer 1223 is relatively large, the roughness can be reduced by fine polishing; the roughness of the second metal sublayer 1133 and the fifth metal sublayer 1223 is less than 1 nm, which is not conducive to the adhesion of other materials.
  • the first metal layer 113 and the second metal layer 122 of the present application are multi-layer metal structures, and the thicknesses of the first metal layer 113 and the second metal layer 122 can be nano-sized, specifically:
  • the thicknesses of the first metal sub-layer 1132 and the sixth metal sub-layer 1224 are both 20 nm-100 nm.
  • the thickness of the first metal sublayer 1132 and the sixth metal sublayer 1224 is less than 20 nm, and the adhesion is weak; the thickness of the first metal sublayer and the sixth metal sublayer 1224 of 1132 is greater than 100 nm, the ohmic contact resistance is high, and the display is increased.
  • the thickness of the panel is not conducive to the thinning of the display panel.
  • the thicknesses of the second metal sub-layer 1133 and the fifth metal sub-layer 1223 are both 50 nm-150 nm.
  • the thicknesses of the second metal sublayer 1133 and the fifth metal sublayer 1223 are less than 50 nm, due to the low conductivity of platinum metal in the second metal sublayer 1133 and the fifth metal sublayer 1223, the second metal sublayer 1133 and the fifth metal sublayer 1223
  • the resistance of the second metal sublayer 1133 and the fifth metal sublayer 1223 is large and the thermal effect is obvious; when the thickness of the second metal sublayer 1133 and the fifth metal sublayer 1223 is greater than 150 nm, due to the thickness Too thick is not conducive to etching.
  • the thicknesses of the third metal sub-layer 1134 and the fourth metal sub-layer 1222 before etching are both 10 nm-50 nm.
  • the thickness of the third metal sub-layer 1134 and the fourth metal sub-layer 1222 is less than 10 nm, the thickness is too thin, the distribution of the third metal sub-layer 1134 and the fourth metal sub-layer 1222 is not uniform, and there may exist the second metal sub-layer 1133 and the fourth metal sub-layer 1222.
  • the third metal sublayer 1134 and the fourth metal sublayer 1222 are not deposited on the partial area of the five metal sublayers 1223, the second metal sublayer 1133 and the fifth metal sublayer 1223 cannot be fully protected; the third metal sublayer 1223 cannot be fully protected; When the thickness of the layer 1134 and the fourth metal sub-layer 1222 is greater than 50 nm, the thickness is too thick, which affects the activation effect of the second metal layer.
  • the growth substrate 111 can be a sapphire substrate, and the sapphire substrate can be removed by using a laser lift-off technology, the removal process is simple, the removal is clean, and residues are not easy to exist.
  • the growth substrate 111 may also be a gallium nitride substrate, a silicon substrate, a silicon carbide substrate, or the like, and a chemical etching method may be used to peel off the growth substrate. After the growth substrate 111 is peeled off, the epitaxial structure 112 is transferred to the circuit substrate 121 .
  • the steps of fabricating the display panel 10 further include:
  • the epitaxial structure 112 is directionally etched on the N-type epitaxial layer 1123 side of the epitaxial structure 112 by using a colloidal crystal or a photoresist as a mask.
  • the bonded first metal layer 113 and the second metal layer 122 are continuously etched to form independent sub-pixels (ie, the epitaxial structure 130).
  • the epitaxial structure 112 between adjacent independent sub-pixels and the bonded first metal layer 113 and the second metal layer 122 are etched.
  • the epitaxial structure 112 is electrically connected to the first electrode 118 through the bonded first metal layer 113 and the second metal layer 122 .
  • the total thickness of the epitaxial structure 112 is 4.6um-5um.
  • the thicknesses of the first metal layer 113 and the second metal layer 122 after bonding are relatively thin. Simple, this avoids the over-etching effect of plasma gas on the N-type epitaxial layer 1123 caused by etching the gold layer with a thickness of 2um in the traditional technical route, so that the performance of the display panel is not affected.
  • the passivation layer 116 may be silicon dioxide, and the deposition method may be chemical vapor deposition or the like.
  • the passivation layer 116 is partially etched by inductively coupled plasma etching to expose the cathode electrode region (not shown in FIG. 7e) and part of the N-type epitaxial layer 1123 on the circuit.
  • ITO Indium Tin Oxide
  • the ITO conductive layer can be deposited by chemical vapor deposition.
  • the ITO forms a transparent conductive network, which connects the N-type epitaxial layers 1123 of all sub-pixels and the cathode electrode of the circuit.
  • the bonded first metal layer 113 and the first metal layer 113 In the process of annealing ITO at high temperature (at this time, the growth substrate has been peeled off, and there is no delamination problem caused by the large difference in thermal expansion coefficient between the growth substrate and the circuit substrate at high temperature), the bonded first metal layer 113 and the first metal layer 113.
  • the second metal layer 122 is also in a high temperature environment, and the first metal layer 113 and the second metal layer 122 bonded at room temperature can be further bonded and strengthened to enhance the bonding strength.
  • the present application provides a display panel, and the specific structure of the display panel is as follows:
  • FIG. 7c is a schematic structural diagram of the display panel after etching.
  • the display panel 10 includes a plurality of epitaxial structures 130 (the epitaxial structures 130 are the etched epitaxial structures 112 and the first metal layer 113 ) and a second substrate 120 , and the epitaxial structures 130 are arranged in an array on the second substrate 120 , each epitaxial structure 130 includes an epitaxial structure 112 and a first metal layer 113 stacked in sequence, and the second substrate 120 includes a circuit substrate 121 (the circuit substrate 121 may be a glass substrate or a silicon substrate, etc.) and stacked on the circuit substrate 121
  • the second metal layer 122, the first metal layer 113 and the second metal layer 122 are bonded and connected, wherein the first metal layer 113 is subjected to activation treatment and the second metal layer 122 is subjected to activation treatment.
  • the circuit substrate 121 includes a plurality of grooves 1211, the bottom of each groove 1211 is provided with a first electrode 118, the second metal layer 122 is laminated on the plurality of circuit substrates 121, and the filling groove 1211 is in contact with the first electrode 118.
  • a metal layer 113 and a second metal layer 122 are bonded to form a conductor 119 , and the epitaxial structure 112 is electrically connected to the first electrode 118 through the conductor 119 .
  • a second electrode ie, the ITO conductive layer 117
  • the epitaxial structure 112 is electrically connected to the second electrode.
  • the epitaxial structure 112 includes a P-type epitaxial layer 1121, a multiple quantum well layer 1122, and an N-type epitaxial layer 1123 that are stacked in sequence.
  • the P-type epitaxial layer 1121 is located on the first metal layer 113, and the P-type epitaxial layer
  • the holes of the layer 1121 and the electrons of the N-type epitaxial layer 1123 recombine in the multiple quantum well layer 1122 (ie, the light-emitting layer), and after the recombination, photons are generated and light is emitted.
  • the N-type epitaxial layer 1123 is electrically connected to the second electrode (ie the ITO conductive layer 117 ), and the P-type epitaxial layer 1121 is connected to the first metal layer 113 and the second metal layer 122 (ie the conductor 119 ) through the bonded first metal layer 113 and the second metal layer 122 (ie the conductor 119 ).
  • the electrical connection of the electrodes 118 realizes the conduction of the circuit, avoids the operation of providing other conductive structures to electrically connect the epitaxial structure 112 and the first electrode 118, simplifies the process, and reduces the cost.
  • the P-type epitaxial layer 1121 may be P-GaN
  • the N-type epitaxial layer 1123 may be N-GaN
  • the first electrode may be a positive electrode
  • the first electrode may be an aluminum electrode.
  • the present application provides that the first metal layer 113 and the second metal layer 122 are bonded at room temperature. Specifically, atomic diffusion occurs when the first metal layer 113 and the second metal layer 122 are in contact with each other at room temperature, so that the first metal layer 113 and the second metal layer 122 are in contact with each other at room temperature.
  • the metal layer 113 and the second metal layer 122 are bonded to each other to achieve bonding, so as to transfer the epitaxial structure 112 to the circuit substrate 121 .
  • the bonding process of the present application is carried out at room temperature, which avoids the delamination problem caused by thermal mismatch due to the large difference in thermal expansion coefficient between the circuit substrate and the growth substrate in the current high-temperature bonding process, which is beneficial to the display of the display panel 10 Performance improvements.
  • the epitaxial structure 112 is transferred, the epitaxial structure 112 is etched, so that the alignment process in the prior art is not required, and the alignment accuracy of the epitaxial structure transfer in the prior art is reduced.

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Abstract

一种显示面板（10）的制作方法、显示面板（10）及显示装置（20）。显示面板（10）的制作方法通过提供第一基板（110）与第二基板（120），第一基板（110）包括依次层叠设置的生长基板（111）、外延结构（112）以及第一金属层（113），第二基板（120）包括电路基板（121）与层叠在电路基板（121）上的第二金属层（122）；对第一金属层（113）进行活化处理，以及对第二金属层（122）进行活化处理；键合活化处理后的第一金属层（113）与活化处理后的第二金属层（122），以使得生长基板（111）、外延结构（112）、第一金属层（113）、第二金属层（122）以及电路基板（121）依次层叠设置；剥离生长基板（111）。键合工艺是在室温下进行的，避免了目前在高温键合制程中，因电路基板（121）和生长基板（111）的热膨胀系数差异大出现热失配导致的分层问题。

Description

显示面板的制作方法、显示面板及显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种显示面板的制作方法及显示面板、以及包括该显示面板的显示装置。
背景技术
近年来，显示技术不断发展，其中，外延结构通过转移技术转移到电路基板上一直是显示技术领域研究的热点。
目前，一般是通过晶圆键合技术将生长基板上的外延结构转移到电路基板上，然而，传统的晶圆键合技术往往选用金属在400℃下键合，电路基板与生长基板热膨胀系数差异明显，高温键合制程中常常出现热失配导致的分层问题，影响显示质量。
因此，如何实现将生长基板上的外延结构低温转移至电路基板，以避免高温键合出现热失配导致的分层现象是亟需解决的问题。
发明内容
鉴于上述现有技术的不足，本申请的目的在于提供一种显示面板的制作方法及显示面板、以及包括该显示面板的显示装置，旨在解决生长基板上的外延结构高温转移至电路基板时，因电路基板与生长基板热膨胀系数差异明显，在高温键合制程中出现热失配导致的分层问题。
第一方面，本申请提供一种显示面板的制作方法，其特征在于，包括：提供第一基板与第二基板，其中所述第一基板包括依次层叠设置的生长基板、外延结构以及第一金属层，所述第二基板包括电路基板与层叠在所述电路基板上的第二金属层；对所述第一金属层进行活化处理，以及对所述第二金属层进行活化处理；键合活化处理后的所述第一金属层与活化处理后的所述第二金属层，以使得所述生长基板、所述外延结构、所述第一金属层、所述第二金属层以及所述电路基板依次层叠设置；剥离所述生长基板。
本申请通过设置第一金属层和第二金属层，并对第一金属层和第二金属层进行表面活化处理，活化后的第一金属层和第二金属层在室温下相互接触时会发生原子扩散现象，使得第一金属层和第二金属层相互粘接实现键合，以将外延结构转移至电路基板。本申请的键合工艺是在室温下进行的，避免了目前在高温键合制程中，因电路基板和生长基板的热膨胀系数差异大出现热失配导致的分层问题，有利于显示面板显示性能的提高。
可选地，所述第一金属层包括背向所述生长基板的第一表面，所述第二金属 层包括背向所述电路基板的第二表面；对所述第一金属层进行活化处理包括对所述第一表面进行活化处理；对所述第二金属层进行活化处理包括对所述第二表面进行活化处理；键合活化处理后的所述第一金属层与活化处理后的所述第二金属层包括对所述第一表面和所述第二表面进行键合。表面活化处理的方法可以包括离子束活化，表面活化处理的过程中，第一表面和第二表面首先受到活化作用，第一表面和第二表面的金属原子被激活，第一表面和第二表面相互接触时，被激活的金属原子进行扩散实现键合连接。
可选地，所述第一金属层包括依次层叠设置的第一金属子层、第二金属子层以及第三金属子层，所述第一金属子层层叠在所述外延结构上；所述第二金属层包括依次层叠设置的第四金属子层、第五金属子层以及第六金属子层，所述第六金属子层层叠在所述电路基板上；在对所述第一金属层与所述第二金属层活化处理的过程中，所述第三金属子层与所述第四金属子层完全刻蚀掉，所述第二金属子层与所述第五金属子层键合连接。在对第一金属层和第二金属层进行表面活化处理的过程中，表层的第三金属子层和第四金属子层可以完全被刻蚀掉，相对于部分刻蚀，完全刻蚀对工艺的要求较小，例如，通过表面活化处理时间控制刻蚀程度时，部分刻蚀由于要保证残留在波谷的第三金属子层不会高于波峰以保证第二金属子层和第五金属子层可以相互接触，所以部分刻蚀对活化工艺条件(比如时间)的控制较为严格，增加了操作难度，而完全刻蚀可以选择较长的活化刻蚀时间，不用考第三金属子层和第四金属子层的残留状态，工艺灵活性较大，利于操作。
可选地，所述第一金属层包括依次层叠设置的第一金属子层、第二金属子层以及第三金属子层，所述第一金属子层层叠在所述外延结构上；所述第二金属层包括依次层叠设置的第四金属子层、第五金属子层以及第六金属子层，所述第六金属子层层叠在所述电路基板上；在对所述第一金属层与所述第二金属层活化处理的过程中，所述第三金属子层部分刻蚀掉，以露出所述第二金属子层，所述第四金属子层部分刻蚀掉，以露出所述第五金属子层，残留的所述第三金属子层与残留的所述第四金属子层键合连接，露出的所述第二金属子层与露出的所述第五金属子层键合连接。
在对第一金属层和第二金属层进行表面活化处理的过程中，表层的第三金属子层和第四金属子层会被刻蚀掉，通过对表面活化工艺的控制，可以使得第三金属子层和第四金属子层不完全被刻蚀(即第一金属层上保留一部分第三金属子层，第二金属层上保留一部分第四金属子层)，通过对第二金属子层和第五金属子层表面粗糙度的控制，使得第二金属子层和第五金属子层具有较大的粗糙度，这样第二金属子层和第五金属子层的表面具有波峰和波谷，活化的过程中可以保留第二金属子层和第五金属子层表面上的部分第三金属子层和第四金属子层，键合的过程中，第二金属子层和第五金属子层表面上的部分残留的第三金属子层和第四 金属子层相互键合且第二金属子层和第五金属子层相互键合，由于第二金属子层和第五金属子层及残留的第三金属子层和残留的第四金属子层的双重键合作用增加了键合强度。
可选地，具体而言，部分刻蚀的过程中，所述第二金属子层朝向所述第三金属子层的表面包括第一波峰和第一波谷，所述第五金属子层朝向所述第四金属子层的表面包括第二波峰和第二波谷，在对所述第一金属层与所述第二金属层活化处理的过程中，所述第三金属子层部分刻蚀掉，以露出所述第二金属子层的所述第一波峰和部分所述第一波谷且其余所述第一波谷内残留部分所述第三金属子层，所述第四金属子层部分刻蚀掉，以露出所述第五金属子层的所述第二波峰和部分所述第二波谷且其余所述第二波谷内残留部分所述第四金属子层，露出的所述第一波峰和露出的部分所述第一波谷与露出的所述第二波峰和露出的部分所述第二波谷键合连接，所述第一波谷内残留的所述第三金属子层与所述第二波谷内残留的所述第四金属子层键合连接。露出的第二金属子层和露出的第五金属子层及残留的第三金属子层和第四金属子层的双重键合作用增加了键合强度。
可选地，所述第一金属子层、所述第三金属子层、所述第四金属子层和所述第六金属子层的材质包括钛。具体而言，第一金属层和第二金属层为结构相同的三层金属结构，由于钛具有一定的粘接作用，第二金属子层直接沉积在外延结构或第五金属子层直接沉积在电路基板时结合效果不理想，通过在电路基板和外延结构上设置一层钛金属(即第一金属子层和第六金属子层为钛金属)，可以起到粘接第二金属子层和外延结构及第五金属子层和电路基板的作用，增加层间结合强度。第三金属子层和第四金属子层为钛金属，一方面，钛金属会对第二金属子层和第五金属子层起到保护作用，避免第二金属子层和第五金属子层直接暴露在环境时表面形成或者粘附有机膜层或者其他杂质，有机膜层会导致第二金属子层和第五金属子层的表面的活化不易处理，另一方面，活化处理的过程中可以保留一部分第三金属子层和第四金属子层的钛金属，这样第二金属子层和第五金属子层及残留的第三金属子层和第四金属子层的双重键合作用增加了键合强度。
可选地，所述第二金属子层和所述第五金属子层的材质包括铂、金、铜、铝中的一种且为同种金属。铂、金、铜、铝等金属易于活化，活化后的铂原子、金原子、铜原子或者铝原子容易发生原子扩散实现键合连接。
可选地，所述第二金属子层和所述第五金属子层的粗糙度均为1nm-10nm。第二金属子层及第五金属子层的粗糙度会影响键合制程，第二金属子层及第五金属子层的粗糙度大于10nm，粗糙度过大，第二金属子层及第五金属子层的表面起伏较大，第二金属子层及第五金属子层相互对接键合时接触的面积较小，影响键合强度，第二金属子层及第五金属子层的粗糙度小于1nm，不利于其他材料的附着。
可选地，在垂直于所述显示面板所在平面的方向上，所述第一金属子层和所 述第六金属子层的厚度均为20nm-100nm。第一金属子层和第六金属子层的厚度小于20nm，粘接作用较弱，第一金属子层和第六金属子层的厚度大于100nm，欧姆接触电阻高且增加了显示面板的厚度，不利于显示面板的轻薄化。
可选地，在垂直于所述显示面板所在平面的方向上，所述第二金属子层和所述第五金属子层的厚度均为50nm-150nm。第二金属子层和第五金属子层的厚度小于50nm时，由于第二金属子层和第五金属子层的铂金属的电导率较低，第二金属子层和第五金属子层太薄时导致第二金属子层和第五金属子层的电阻大、热效应明显，第二金属子层和第五金属子层的厚度大于150nm时，由于厚度过厚，不利于刻蚀。
可选地，在垂直于所述显示面板所在平面的方向上，未刻蚀前的所述第三金属子层和所述第四金属子层的厚度均为10nm-50nm。第三金属子层和第四金属子层的厚度小于10nm时，厚度过薄，第三金属子层和第四金属子层分布不均匀，可能存在部分区域没有沉积上第三金属子层和第四金属子层的情况，第三金属子层和第四金属子层的厚度大于50nm时，厚度过厚，影响对第二金属层的活化效果。
可选地，制作所述显示面板的步骤还包括：对剥离生长基板后的显示面板进行刻蚀，在经过刻蚀处理的外表面沉积钝化层；在所述钝化层上沉积氧化铟锡(Indium Tin Oxide，ITO)层；对所述ITO层进行高温退火处理。钝化层可以为二氧化硅钝化层，对ITO进行高温退火的过程中(此时，生长基板已经被剥离，不存在高温时因生长基板和电路基板热膨胀系数差异大造成的分层问题)，键合层也处于高温环境中，可以对低温键合后的第一金属层和第二金属层进行进一步的键合加固，增强键合强度。
第二方面，基于同样的发明构思，本申请还提供一种显示面板，其特征在于，包括多个磊晶结构和第二基板，所述磊晶结构阵列排布于所述第二基板上；每个所述磊晶结构包括依次层叠设置的外延结构以及第一金属层，所述第二基板包括电路基板与层叠在所述电路基板上的第二金属层，所述第一金属层与所述第二金属层键合连接，其中，所述第一金属层经过活化处理且所述第二金属层经过活化处理。
本申请设置第一金属层和第二金属层在室温下键合，具体而言，第一金属层和第二金属层在室温下相互接触时会发生原子扩散现象，使得第一金属层和第二金属层相互粘接实现键合，以将外延结构转移至电路基板。本申请的键合工艺是在室温下进行的，避免了目前在高温键合制程中，因电路基板和生长基板的热膨胀系数差异大出现热失配导致的分层问题，有利于显示面板显示性能的提高。
可选地，所述电路基板包括多个凹槽，每个所述凹槽的底部设置有第一电极；所述第二金属层层叠在多个所述电路基板上且填充所述凹槽与所述第一电极接触；所述第一金属层和所述第二金属层键合后形成导电体，所述外延结构通过所 述导电体与所述第一电极电连接。第一电极为正极，第一电极可以为铝电极，第一金属层和第二金属层为导电体，外延结构通过导电体与第一电极电连接，实现电路的导通，避免了需要设置其它导电结构以将外延结构和第一电极电连接的操作，简化了工艺，降低了成本。
可选地，所述外延结构背离所述第一金属层的一侧设有第二电极，所述外延结构与所述第二电极电连接。外延结构的两侧分别实现与第一电极和第二电极的电连接，实现电路的导通。
可选地，所述外延结构包括依次层叠设置的P型外延层、多量子阱层和N型外延层，所述P型外延层位于所述第一金属层上，所述P型外延层通过所述导电体与所述第一电极电连接，所述N型外延层与所述第二电极电连接，所述P型外延层的空穴与所述N型外延层的电子在所述多量子阱层复合产生光子，所述光子用于发光。P型外延层通过键合后的第一金属层和第二金属层实现与第一电极的电连接，N型外延层直接与第二电极电连接，本申请的显示面板可以采用共阴极设计，第二电极为ITO导电层。
第三方面，基于同样的发明构思，本申请还提供一种显示装置，包括上述任一种可选地实施方式提供的显示面板。
附图说明
图1为本申请显示面板应用于显示装置的结构示意图；
图2为本申请一种实施方式提供的显示面板的制作方法流程图；
图3a至图3d为执行图2中的各步骤后显示面板的结构示意图；
图4a至图4c为本申请一种实施方式提供的部分刻蚀后的键合结构示意图；
图5为本申请另一种实施方式提供的部分刻蚀后的键合结合示意图；
图6为本申请一种实施方式提供的外延结构转移后的显示面板制作方法流程图；
图7a至图7f为执行图6中的各步骤后显示面板的结构示意图。
附图标记说明：
10-显示面板；20-显示装置；110-第一基板；120-第二基板；111-生长基板；112-外延结构；113-第一金属层；121-电路基板；122-第二金属层；1131-第一表面；1221-第二表面；1132-第一金属子层；1133-第二金属子层；1134-第三金属子层；1222-第四金属子层；1223-第五金属子层；1224-第六金属子层；1141-第一波峰；1142-第一波谷；1143-第二波峰；1144-第二波谷；1121-P型外延层；1122-多量子阱层；1123-N型外延层；116-钝化层；117-ITO导电层；118-第一电极；119-导电体；1211-凹槽；130-磊晶结构。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的较佳实施方式。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施方式。相反地，提供这些实施方式的目的是使对本申请的公开内容理解的更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施方式的目的，不是旨在于限制本申请。
目前，一般是通过晶圆键合技术将生长基板上的外延结构转移到电路基板上，然而，传统的晶圆键合技术往往选用金属在400℃下键合，电路基板与生长基板热膨胀系数差异明显，高温键合制程中常常出现热失配导致的分层问题，影响显示质量。
基于此，本申请希望提供一种能够解决上述技术问题的方案，其详细内容将在后续实施例中得以阐述。
本申请提供一种显示面板的制作方法及显示面板、以及包括该显示面板的显示装置。请参阅图1，图1是显示面板应用于显示装置的结构示意图。显示面板10位于显示装置20内，显示装置20可以为手机、平板电脑、电视机、显示器、笔记本电脑、导航仪等任何具有显示功能的产品或部件。
首先，本申请提供一种显示面板的制作方法，如图2所示，一种实施方式中的显示面板的制作方法具体包括以下步骤：
T10、提供第一基板和第二基板。
参阅图3a和图3b，第一基板110包括依次层叠设置的生长基板111、外延结构112以及第一金属层113，第二基板120包括电路基板121与层叠在电路基板121上的第二金属层122，外延结构112刻蚀后形成发光二极管。
T20、对第一金属层进行活化处理且对第二金属层进行活化处理。
T30、键合活化处理后的第一金属层和活化处理后的第二金属层。
请参阅图3c，键合第一金属层113和第二金属层122后使得生长基板111、外延结构112、第一金属层113、第二金属层122以及电路基板121依次层叠设置。
T40、剥离生长基板。
请参阅图3d，剥离生长基板111之后，外延结构112就转移到了电路基板121上。
本申请通过提供第一金属层113和第二金属层122，并对第一金属层113和第二金属层122进行表面活化处理，活化后的第一金属层113和第二金属层122在室温下相互接触时会发生原子扩散现象，使得第一金属层113和第二金属层122相互粘接实现键合，以将外延结构112转移至电路基板121。本申请的键合 工艺是在室温下进行的，避免了目前在高温键合制程中，因电路基板121和生长基板111的热膨胀系数差异大出现热失配导致的分层问题，有利于显示面板10显示性能的提高。
具体而言，参阅图3a和图3b，第一金属层113包括背向生长基板111的第一表面1131，第二金属层122包括背向电路基板121的第二表面1221；对第一金属层113进行活化处理包括对第一表面1131进行活化处理；对第二金属层122进行活化处理包括对第二表面1221进行活化处理；键合活化处理后的第一金属层113与活化处理后的第二金属层122包括对所述第一表面1131和所述第二表面1221进行键合。表面活化处理的方法可以包括离子束活化，表面活化处理的过程中，第一表面1131和第二表面1221首先受到活化作用，第一表面1131和第二表面1221的金属原子被激活，第一表面1131和第二表面1221相互接触时，被激活的金属原子进行扩散实现键合粘接。
参阅图4a和图4b，本申请的第一金属层113和第二金属层122为结构相同的三层金属结构，第一金属层113包括依次层叠设置的第一金属子层1132、第二金属子层1133以及第三金属子层1134，其中，第一金属子层1132层叠在外延结构112上；第二金属层122包括依次层叠设置的第四金属子层1222、第五金属子层1223以及第六金属子层1224，其中，第六金属子层1224层叠在电路基板121上。
一种可能的实施方式中，第一金属子层1132、第二金属子层1133以及第三金属子层1134可以通过电子束蒸发技术依次沉积到外延结构112上，第四金属子层1222、第五金属子层1223以及第六金属子层1224可以通过电子束蒸发技术依次沉积到电路基板121上。
第一金属层113的第一金属子层1132和第三金属子层1134及第二金属层122的第四金属子层1222和第六金属子层1224可以为钛。第一金属子层1132和第六金属子层1224为钛，由于钛具有一定的粘接作用，第二金属子层1133直接沉积在外延结构112或第五金属子层1223直接沉积在电路基板121时结合效果不理想，通过在电路基板121和外延结构112上设置一层钛金属(即第一金属子层1132和第六金属子层1224为钛金属)，可以起到粘接第二金属子层1133和外延结构112及第五金属子层1223和电路基板121的作用，增加层间结合强度。第三金属子层1134和第四金属子层1222为钛金属，一方面，钛金属会对第二金属子层1133和第五金属子层1223起到保护作用，避免第二金属子层1133和第五金属子层1223直接暴露在环境时表面形成或者粘附有机膜层或者其他杂质，有机膜层会导致第二金属子层1133和第五金属子层1223的表面的活化不易处理，另一方面，活化处理的过程中可以保留一部分第三金属子层1134和第四金属子层1222的钛金属，这样第二金属子层1133和第五金属子层1223及残留的第三金属子层1134和残留的第四金属子层1222的双重键合作用增加了键合强度。
第一金属层113的第二金属子层1133及第二金属层122的第五金属子层1223可以为铂、金、铜、铝中的一种且为同种金属。铂、金、铜、铝等金属易于活化，活化后的铂原子、金原子、铜原子或者铝原子容易发生原子扩散实现键合连接。
本申请的第一金属层113和第二金属层122键合连接的过程中有两种不同的键合方案，具体包括：
第一种方案，在对第一金属层113与第二金属层122进行表面活化处理的过程中，第三金属子层1134与第四金属子层1222完全刻蚀掉，第二金属子层1133与第五金属子层1223键合连接。
在对第一金属层113和第二金属层122进行表面活化处理的过程中，表层的第三金属子层1134和第四金属子层1222可以完全被刻蚀掉，相对于部分刻蚀，完全刻蚀对工艺的要求较小，例如，通过表面活化处理时间控制刻蚀程度时，部分刻蚀由于要保证残留在波谷的第三金属子层1134不会高于波峰以保证第二金属子层1133和第五金属子层1223可以相互接触，所以部分刻蚀对活化工艺条件(比如时间)的控制较为严格，增加了操作难度，而完全刻蚀可以选择较长的活化刻蚀时间，不用考第三金属子层1134和第四金属子层1222的残留状态，工艺灵活性较大，利于操作。
第二种方案，参阅图4a、图4b、图4c和图5，在对第一金属层113与第二金属层122进行表面活化处理的过程中，第三金属子层1134部分刻蚀掉，以露出第二金属子层1133，第四金属子层1222部分刻蚀掉，以露出第五金属子层1223，残留的第三金属子层1134与残留的第四金属子层1222键合连接，露出第二金属子层1133与露出的第五金属子层1223键合连接。
在对第一金属层113和第二金属层122进行表面活化处理的过程中，表层的第三金属子层1134和第四金属子层1222会被刻蚀掉，通过对表面活化工艺的控制，可以使得第三金属子层1134和第四金属子层1222不完全被刻蚀(即第一金属层113上保留一部分第三金属子层1134，第二金属层122上保留一部分第四金属子层1222)，通过对第二金属子层1133和第五金属子层1223表面粗糙度的控制，使得第二金属子层1133和第五金属子层1223具有较大的粗糙度，这样第二金属子层1133和第五金属子层1223的表面具有波峰和波谷，活化的过程中可以保留第二金属子层1133和第五金属子层1223表面上的部分第三金属子层1134和第四金属子层1222，键合的过程中，第二金属子层1133和第五金属子层1223表面上的部分残留的第三金属子层1134和第四金属子层1222相互键合且相对应的第二金属子层1133和第五金属子层1223相互键合，由于第二金属子层1133和第五金属子层1223及残留的第三金属子层1134和第四金属子层1222的双重键合作用增加了键合强度。
可以理解的，参阅图4a、图4b、图4c和图5，部分刻蚀的过程中，第二金属子层1133朝向第三金属子层1134的表面包括第一波峰1141和第一波谷1142， 第五金属子层1223朝向第四金属子层1222的表面包括第二波峰1143和第二波谷1144，在对第一金属层113与第二金属层122活化处理的过程中，第三金属子层1134部分刻蚀掉，以露出第二金属子层1133的第一波峰1141和部分第一波谷1142且其余第一波谷1142内残留部分第三金属子层1134，第四金属子层1222部分刻蚀掉，以露出第五金属子层1223的第二波峰1143和部分第二波谷1144且其余第二波谷内1144残留部分第四金属子层1222，露出的第一波峰1141和露出的部分第一波谷1142与露出的第二波峰1143和露出的部分第二波谷1144键合连接，第一波谷1141内残留的第三金属子层1134与第二波谷1144内残留的第四金属子层1222键合连接。
第二金属子层1133及第五金属子层1223的粗糙度对键合工艺是至关重要的，第二金属子层1133及第五金属子层1223的粗糙度均为1nm-10nm。第二金属子层1133及第五金属子层1223的粗糙度会影响键合制程，第二金属子层1133及第五金属子层1223的粗糙度大于10nm，粗糙度过大，第二金属子层1133及第五金属子层1223的表面起伏较大，第二金属子层1133及第五金属子层1223相互对接键合时接触的面积较小，影响键合强度，第二金属子层1133及第五金属子层1223的粗糙度较大时，可以采用精抛的方式降低粗糙度；第二金属子层1133及第五金属子层1223的粗糙度小于1nm，不利于其他材料的附着。
本申请的第一金属层113和第二金属层122为多层金属结构，第一金属层113和第二金属层122的厚度可以做到纳米尺寸，具体而言：
在垂直于显示面板所在平面的方向上，第一金属子层1132和第六金属子层1224的厚度均为20nm-100nm。第一金属子层1132和第六金属子层1224的厚度小于20nm，粘接作用较弱；第一金属子层和1132第六金属子层1224的厚度大于100nm，欧姆接触电阻高且增加了显示面板的厚度，且不利于显示面板的轻薄化。
在垂直于显示面板所在平面的方向上，第二金属子层1133和第五金属子层1223的厚度均为50nm-150nm。第二金属子层1133和第五金属子层1223的厚度小于50nm时，由于第二金属子层1133和第五金属子层1223的铂金属的电导率较低，第二金属子层1133和第五金属子层1223太薄时导致第二金属子层1133和第五金属子层1223的电阻大、热效应明显；第二金属子层1133和第五金属子层1223的厚度大于150nm时，由于厚度过厚，不利于刻蚀。
在垂直于显示面板所在平面的方向上，未刻蚀前的第三金属子层1134和第四金属子层1222的厚度均为10nm-50nm。第三金属子层1134和第四金属子层1222的厚度小于10nm时，厚度过薄，第三金属子层1134和第四金属子层1222分布不均匀，可能存在第二金属子层1133和第五金属子层1223部分区域没有沉积上第三金属子层1134和第四金属子层1222的情况，不能实现对第二金属子层1133和第五金属子层1223的完全保护；第三金属子层1134和第四金属子层1222 的厚度大于50nm时，厚度过厚，影响对第二金属层的活化效果。
生长基板111可以为蓝宝石基板，蓝宝石基板可以采用激光剥离技术去除，去除工艺简单，去除干净，不易存在残留。其他实施方式中，生长基板111也可以为氮化镓基板或硅基板或碳化硅基板等，可以采用化学刻蚀法进行生长基板的剥离。生长基板111剥离之后外延结构112就转移到了电路基板121上。
剥离生长基板111之后，参阅图6，制作显示面板10的步骤还包括：
S110、对外延结构进行刻蚀处理。
参阅图7a和图7b，在外延结构112的N型外延层1123侧通过胶体晶体或者光刻胶作为掩膜，对外延结构112进行定向刻蚀。
S120、对键合后的第一金属层与第二金属层进行刻蚀处理。
参阅图7c，对外延结构112进行刻蚀后继续对键合后的第一金属层113与第二金属层122进行刻蚀处理以形成独立的子像素(即磊晶结构130)。换言之，对相邻的独立子像素之间的外延结构112和键合后的第一金属层113与第二金属层122进行刻蚀处理。外延结构112通过键合后的第一金属层113与第二金属层122与第一电极118电连接。
一般而言，外延结构112的总厚度在4.6um-5um，此外，由于采用低温，键合后的第一金属层113与第二金属层122的厚度较薄，采用感应耦合等离子体刻蚀相对简单，这就避免传统技术路线中刻蚀厚度为2um的金层而出现等离子气体对N型外延层1123的过刻蚀效应，从而不影响显示面板的性能。
S130、在经过刻蚀处理的外表面沉积钝化层。
参阅图7d，钝化层116可以为二氧化硅，沉积的方式可以为化学气相沉积等。
S140、对钝化层进行局部刻蚀处理。
参阅图7e，通过感应耦合等离子体刻蚀对钝化层116进行局部刻蚀处理，以将电路上的阴极电极区(图7e未示)及部分N型外延层1123露出。
S150、在钝化层上沉积氧化铟锡(Indium Tin Oxide，ITO)导电层，并对ITO导电层进行高温退火处理。
参阅图7f，可以采用化学气相沉积的方式沉积ITO导电层，通过共阴极设计，使ITO形成透明导电网络，将所有子像素的N型外延层1123相连，并与电路的阴极电极相连接。
对ITO进行高温退火的过程中(此时，生长基板已经被剥离，不存在高温时因生长基板和电路基板热膨胀系数差异大造成的分层问题)，键合后的第一金属层113与第二金属层122也处于高温环境中，可以对室温键合的第一金属层113与第二金属层122进行进一步的键合加固，增强键合强度。
其次，基于同样的发明构思，本申请提供一种显示面板，显示面板的具体结构如下：
如图7c所示，图7c为刻蚀之后的显示面板的结构示意图。显示面板10包 括多个磊晶结构130(磊晶结构130即为刻蚀后的外延结构112和第一金属层113)和第二基板120，磊晶结构130阵列排布于第二基板120上，每个磊晶结构130包括依次层叠设置的外延结构112以及第一金属层113，第二基板120包括电路基板121(电路基板121可以为玻璃基板或者硅基板等)与层叠在电路基板121上的第二金属层122，第一金属层113与第二金属层122键合连接，其中，第一金属层113经过活化处理且第二金属层122经过活化处理。
电路基板121包括多个凹槽1211，每个凹槽1211的底部设置有第一电极118，第二金属层122层叠在多个电路基板121上且填充凹槽1211与第一电极118接触，第一金属层113和第二金属层122键合后形成导电体119，外延结构112通过导电体119与第一电极118电连接。外延结构112背离第一金属层113的一侧设有第二电极(即ITO导电层117)，外延结构112与第二电极电连接。
具体而言，参阅图7f，外延结构112包括依次层叠设置的P型外延层1121、多量子阱层1122和N型外延层1123，P型外延,1121位于第一金属层113上，P型外延层1121的空穴与N型外延层1123的电子在多量子阱层1122(即发光层)复合，复合之后产生光子并发光。N型外延层1123与第二电极(即ITO导电层117)电连接，P型外延层1121通过键合后的第一金属层113和第二金属层122(即导电体119)实现与第一电极118的电连接，实现电路的导通，避免了需要设置其它导电结构以将外延结构112和第一电极118电连接的操作，简化了工艺，降低了成本。
具体地，P型外延层1121可以为P-GaN，N型外延层1123可以为N-GaN，第一电极为正极，第一电极可以为铝电极。
本申请设置第一金属层113和第二金属层122在室温下键合，具体而言，第一金属层113和第二金属层122在室温下相互接触时会发生原子扩散现象，使得第一金属层113和第二金属层122相互粘接实现键合，以将外延结构112转移至电路基板121。本申请的键合工艺是在室温下进行的，避免了目前在高温键合制程中，因电路基板和生长基板的热膨胀系数差异大出现热失配导致的分层问题，有利于显示面板10显示性能的提高。本申请在转移外延结构112后，对外延结构112进行刻蚀，这样不需要现有技术中进行对位的工艺，降低了现有技术中外延结构转移的对位精度的问题。
应当理解的是，本发明的应用不限于上述的举例，对本领域普通技术人员来说，可以根据上述说明加以改进或变换，所有这些改进和变换都应属于本发明所附权利要求的保护范围。

Claims (16)

  1. 一种显示面板的制作方法，其特征在于，包括：
    提供第一基板与第二基板，其中所述第一基板包括依次层叠设置的生长基板、外延结构以及第一金属层，所述第二基板包括电路基板与层叠在所述电路基板上的第二金属层；
    对所述第一金属层进行活化处理，以及对所述第二金属层进行活化处理；
    键合活化处理后的所述第一金属层与活化处理后的所述第二金属层，以使得所述生长基板、所述外延结构、所述第一金属层、所述第二金属层以及所述电路基板依次层叠设置；
    剥离所述生长基板。
  2. 如权利要求1所述的显示面板的制作方法，其特征在于，所述第一金属层包括背向所述生长基板的第一表面，所述第二金属层包括背向所述电路基板的第二表面；
    对所述第一金属层进行活化处理包括：对所述第一表面进行活化处理；对所述第二金属层进行活化处理包括：对所述第二表面进行活化处理；
    键合活化处理后的所述第一金属层与活化处理后的所述第二金属层包括：对所述第一表面和所述第二表面进行键合。
  3. 如权利要求1所述的显示面板的制作方法，其特征在于，所述第一金属层包括依次层叠设置的第一金属子层、第二金属子层以及第三金属子层，所述第一金属子层层叠在所述外延结构上；所述第二金属层包括依次层叠设置的第四金属子层、第五金属子层以及第六金属子层，所述第六金属子层层叠在所述电路基板上；在对所述第一金属层与所述第二金属层活化处理的过程中，所述第三金属子层与所述第四金属子层完全刻蚀掉，所述第二金属子层与所述第五金属子层键 合连接。
  4. 如权利要求1所述的显示面板的制作方法，其特征在于，所述第一金属层包括依次层叠设置的第一金属子层、第二金属子层以及第三金属子层，所述第一金属子层层叠在所述外延结构上；所述第二金属层包括依次层叠设置的第四金属子层、第五金属子层以及第六金属子层，所述第六金属子层层叠在所述电路基板上；在对所述第一金属层与所述第二金属层活化处理的过程中，所述第三金属子层部分刻蚀掉，以露出所述第二金属子层，所述第四金属子层部分刻蚀掉，以露出所述第五金属子层，残留的所述第三金属子层与残留的所述第四金属子层键合连接，露出的所述第二金属子层与露出的所述第五金属子层键合连接。
  5. 如权利要求4所述的显示面板的制作方法，其特征在于，所述第二金属子层朝向所述第三金属子层的表面包括第一波峰和第一波谷，所述第五金属子层朝向所述第四金属子层的表面包括第二波峰和第二波谷，在对所述第一金属层与所述第二金属层活化处理的过程中，所述第三金属子层部分刻蚀掉，以露出所述第二金属子层的所述第一波峰和部分所述第一波谷且其余所述第一波谷内残留部分所述第三金属子层，所述第四金属子层部分刻蚀掉，以露出所述第五金属子层的所述第二波峰和部分所述第二波谷且其余所述第二波谷内残留部分所述第四金属子层，露出的所述第一波峰和露出的部分所述第一波谷与露出的所述第二波峰和露出的部分所述第二波谷键合连接，所述第一波谷内残留的所述第三金属子层与所述第二波谷内残留的所述第四金属子层键合连接。
  6. 如权利要求3至5任一项所述的显示面板的制作方法，其特征在于，所述第一金属子层、所述第三金属子层、所述第四金属子层和所述第六金属子层的材质包括钛。
  7. 如权利要求3至5任一项所述的显示面板的制作方法，其特征在于，所述第二金属子层和所述第五金属子层的材质包括铂、金、铜、铝中的一种且为同 种金属。
  8. 如权利要求3至5任一项所述的显示面板的制作方法，其特征在于，所述第二金属子层和所述第五金属子层的粗糙度均为1nm-10nm。
  9. 如权利要求3至5任一项所述的显示面板的制作方法，其特征在于，在垂直于所述显示面板所在平面的方向上，所述第一金属子层和所述第六金属子层的厚度均为20nm-100nm。
  10. 如权利要求3至5任一项所述的显示面板的制作方法，其特征在于，在垂直于所述显示面板所在平面的方向上，所述第二金属子层和所述第五金属子层的厚度均为50nm-150nm。
  11. 如权利要求3至5任一项所述的显示面板的制作方法，其特征在于，在垂直于所述显示面板所在平面的方向上，未刻蚀前的所述第三金属子层和所述第四金属子层的厚度均为10nm-50nm。
  12. 一种显示面板，其特征在于，包括多个磊晶结构和第二基板，所述磊晶结构阵列排布于所述第二基板上；每个所述磊晶结构包括依次层叠设置的外延结构以及第一金属层，所述第二基板包括电路基板与层叠在所述电路基板上的第二金属层，所述第一金属层与所述第二金属层键合连接，其中，所述第一金属层经过活化处理且所述第二金属层经过活化处理。
  13. 如权利要求12所述的显示面板，其特征在于，所述电路基板包括多个凹槽，每个所述凹槽的底部设置有第一电极；所述第二金属层层叠在多个所述电路基板上且填充所述凹槽与所述第一电极接触；
    所述第一金属层和所述第二金属层键合后形成导电体，所述外延结构通过所述导电体与所述第一电极电连接。
  14. 如权利要求13所述的显示面板，其特征在于，所述外延结构背离所述第一金属层的一侧设有第二电极，所述外延结构与所述第二电极电连接。
  15. 如权利要求14所述的显示面板，其特征在于，所述外延结构包括依次层叠设置的P型外延层、多量子阱层和N型外延层，所述P型外延层位于所述第一金属层上，所述P型外延层通过所述导电体与所述第一电极电连接，所述N型外延层与所述第二电极电连接，所述P型外延层的空穴与所述N型外延层的电子在所述多量子阱层复合产生光子，所述光子用于发光。
  16. 一种显示装置，其特征在于，包括如权利要求12至15任一项所述的显示面板。
PCT/CN2020/099791 2020-07-01 2020-07-01 显示面板的制作方法、显示面板及显示装置 WO2022000385A1 (zh)

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Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102712126B1 (ko) * 2023-02-21 2024-09-30 웨이브로드 주식회사 마이크로디스플레이 패널 제조 방법

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001060602A (ja) * 1999-08-23 2001-03-06 Fuji Electric Co Ltd フリップチップ実装構造及びその製造方法
US20050112340A1 (en) * 2003-11-24 2005-05-26 Su-Tsai Lu Bonding structure with buffer layer and method of forming the same
CN102629656A (zh) * 2012-03-15 2012-08-08 苏州晶品光电科技有限公司 一种具有高散热效果的led封接结构及其封接方法
CN103887377A (zh) * 2014-03-12 2014-06-25 江苏新广联科技股份有限公司 减少GaN基垂直结构LED漏电的器件工艺
CN108140559A (zh) * 2015-08-25 2018-06-08 英帆萨斯邦德科技有限公司 传导阻障直接混合型接合
WO2019160690A1 (en) * 2018-02-15 2019-08-22 Invensas Bonding Technologies, Inc. Techniques for processing devices
CN110494983A (zh) * 2017-03-16 2019-11-22 伊文萨思公司 直接键合的led阵列和应用
CN110707186A (zh) * 2019-10-21 2020-01-17 深圳市华星光电半导体显示技术有限公司 Led显示面板的制备方法
CN111048634A (zh) * 2019-12-26 2020-04-21 重庆康佳光电技术研究院有限公司 一种Micro LED转移方法及背板

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100521171C (zh) 2004-10-21 2009-07-29 财团法人工业技术研究院 一种元件的封装接合结构
JP4906256B2 (ja) 2004-11-10 2012-03-28 株式会社沖データ 半導体複合装置の製造方法
US7550366B2 (en) 2005-12-02 2009-06-23 Ayumi Industry Method for bonding substrates and device for bonding substrates
DE102013101367A1 (de) * 2013-02-12 2014-08-14 Osram Opto Semiconductors Gmbh Halbleiterchip
WO2015012108A1 (ja) 2013-07-26 2015-01-29 コニカミノルタ株式会社 電子デバイスおよびその製造方法
CN105161515B (zh) 2015-08-11 2018-03-23 京东方科技集团股份有限公司 有机发光二极管显示面板及其封装方法、显示装置
CN108781064B (zh) 2016-03-25 2019-10-11 日本碍子株式会社 接合方法
CN106571334B (zh) 2016-10-26 2020-11-10 上海集成电路研发中心有限公司 一种硅片间的混合键合方法
US10629577B2 (en) * 2017-03-16 2020-04-21 Invensas Corporation Direct-bonded LED arrays and applications
CN109830566A (zh) 2018-12-29 2019-05-31 中国电子科技集团公司第十八研究所 一种制备高效五结太阳电池的低温半导体键合方法
CN111192831B (zh) 2020-03-05 2022-11-04 哈尔滨工业大学（威海） 一种用于高导热氮化硅陶瓷基板的金属化方法及其封装基板

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001060602A (ja) * 1999-08-23 2001-03-06 Fuji Electric Co Ltd フリップチップ実装構造及びその製造方法
US20050112340A1 (en) * 2003-11-24 2005-05-26 Su-Tsai Lu Bonding structure with buffer layer and method of forming the same
CN102629656A (zh) * 2012-03-15 2012-08-08 苏州晶品光电科技有限公司 一种具有高散热效果的led封接结构及其封接方法
CN103887377A (zh) * 2014-03-12 2014-06-25 江苏新广联科技股份有限公司 减少GaN基垂直结构LED漏电的器件工艺
CN108140559A (zh) * 2015-08-25 2018-06-08 英帆萨斯邦德科技有限公司 传导阻障直接混合型接合
CN110494983A (zh) * 2017-03-16 2019-11-22 伊文萨思公司 直接键合的led阵列和应用
WO2019160690A1 (en) * 2018-02-15 2019-08-22 Invensas Bonding Technologies, Inc. Techniques for processing devices
CN110707186A (zh) * 2019-10-21 2020-01-17 深圳市华星光电半导体显示技术有限公司 Led显示面板的制备方法
CN111048634A (zh) * 2019-12-26 2020-04-21 重庆康佳光电技术研究院有限公司 一种Micro LED转移方法及背板

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